Searched refs:pl (Results 51 - 75 of 136) sorted by path

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/linux-master/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_submission.c1771 struct list_head *pl; local
1792 pl = i915_sched_lookup_priolist(sched_engine, prio);
1796 list_add(&rq->sched.link, pl);
5428 struct i915_priolist *pl = to_priolist(rb); local
5431 priolist_for_each_request(rq, pl)
/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_plane.c30 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\
31 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
33 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
34 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
/linux-master/drivers/gpu/drm/nouveau/
H A Dnouveau_bo.c442 struct ttm_place *pl = nvbo->placements; local
448 pl[*n].mem_type = TTM_PL_VRAM;
449 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_VRAM ?
454 pl[*n].mem_type = TTM_PL_TT;
455 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_GART ?
460 pl[*n].mem_type = TTM_PL_SYSTEM;
461 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_CPU ?
795 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) argument
809 *pl = nvbo->placement;
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.c36 static u32 pl_to_div(u32 pl) argument
38 if (pl >= ARRAY_SIZE(_pl_to_div))
41 return _pl_to_div[pl];
46 u32 pl; local
48 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) {
49 if (_pl_to_div[pl] >= div)
50 return pl;
73 pll->pl
111 u32 pl; local
[all...]
H A Dgk20a.h113 u32 pl; member in struct:gk20a_pll
H A Dgm20b.c141 static u32 pl_to_div(u32 pl) argument
143 return pl;
389 u32 old = cur_pll.base.pl;
390 u32 new = pll->pl;
399 cur_pll.base.pl = min(old | BIT(ffs(new) - 1),
404 cur_pll.base.pl = new;
442 if (pll->m == cur_pll.m && pll->pl == cur_pll.pl)
505 pll->pl = DIV_ROUND_UP(nmin * parent_rate, pll->m * rate);
/linux-master/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c1241 struct rv7xx_pl *pl)
1244 if ((pl->mclk == 0) || (pl->sclk == 0))
1247 if (pl->mclk == pl->sclk)
1250 if (pl->mclk > pl->sclk) {
1251 if (((pl->mclk + (pl->sclk - 1)) / pl
1239 btc_adjust_clock_combinations(struct radeon_device *rdev, const struct radeon_clock_and_voltage_limits *max_limits, struct rv7xx_pl *pl) argument
2711 struct rv7xx_pl *pl; local
2736 struct rv7xx_pl *pl; local
2759 struct rv7xx_pl *pl; local
[all...]
H A Dci_dpm.c5436 struct ci_pl *pl = &ps->performance_levels[index]; local
5440 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5441 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5442 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5443 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5445 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
5449 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
5454 pi->acpi_pcie_gen = pl->pcie_gen;
5459 pi->ulv.pl = *pl;
5927 struct ci_pl *pl; local
[all...]
H A Dci_dpm.h94 struct ci_pl pl; member in struct:ci_ulv_parm
H A Dcypress_dpm.c679 struct rv7xx_pl *pl,
689 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
690 level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
691 level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
694 ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk);
700 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
710 if (pl->mclk > pi->mclk_edc_enable_threshold)
713 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
716 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
719 if (cypress_get_mclk_frequency_ratio(rdev, pl
678 cypress_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, RV770_SMC_HW_PERFORMANCE_LEVEL *level, u8 watermark_level) argument
830 cypress_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_Evergreen_MCRegisterSet *mc_reg_table_data) argument
[all...]
H A Dkv_dpm.c2412 struct kv_pl *pl = &ps->levels[index]; local
2417 pl->sclk = sclk;
2418 pl->vddc_index = clock_info->sumo.vddcIndex;
2423 pl->ds_divider_index = 5;
2424 pl->ss_divider_index = 5;
2654 struct kv_pl *pl = &ps->levels[i]; local
2656 i, pl->sclk,
2657 kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
H A Dni_dpm.c1614 struct rv7xx_pl *pl,
1621 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);
1624 radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk);
2314 struct rv7xx_pl *pl,
2326 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
2328 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);
2334 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
2341 if (pl->mclk > pi->mclk_edc_enable_threshold)
2343 if (pl
1613 ni_populate_memory_timing_parameters(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs) argument
2313 ni_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, NISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) argument
2960 ni_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_NIslands_MCRegisterSet *mc_reg_table_data) argument
3927 struct rv7xx_pl *pl = &ps->performance_levels[index]; local
4286 struct rv7xx_pl *pl; local
4310 struct rv7xx_pl *pl; local
4330 struct rv7xx_pl *pl; local
4348 struct rv7xx_pl *pl; local
[all...]
H A Drv770_dpm.c229 struct rv7xx_pl *pl)
231 return (pl->flags & ATOM_PPLIB_R600_FLAGS_LOWPOWER) ?
616 struct rv7xx_pl *pl,
624 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
625 level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
626 level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
630 ret = rv740_populate_sclk_value(rdev, pl->sclk,
633 ret = rv730_populate_sclk_value(rdev, pl->sclk,
636 ret = rv770_populate_sclk_value(rdev, pl->sclk,
643 if (pl
228 rv770_get_seq_value(struct radeon_device *rdev, struct rv7xx_pl *pl) argument
615 rv770_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, RV770_SMC_HW_PERFORMANCE_LEVEL *level, u8 watermark_level) argument
2183 struct rv7xx_pl *pl; local
2438 struct rv7xx_pl *pl; local
2472 struct rv7xx_pl *pl; local
2501 struct rv7xx_pl *pl; local
2523 struct rv7xx_pl *pl; local
[all...]
H A Dsi_dpm.c1690 struct rv7xx_pl *pl,
4229 struct rv7xx_pl *pl,
4237 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4240 pl->sclk,
4241 pl->mclk);
4574 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4603 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4696 if (ulv->supported && ulv->pl.vddc) {
4915 struct rv7xx_pl *pl,
4930 level->gen2PCIE = (u8)pl
4228 si_populate_memory_timing_parameters(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) argument
4914 si_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) argument
5553 si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_SIslands_MCRegisterSet *mc_reg_table_data) argument
6677 struct rv7xx_pl *pl = &ps->performance_levels[index]; local
7034 struct rv7xx_pl *pl; local
7054 struct rv7xx_pl *pl; local
7072 struct rv7xx_pl *pl; local
[all...]
H A Dsi_dpm.h140 struct rv7xx_pl pl; member in struct:si_ulv_param
H A Dsumo_dpm.c545 struct sumo_pl *pl, u32 index)
553 pl->sclk, false, &dividers);
559 sumo_set_vid(rdev, index, pl->vddc_index);
561 if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) {
565 sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
566 sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
572 sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
575 sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
1433 struct sumo_pl *pl local
544 sumo_program_power_level(struct radeon_device *rdev, struct sumo_pl *pl, u32 index) argument
1804 struct sumo_pl *pl = &ps->levels[i]; local
1818 struct sumo_pl *pl; local
1845 struct sumo_pl *pl; local
1873 struct sumo_pl *pl; local
[all...]
H A Dtrinity_dpm.c667 struct trinity_pl *pl, u32 index)
674 trinity_set_divider_value(rdev, index, pl->sclk);
675 trinity_set_vid(rdev, index, pl->vddc_index);
676 trinity_set_ss_dividers(rdev, index, pl->ss_divider_index);
677 trinity_set_ds_dividers(rdev, index, pl->ds_divider_index);
678 trinity_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
679 trinity_set_force_nbp_state(rdev, index, pl->force_nbp_state);
680 trinity_set_display_wm(rdev, index, pl->display_wm);
681 trinity_set_vce_wm(rdev, index, pl->vce_wm);
1665 struct trinity_pl *pl local
666 trinity_program_power_level(struct radeon_device *rdev, struct trinity_pl *pl, u32 index) argument
1975 struct trinity_pl *pl = &ps->levels[i]; local
1989 struct trinity_pl *pl; local
2010 struct trinity_pl *pl; local
[all...]
/linux-master/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_bo.c282 struct ttm_place pl; local
293 pl.fpfn = 0;
294 pl.lpfn = 0;
295 pl.mem_type = bo->resource->mem_type;
296 pl.flags = bo->resource->placement;
300 placement.placement = &pl;
759 set_placement_list(struct ttm_place *pl, u32 desired, u32 fallback) argument
768 pl[n].mem_type = VMW_PL_MOB;
769 pl[n].flags = placement_flags(VMW_BO_DOMAIN_MOB, desired,
771 pl[
823 struct ttm_placement *pl = &bo->placement; local
[all...]
/linux-master/drivers/hid/
H A DMakefile95 obj-$(CONFIG_HID_PANTHERLORD) += hid-pl.o
/linux-master/drivers/md/
H A Ddm-integrity.c734 static struct journal_sector *access_page_list(struct dm_integrity_c *ic, struct page_list *pl, argument
745 va = lowmem_page_address(pl[pl_index].page);
1061 io_req.mem.ptr.pl = &ic->journal_io[pl_index];
1063 io_req.mem.ptr.pl = &ic->journal[pl_index];
1184 io_req.mem.ptr.pl = &ic->journal[pl_index];
3666 static void dm_integrity_free_page_list(struct page_list *pl) argument
3670 if (!pl)
3672 for (i = 0; pl[i].page; i++)
3673 __free_page(pl[i].page);
3674 kvfree(pl);
3679 struct page_list *pl; local
3710 dm_integrity_alloc_journal_scatterlist(struct dm_integrity_c *ic, struct page_list *pl) argument
[all...]
H A Ddm-io.c190 struct page_list *pl = dp->context_ptr; local
192 *p = pl->page;
199 struct page_list *pl = dp->context_ptr; local
201 dp->context_ptr = pl->next;
205 static void list_dp_init(struct dpages *dp, struct page_list *pl, unsigned int offset) argument
210 dp->context_ptr = pl;
498 list_dp_init(dp, io_req->mem.ptr.pl, io_req->mem.offset);
H A Ddm-kcopyd.c220 struct page_list *pl; local
222 pl = kmalloc(sizeof(*pl), gfp);
223 if (!pl)
226 pl->page = alloc_page(gfp | __GFP_HIGHMEM);
227 if (!pl->page) {
228 kfree(pl);
232 return pl;
235 static void free_pl(struct page_list *pl) argument
237 __free_page(pl
245 kcopyd_put_pages(struct dm_kcopyd_client *kc, struct page_list *pl) argument
267 struct page_list *pl; local
296 drop_pages(struct page_list *pl) argument
313 struct page_list *pl = NULL, *next; local
[all...]
/linux-master/drivers/media/platform/qcom/venus/
H A Dhelpers.c850 v4l2_id_profile_level(u32 hfi_codec, struct hfi_profile_level *pl, u32 *profile, u32 *level) argument
852 u32 hfi_pf = pl->profile;
853 u32 hfi_lvl = pl->level;
886 hfi_id_profile_level(u32 hfi_codec, u32 v4l2_pf, u32 v4l2_lvl, struct hfi_profile_level *pl) argument
890 pl->profile = find_hfi_id(v4l2_pf, h264_profiles, ARRAY_SIZE(h264_profiles));
891 pl->level = find_hfi_id(v4l2_lvl, h264_levels, ARRAY_SIZE(h264_levels));
894 pl->profile = find_hfi_id(v4l2_pf, mpeg2_profiles, ARRAY_SIZE(mpeg2_profiles));
895 pl->level = find_hfi_id(v4l2_lvl, mpeg2_levels, ARRAY_SIZE(mpeg2_levels));
898 pl->profile = find_hfi_id(v4l2_pf, mpeg4_profiles, ARRAY_SIZE(mpeg4_profiles));
899 pl
937 struct hfi_profile_level pl; local
[all...]
H A Dhfi_cmds.c621 struct hfi_profile_level *in = pdata, *pl = prop_data; local
623 pl->level = in->level;
624 pl->profile = in->profile;
625 if (pl->profile <= 0)
627 pl->profile = HFI_H264_PROFILE_HIGH;
629 if (!pl->level)
631 pl->level = 1;
633 pkt->shdr.hdr.size += sizeof(u32) + sizeof(*pl);
H A Dhfi_parser.c90 const struct hfi_profile_level *pl = data; local
95 memcpy(&cap->pl[cap->num_pl], pl, num * sizeof(*pl));
102 struct hfi_profile_level_supported *pl = data; local
103 struct hfi_profile_level *proflevel = pl->profile_level;
106 if (pl->profile_count > HFI_MAX_PROFILE_COUNT)
109 memcpy(pl_arr, proflevel, pl->profile_count * sizeof(*proflevel));
112 fill_profile_level, pl_arr, pl->profile_count);

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