1/* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24/* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30#include <linux/dma-mapping.h> 31#include <drm/ttm/ttm_tt.h> 32 33#include "nouveau_drv.h" 34#include "nouveau_chan.h" 35#include "nouveau_fence.h" 36 37#include "nouveau_bo.h" 38#include "nouveau_ttm.h" 39#include "nouveau_gem.h" 40#include "nouveau_mem.h" 41#include "nouveau_vmm.h" 42 43#include <nvif/class.h> 44#include <nvif/if500b.h> 45#include <nvif/if900b.h> 46 47static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm, 48 struct ttm_resource *reg); 49static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm); 50 51/* 52 * NV10-NV40 tiling helpers 53 */ 54 55static void 56nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, 57 u32 addr, u32 size, u32 pitch, u32 flags) 58{ 59 struct nouveau_drm *drm = nouveau_drm(dev); 60 int i = reg - drm->tile.reg; 61 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 62 struct nvkm_fb_tile *tile = &fb->tile.region[i]; 63 64 nouveau_fence_unref(®->fence); 65 66 if (tile->pitch) 67 nvkm_fb_tile_fini(fb, i, tile); 68 69 if (pitch) 70 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); 71 72 nvkm_fb_tile_prog(fb, i, tile); 73} 74 75static struct nouveau_drm_tile * 76nv10_bo_get_tile_region(struct drm_device *dev, int i) 77{ 78 struct nouveau_drm *drm = nouveau_drm(dev); 79 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; 80 81 spin_lock(&drm->tile.lock); 82 83 if (!tile->used && 84 (!tile->fence || nouveau_fence_done(tile->fence))) 85 tile->used = true; 86 else 87 tile = NULL; 88 89 spin_unlock(&drm->tile.lock); 90 return tile; 91} 92 93static void 94nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, 95 struct dma_fence *fence) 96{ 97 struct nouveau_drm *drm = nouveau_drm(dev); 98 99 if (tile) { 100 spin_lock(&drm->tile.lock); 101 tile->fence = (struct nouveau_fence *)dma_fence_get(fence); 102 tile->used = false; 103 spin_unlock(&drm->tile.lock); 104 } 105} 106 107static struct nouveau_drm_tile * 108nv10_bo_set_tiling(struct drm_device *dev, u32 addr, 109 u32 size, u32 pitch, u32 zeta) 110{ 111 struct nouveau_drm *drm = nouveau_drm(dev); 112 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 113 struct nouveau_drm_tile *tile, *found = NULL; 114 int i; 115 116 for (i = 0; i < fb->tile.regions; i++) { 117 tile = nv10_bo_get_tile_region(dev, i); 118 119 if (pitch && !found) { 120 found = tile; 121 continue; 122 123 } else if (tile && fb->tile.region[i].pitch) { 124 /* Kill an unused tile region. */ 125 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); 126 } 127 128 nv10_bo_put_tile_region(dev, tile, NULL); 129 } 130 131 if (found) 132 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); 133 return found; 134} 135 136static void 137nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 138{ 139 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 140 struct drm_device *dev = drm->dev; 141 struct nouveau_bo *nvbo = nouveau_bo(bo); 142 143 WARN_ON(nvbo->bo.pin_count > 0); 144 nouveau_bo_del_io_reserve_lru(bo); 145 nv10_bo_put_tile_region(dev, nvbo->tile, NULL); 146 147 /* 148 * If nouveau_bo_new() allocated this buffer, the GEM object was never 149 * initialized, so don't attempt to release it. 150 */ 151 if (bo->base.dev) { 152 /* Gem objects not being shared with other VMs get their 153 * dma_resv from a root GEM object. 154 */ 155 if (nvbo->no_share) 156 drm_gem_object_put(nvbo->r_obj); 157 158 drm_gem_object_release(&bo->base); 159 } else { 160 dma_resv_fini(&bo->base._resv); 161 } 162 163 kfree(nvbo); 164} 165 166static inline u64 167roundup_64(u64 x, u32 y) 168{ 169 x += y - 1; 170 do_div(x, y); 171 return x * y; 172} 173 174static void 175nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size) 176{ 177 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 178 struct nvif_device *device = &drm->client.device; 179 180 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { 181 if (nvbo->mode) { 182 if (device->info.chipset >= 0x40) { 183 *align = 65536; 184 *size = roundup_64(*size, 64 * nvbo->mode); 185 186 } else if (device->info.chipset >= 0x30) { 187 *align = 32768; 188 *size = roundup_64(*size, 64 * nvbo->mode); 189 190 } else if (device->info.chipset >= 0x20) { 191 *align = 16384; 192 *size = roundup_64(*size, 64 * nvbo->mode); 193 194 } else if (device->info.chipset >= 0x10) { 195 *align = 16384; 196 *size = roundup_64(*size, 32 * nvbo->mode); 197 } 198 } 199 } else { 200 *size = roundup_64(*size, (1 << nvbo->page)); 201 *align = max((1 << nvbo->page), *align); 202 } 203 204 *size = roundup_64(*size, PAGE_SIZE); 205} 206 207struct nouveau_bo * 208nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain, 209 u32 tile_mode, u32 tile_flags, bool internal) 210{ 211 struct nouveau_drm *drm = cli->drm; 212 struct nouveau_bo *nvbo; 213 struct nvif_mmu *mmu = &cli->mmu; 214 struct nvif_vmm *vmm = &nouveau_cli_vmm(cli)->vmm; 215 int i, pi = -1; 216 217 if (!*size) { 218 NV_WARN(drm, "skipped size %016llx\n", *size); 219 return ERR_PTR(-EINVAL); 220 } 221 222 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 223 if (!nvbo) 224 return ERR_PTR(-ENOMEM); 225 226 INIT_LIST_HEAD(&nvbo->head); 227 INIT_LIST_HEAD(&nvbo->entry); 228 INIT_LIST_HEAD(&nvbo->vma_list); 229 nvbo->bo.bdev = &drm->ttm.bdev; 230 231 /* This is confusing, and doesn't actually mean we want an uncached 232 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated 233 * into in nouveau_gem_new(). 234 */ 235 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) { 236 /* Determine if we can get a cache-coherent map, forcing 237 * uncached mapping if we can't. 238 */ 239 if (!nouveau_drm_use_coherent_gpu_mapping(drm)) 240 nvbo->force_coherent = true; 241 } 242 243 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); 244 if (!nouveau_cli_uvmm(cli) || internal) { 245 /* for BO noVM allocs, don't assign kinds */ 246 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { 247 nvbo->kind = (tile_flags & 0x0000ff00) >> 8; 248 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 249 kfree(nvbo); 250 return ERR_PTR(-EINVAL); 251 } 252 253 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind; 254 } else if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 255 nvbo->kind = (tile_flags & 0x00007f00) >> 8; 256 nvbo->comp = (tile_flags & 0x00030000) >> 16; 257 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 258 kfree(nvbo); 259 return ERR_PTR(-EINVAL); 260 } 261 } else { 262 nvbo->zeta = (tile_flags & 0x00000007); 263 } 264 nvbo->mode = tile_mode; 265 266 /* Determine the desirable target GPU page size for the buffer. */ 267 for (i = 0; i < vmm->page_nr; i++) { 268 /* Because we cannot currently allow VMM maps to fail 269 * during buffer migration, we need to determine page 270 * size for the buffer up-front, and pre-allocate its 271 * page tables. 272 * 273 * Skip page sizes that can't support needed domains. 274 */ 275 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && 276 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram) 277 continue; 278 if ((domain & NOUVEAU_GEM_DOMAIN_GART) && 279 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) 280 continue; 281 282 /* Select this page size if it's the first that supports 283 * the potential memory domains, or when it's compatible 284 * with the requested compression settings. 285 */ 286 if (pi < 0 || !nvbo->comp || vmm->page[i].comp) 287 pi = i; 288 289 /* Stop once the buffer is larger than the current page size. */ 290 if (*size >= 1ULL << vmm->page[i].shift) 291 break; 292 } 293 294 if (WARN_ON(pi < 0)) { 295 kfree(nvbo); 296 return ERR_PTR(-EINVAL); 297 } 298 299 /* Disable compression if suitable settings couldn't be found. */ 300 if (nvbo->comp && !vmm->page[pi].comp) { 301 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) 302 nvbo->kind = mmu->kind[nvbo->kind]; 303 nvbo->comp = 0; 304 } 305 nvbo->page = vmm->page[pi].shift; 306 } else { 307 /* reject other tile flags when in VM mode. */ 308 if (tile_mode) 309 return ERR_PTR(-EINVAL); 310 if (tile_flags & ~NOUVEAU_GEM_TILE_NONCONTIG) 311 return ERR_PTR(-EINVAL); 312 313 /* Determine the desirable target GPU page size for the buffer. */ 314 for (i = 0; i < vmm->page_nr; i++) { 315 /* Because we cannot currently allow VMM maps to fail 316 * during buffer migration, we need to determine page 317 * size for the buffer up-front, and pre-allocate its 318 * page tables. 319 * 320 * Skip page sizes that can't support needed domains. 321 */ 322 if ((domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram) 323 continue; 324 if ((domain & NOUVEAU_GEM_DOMAIN_GART) && 325 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) 326 continue; 327 328 /* pick the last one as it will be smallest. */ 329 pi = i; 330 331 /* Stop once the buffer is larger than the current page size. */ 332 if (*size >= 1ULL << vmm->page[i].shift) 333 break; 334 } 335 if (WARN_ON(pi < 0)) { 336 kfree(nvbo); 337 return ERR_PTR(-EINVAL); 338 } 339 nvbo->page = vmm->page[pi].shift; 340 } 341 342 nouveau_bo_fixup_align(nvbo, align, size); 343 344 return nvbo; 345} 346 347int 348nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain, 349 struct sg_table *sg, struct dma_resv *robj) 350{ 351 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device; 352 int ret; 353 struct ttm_operation_ctx ctx = { 354 .interruptible = false, 355 .no_wait_gpu = false, 356 .resv = robj, 357 }; 358 359 nouveau_bo_placement_set(nvbo, domain, 0); 360 INIT_LIST_HEAD(&nvbo->io_reserve_lru); 361 362 ret = ttm_bo_init_reserved(nvbo->bo.bdev, &nvbo->bo, type, 363 &nvbo->placement, align >> PAGE_SHIFT, &ctx, 364 sg, robj, nouveau_bo_del_ttm); 365 if (ret) { 366 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 367 return ret; 368 } 369 370 if (!robj) 371 ttm_bo_unreserve(&nvbo->bo); 372 373 return 0; 374} 375 376int 377nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, 378 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags, 379 struct sg_table *sg, struct dma_resv *robj, 380 struct nouveau_bo **pnvbo) 381{ 382 struct nouveau_bo *nvbo; 383 int ret; 384 385 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode, 386 tile_flags, true); 387 if (IS_ERR(nvbo)) 388 return PTR_ERR(nvbo); 389 390 nvbo->bo.base.size = size; 391 dma_resv_init(&nvbo->bo.base._resv); 392 drm_vma_node_reset(&nvbo->bo.base.vma_node); 393 394 /* This must be called before ttm_bo_init_reserved(). Subsequent 395 * bo_move() callbacks might already iterate the GEMs GPUVA list. 396 */ 397 drm_gem_gpuva_init(&nvbo->bo.base); 398 399 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj); 400 if (ret) 401 return ret; 402 403 *pnvbo = nvbo; 404 return 0; 405} 406 407static void 408set_placement_range(struct nouveau_bo *nvbo, uint32_t domain) 409{ 410 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 411 u64 vram_size = drm->client.device.info.ram_size; 412 unsigned i, fpfn, lpfn; 413 414 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && 415 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) && 416 nvbo->bo.base.size < vram_size / 4) { 417 /* 418 * Make sure that the color and depth buffers are handled 419 * by independent memory controller units. Up to a 9x 420 * speed up when alpha-blending and depth-test are enabled 421 * at the same time. 422 */ 423 if (nvbo->zeta) { 424 fpfn = (vram_size / 2) >> PAGE_SHIFT; 425 lpfn = ~0; 426 } else { 427 fpfn = 0; 428 lpfn = (vram_size / 2) >> PAGE_SHIFT; 429 } 430 for (i = 0; i < nvbo->placement.num_placement; ++i) { 431 nvbo->placements[i].fpfn = fpfn; 432 nvbo->placements[i].lpfn = lpfn; 433 } 434 } 435} 436 437void 438nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain, 439 uint32_t busy) 440{ 441 unsigned int *n = &nvbo->placement.num_placement; 442 struct ttm_place *pl = nvbo->placements; 443 444 domain |= busy; 445 446 *n = 0; 447 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) { 448 pl[*n].mem_type = TTM_PL_VRAM; 449 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_VRAM ? 450 TTM_PL_FLAG_FALLBACK : 0; 451 (*n)++; 452 } 453 if (domain & NOUVEAU_GEM_DOMAIN_GART) { 454 pl[*n].mem_type = TTM_PL_TT; 455 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_GART ? 456 TTM_PL_FLAG_FALLBACK : 0; 457 (*n)++; 458 } 459 if (domain & NOUVEAU_GEM_DOMAIN_CPU) { 460 pl[*n].mem_type = TTM_PL_SYSTEM; 461 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_CPU ? 462 TTM_PL_FLAG_FALLBACK : 0; 463 (*n)++; 464 } 465 466 nvbo->placement.placement = nvbo->placements; 467 set_placement_range(nvbo, domain); 468} 469 470int 471nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig) 472{ 473 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 474 struct ttm_buffer_object *bo = &nvbo->bo; 475 bool force = false, evict = false; 476 int ret; 477 478 ret = ttm_bo_reserve(bo, false, false, NULL); 479 if (ret) 480 return ret; 481 482 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 483 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) { 484 if (!nvbo->contig) { 485 nvbo->contig = true; 486 force = true; 487 evict = true; 488 } 489 } 490 491 if (nvbo->bo.pin_count) { 492 bool error = evict; 493 494 switch (bo->resource->mem_type) { 495 case TTM_PL_VRAM: 496 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM); 497 break; 498 case TTM_PL_TT: 499 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART); 500 break; 501 default: 502 break; 503 } 504 505 if (error) { 506 NV_ERROR(drm, "bo %p pinned elsewhere: " 507 "0x%08x vs 0x%08x\n", bo, 508 bo->resource->mem_type, domain); 509 ret = -EBUSY; 510 } 511 ttm_bo_pin(&nvbo->bo); 512 goto out; 513 } 514 515 if (evict) { 516 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0); 517 ret = nouveau_bo_validate(nvbo, false, false); 518 if (ret) 519 goto out; 520 } 521 522 nouveau_bo_placement_set(nvbo, domain, 0); 523 ret = nouveau_bo_validate(nvbo, false, false); 524 if (ret) 525 goto out; 526 527 ttm_bo_pin(&nvbo->bo); 528 529 switch (bo->resource->mem_type) { 530 case TTM_PL_VRAM: 531 drm->gem.vram_available -= bo->base.size; 532 break; 533 case TTM_PL_TT: 534 drm->gem.gart_available -= bo->base.size; 535 break; 536 default: 537 break; 538 } 539 540out: 541 if (force && ret) 542 nvbo->contig = false; 543 ttm_bo_unreserve(bo); 544 return ret; 545} 546 547int 548nouveau_bo_unpin(struct nouveau_bo *nvbo) 549{ 550 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 551 struct ttm_buffer_object *bo = &nvbo->bo; 552 int ret; 553 554 ret = ttm_bo_reserve(bo, false, false, NULL); 555 if (ret) 556 return ret; 557 558 ttm_bo_unpin(&nvbo->bo); 559 if (!nvbo->bo.pin_count) { 560 switch (bo->resource->mem_type) { 561 case TTM_PL_VRAM: 562 drm->gem.vram_available += bo->base.size; 563 break; 564 case TTM_PL_TT: 565 drm->gem.gart_available += bo->base.size; 566 break; 567 default: 568 break; 569 } 570 } 571 572 ttm_bo_unreserve(bo); 573 return 0; 574} 575 576int 577nouveau_bo_map(struct nouveau_bo *nvbo) 578{ 579 int ret; 580 581 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); 582 if (ret) 583 return ret; 584 585 ret = ttm_bo_kmap(&nvbo->bo, 0, PFN_UP(nvbo->bo.base.size), &nvbo->kmap); 586 587 ttm_bo_unreserve(&nvbo->bo); 588 return ret; 589} 590 591void 592nouveau_bo_unmap(struct nouveau_bo *nvbo) 593{ 594 if (!nvbo) 595 return; 596 597 ttm_bo_kunmap(&nvbo->kmap); 598} 599 600void 601nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) 602{ 603 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 604 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm; 605 int i, j; 606 607 if (!ttm_dma || !ttm_dma->dma_address) 608 return; 609 if (!ttm_dma->pages) { 610 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma); 611 return; 612 } 613 614 /* Don't waste time looping if the object is coherent */ 615 if (nvbo->force_coherent) 616 return; 617 618 i = 0; 619 while (i < ttm_dma->num_pages) { 620 struct page *p = ttm_dma->pages[i]; 621 size_t num_pages = 1; 622 623 for (j = i + 1; j < ttm_dma->num_pages; ++j) { 624 if (++p != ttm_dma->pages[j]) 625 break; 626 627 ++num_pages; 628 } 629 dma_sync_single_for_device(drm->dev->dev, 630 ttm_dma->dma_address[i], 631 num_pages * PAGE_SIZE, DMA_TO_DEVICE); 632 i += num_pages; 633 } 634} 635 636void 637nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) 638{ 639 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 640 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm; 641 int i, j; 642 643 if (!ttm_dma || !ttm_dma->dma_address) 644 return; 645 if (!ttm_dma->pages) { 646 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma); 647 return; 648 } 649 650 /* Don't waste time looping if the object is coherent */ 651 if (nvbo->force_coherent) 652 return; 653 654 i = 0; 655 while (i < ttm_dma->num_pages) { 656 struct page *p = ttm_dma->pages[i]; 657 size_t num_pages = 1; 658 659 for (j = i + 1; j < ttm_dma->num_pages; ++j) { 660 if (++p != ttm_dma->pages[j]) 661 break; 662 663 ++num_pages; 664 } 665 666 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], 667 num_pages * PAGE_SIZE, DMA_FROM_DEVICE); 668 i += num_pages; 669 } 670} 671 672void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo) 673{ 674 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 675 struct nouveau_bo *nvbo = nouveau_bo(bo); 676 677 mutex_lock(&drm->ttm.io_reserve_mutex); 678 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru); 679 mutex_unlock(&drm->ttm.io_reserve_mutex); 680} 681 682void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo) 683{ 684 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 685 struct nouveau_bo *nvbo = nouveau_bo(bo); 686 687 mutex_lock(&drm->ttm.io_reserve_mutex); 688 list_del_init(&nvbo->io_reserve_lru); 689 mutex_unlock(&drm->ttm.io_reserve_mutex); 690} 691 692int 693nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, 694 bool no_wait_gpu) 695{ 696 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 697 int ret; 698 699 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx); 700 if (ret) 701 return ret; 702 703 nouveau_bo_sync_for_device(nvbo); 704 705 return 0; 706} 707 708void 709nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 710{ 711 bool is_iomem; 712 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 713 714 mem += index; 715 716 if (is_iomem) 717 iowrite16_native(val, (void __force __iomem *)mem); 718 else 719 *mem = val; 720} 721 722u32 723nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 724{ 725 bool is_iomem; 726 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 727 728 mem += index; 729 730 if (is_iomem) 731 return ioread32_native((void __force __iomem *)mem); 732 else 733 return *mem; 734} 735 736void 737nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 738{ 739 bool is_iomem; 740 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 741 742 mem += index; 743 744 if (is_iomem) 745 iowrite32_native(val, (void __force __iomem *)mem); 746 else 747 *mem = val; 748} 749 750static struct ttm_tt * 751nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) 752{ 753#if IS_ENABLED(CONFIG_AGP) 754 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 755 756 if (drm->agp.bridge) { 757 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags); 758 } 759#endif 760 761 return nouveau_sgdma_create_ttm(bo, page_flags); 762} 763 764static int 765nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm, 766 struct ttm_resource *reg) 767{ 768#if IS_ENABLED(CONFIG_AGP) 769 struct nouveau_drm *drm = nouveau_bdev(bdev); 770#endif 771 if (!reg) 772 return -EINVAL; 773#if IS_ENABLED(CONFIG_AGP) 774 if (drm->agp.bridge) 775 return ttm_agp_bind(ttm, reg); 776#endif 777 return nouveau_sgdma_bind(bdev, ttm, reg); 778} 779 780static void 781nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm) 782{ 783#if IS_ENABLED(CONFIG_AGP) 784 struct nouveau_drm *drm = nouveau_bdev(bdev); 785 786 if (drm->agp.bridge) { 787 ttm_agp_unbind(ttm); 788 return; 789 } 790#endif 791 nouveau_sgdma_unbind(bdev, ttm); 792} 793 794static void 795nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 796{ 797 struct nouveau_bo *nvbo = nouveau_bo(bo); 798 799 switch (bo->resource->mem_type) { 800 case TTM_PL_VRAM: 801 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 802 NOUVEAU_GEM_DOMAIN_CPU); 803 break; 804 default: 805 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0); 806 break; 807 } 808 809 *pl = nvbo->placement; 810} 811 812static int 813nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, 814 struct ttm_resource *reg) 815{ 816 struct nouveau_mem *old_mem = nouveau_mem(bo->resource); 817 struct nouveau_mem *new_mem = nouveau_mem(reg); 818 struct nvif_vmm *vmm = &drm->client.vmm.vmm; 819 int ret; 820 821 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0, 822 old_mem->mem.size, &old_mem->vma[0]); 823 if (ret) 824 return ret; 825 826 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0, 827 new_mem->mem.size, &old_mem->vma[1]); 828 if (ret) 829 goto done; 830 831 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); 832 if (ret) 833 goto done; 834 835 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); 836done: 837 if (ret) { 838 nvif_vmm_put(vmm, &old_mem->vma[1]); 839 nvif_vmm_put(vmm, &old_mem->vma[0]); 840 } 841 return 0; 842} 843 844static int 845nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, 846 struct ttm_operation_ctx *ctx, 847 struct ttm_resource *new_reg) 848{ 849 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 850 struct nouveau_channel *chan = drm->ttm.chan; 851 struct nouveau_cli *cli = (void *)chan->user.client; 852 struct nouveau_fence *fence; 853 int ret; 854 855 /* create temporary vmas for the transfer and attach them to the 856 * old nvkm_mem node, these will get cleaned up after ttm has 857 * destroyed the ttm_resource 858 */ 859 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 860 ret = nouveau_bo_move_prep(drm, bo, new_reg); 861 if (ret) 862 return ret; 863 } 864 865 if (drm_drv_uses_atomic_modeset(drm->dev)) 866 mutex_lock(&cli->mutex); 867 else 868 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); 869 870 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible); 871 if (ret) 872 goto out_unlock; 873 874 ret = drm->ttm.move(chan, bo, bo->resource, new_reg); 875 if (ret) 876 goto out_unlock; 877 878 ret = nouveau_fence_new(&fence, chan); 879 if (ret) 880 goto out_unlock; 881 882 /* TODO: figure out a better solution here 883 * 884 * wait on the fence here explicitly as going through 885 * ttm_bo_move_accel_cleanup somehow doesn't seem to do it. 886 * 887 * Without this the operation can timeout and we'll fallback to a 888 * software copy, which might take several minutes to finish. 889 */ 890 nouveau_fence_wait(fence, false, false); 891 ret = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false, 892 new_reg); 893 nouveau_fence_unref(&fence); 894 895out_unlock: 896 mutex_unlock(&cli->mutex); 897 return ret; 898} 899 900void 901nouveau_bo_move_init(struct nouveau_drm *drm) 902{ 903 static const struct _method_table { 904 const char *name; 905 int engine; 906 s32 oclass; 907 int (*exec)(struct nouveau_channel *, 908 struct ttm_buffer_object *, 909 struct ttm_resource *, struct ttm_resource *); 910 int (*init)(struct nouveau_channel *, u32 handle); 911 } _methods[] = { 912 { "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init }, 913 { "GRCE", 0, 0xc7b5, nve0_bo_move_copy, nvc0_bo_move_init }, 914 { "COPY", 4, 0xc6b5, nve0_bo_move_copy, nve0_bo_move_init }, 915 { "GRCE", 0, 0xc6b5, nve0_bo_move_copy, nvc0_bo_move_init }, 916 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init }, 917 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init }, 918 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init }, 919 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init }, 920 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, 921 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, 922 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, 923 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 924 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, 925 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 926 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, 927 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 928 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, 929 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, 930 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, 931 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, 932 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, 933 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, 934 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, 935 {}, 936 }; 937 const struct _method_table *mthd = _methods; 938 const char *name = "CPU"; 939 int ret; 940 941 do { 942 struct nouveau_channel *chan; 943 944 if (mthd->engine) 945 chan = drm->cechan; 946 else 947 chan = drm->channel; 948 if (chan == NULL) 949 continue; 950 951 ret = nvif_object_ctor(&chan->user, "ttmBoMove", 952 mthd->oclass | (mthd->engine << 16), 953 mthd->oclass, NULL, 0, 954 &drm->ttm.copy); 955 if (ret == 0) { 956 ret = mthd->init(chan, drm->ttm.copy.handle); 957 if (ret) { 958 nvif_object_dtor(&drm->ttm.copy); 959 continue; 960 } 961 962 drm->ttm.move = mthd->exec; 963 drm->ttm.chan = chan; 964 name = mthd->name; 965 break; 966 } 967 } while ((++mthd)->exec); 968 969 NV_INFO(drm, "MM: using %s for buffer copies\n", name); 970} 971 972static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, 973 struct ttm_resource *new_reg) 974{ 975 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; 976 struct nouveau_bo *nvbo = nouveau_bo(bo); 977 struct nouveau_vma *vma; 978 long ret; 979 980 /* ttm can now (stupidly) pass the driver bos it didn't create... */ 981 if (bo->destroy != nouveau_bo_del_ttm) 982 return; 983 984 nouveau_bo_del_io_reserve_lru(bo); 985 986 if (mem && new_reg->mem_type != TTM_PL_SYSTEM && 987 mem->mem.page == nvbo->page) { 988 list_for_each_entry(vma, &nvbo->vma_list, head) { 989 nouveau_vma_map(vma, mem); 990 } 991 nouveau_uvmm_bo_map_all(nvbo, mem); 992 } else { 993 list_for_each_entry(vma, &nvbo->vma_list, head) { 994 ret = dma_resv_wait_timeout(bo->base.resv, 995 DMA_RESV_USAGE_BOOKKEEP, 996 false, 15 * HZ); 997 WARN_ON(ret <= 0); 998 nouveau_vma_unmap(vma); 999 } 1000 nouveau_uvmm_bo_unmap_all(nvbo); 1001 } 1002 1003 if (new_reg) 1004 nvbo->offset = (new_reg->start << PAGE_SHIFT); 1005 1006} 1007 1008static int 1009nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg, 1010 struct nouveau_drm_tile **new_tile) 1011{ 1012 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1013 struct drm_device *dev = drm->dev; 1014 struct nouveau_bo *nvbo = nouveau_bo(bo); 1015 u64 offset = new_reg->start << PAGE_SHIFT; 1016 1017 *new_tile = NULL; 1018 if (new_reg->mem_type != TTM_PL_VRAM) 1019 return 0; 1020 1021 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 1022 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size, 1023 nvbo->mode, nvbo->zeta); 1024 } 1025 1026 return 0; 1027} 1028 1029static void 1030nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 1031 struct nouveau_drm_tile *new_tile, 1032 struct nouveau_drm_tile **old_tile) 1033{ 1034 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1035 struct drm_device *dev = drm->dev; 1036 struct dma_fence *fence; 1037 int ret; 1038 1039 ret = dma_resv_get_singleton(bo->base.resv, DMA_RESV_USAGE_WRITE, 1040 &fence); 1041 if (ret) 1042 dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_WRITE, 1043 false, MAX_SCHEDULE_TIMEOUT); 1044 1045 nv10_bo_put_tile_region(dev, *old_tile, fence); 1046 *old_tile = new_tile; 1047} 1048 1049static int 1050nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, 1051 struct ttm_operation_ctx *ctx, 1052 struct ttm_resource *new_reg, 1053 struct ttm_place *hop) 1054{ 1055 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1056 struct nouveau_bo *nvbo = nouveau_bo(bo); 1057 struct drm_gem_object *obj = &bo->base; 1058 struct ttm_resource *old_reg = bo->resource; 1059 struct nouveau_drm_tile *new_tile = NULL; 1060 int ret = 0; 1061 1062 if (new_reg->mem_type == TTM_PL_TT) { 1063 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg); 1064 if (ret) 1065 return ret; 1066 } 1067 1068 drm_gpuvm_bo_gem_evict(obj, evict); 1069 nouveau_bo_move_ntfy(bo, new_reg); 1070 ret = ttm_bo_wait_ctx(bo, ctx); 1071 if (ret) 1072 goto out_ntfy; 1073 1074 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1075 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); 1076 if (ret) 1077 goto out_ntfy; 1078 } 1079 1080 /* Fake bo copy. */ 1081 if (!old_reg || (old_reg->mem_type == TTM_PL_SYSTEM && 1082 !bo->ttm)) { 1083 ttm_bo_move_null(bo, new_reg); 1084 goto out; 1085 } 1086 1087 if (old_reg->mem_type == TTM_PL_SYSTEM && 1088 new_reg->mem_type == TTM_PL_TT) { 1089 ttm_bo_move_null(bo, new_reg); 1090 goto out; 1091 } 1092 1093 if (old_reg->mem_type == TTM_PL_TT && 1094 new_reg->mem_type == TTM_PL_SYSTEM) { 1095 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm); 1096 ttm_resource_free(bo, &bo->resource); 1097 ttm_bo_assign_mem(bo, new_reg); 1098 goto out; 1099 } 1100 1101 /* Hardware assisted copy. */ 1102 if (drm->ttm.move) { 1103 if ((old_reg->mem_type == TTM_PL_SYSTEM && 1104 new_reg->mem_type == TTM_PL_VRAM) || 1105 (old_reg->mem_type == TTM_PL_VRAM && 1106 new_reg->mem_type == TTM_PL_SYSTEM)) { 1107 hop->fpfn = 0; 1108 hop->lpfn = 0; 1109 hop->mem_type = TTM_PL_TT; 1110 hop->flags = 0; 1111 return -EMULTIHOP; 1112 } 1113 ret = nouveau_bo_move_m2mf(bo, evict, ctx, 1114 new_reg); 1115 } else 1116 ret = -ENODEV; 1117 1118 if (ret) { 1119 /* Fallback to software copy. */ 1120 ret = ttm_bo_move_memcpy(bo, ctx, new_reg); 1121 } 1122 1123out: 1124 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1125 if (ret) 1126 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 1127 else 1128 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 1129 } 1130out_ntfy: 1131 if (ret) { 1132 nouveau_bo_move_ntfy(bo, bo->resource); 1133 drm_gpuvm_bo_gem_evict(obj, !evict); 1134 } 1135 return ret; 1136} 1137 1138static void 1139nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm, 1140 struct ttm_resource *reg) 1141{ 1142 struct nouveau_mem *mem = nouveau_mem(reg); 1143 1144 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1145 switch (reg->mem_type) { 1146 case TTM_PL_TT: 1147 if (mem->kind) 1148 nvif_object_unmap_handle(&mem->mem.object); 1149 break; 1150 case TTM_PL_VRAM: 1151 nvif_object_unmap_handle(&mem->mem.object); 1152 break; 1153 default: 1154 break; 1155 } 1156 } 1157} 1158 1159static int 1160nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg) 1161{ 1162 struct nouveau_drm *drm = nouveau_bdev(bdev); 1163 struct nvkm_device *device = nvxx_device(&drm->client.device); 1164 struct nouveau_mem *mem = nouveau_mem(reg); 1165 struct nvif_mmu *mmu = &drm->client.mmu; 1166 int ret; 1167 1168 mutex_lock(&drm->ttm.io_reserve_mutex); 1169retry: 1170 switch (reg->mem_type) { 1171 case TTM_PL_SYSTEM: 1172 /* System memory */ 1173 ret = 0; 1174 goto out; 1175 case TTM_PL_TT: 1176#if IS_ENABLED(CONFIG_AGP) 1177 if (drm->agp.bridge) { 1178 reg->bus.offset = (reg->start << PAGE_SHIFT) + 1179 drm->agp.base; 1180 reg->bus.is_iomem = !drm->agp.cma; 1181 reg->bus.caching = ttm_write_combined; 1182 } 1183#endif 1184 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || 1185 !mem->kind) { 1186 /* untiled */ 1187 ret = 0; 1188 break; 1189 } 1190 fallthrough; /* tiled memory */ 1191 case TTM_PL_VRAM: 1192 reg->bus.offset = (reg->start << PAGE_SHIFT) + 1193 device->func->resource_addr(device, 1); 1194 reg->bus.is_iomem = true; 1195 1196 /* Some BARs do not support being ioremapped WC */ 1197 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 1198 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED) 1199 reg->bus.caching = ttm_uncached; 1200 else 1201 reg->bus.caching = ttm_write_combined; 1202 1203 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1204 union { 1205 struct nv50_mem_map_v0 nv50; 1206 struct gf100_mem_map_v0 gf100; 1207 } args; 1208 u64 handle, length; 1209 u32 argc = 0; 1210 1211 switch (mem->mem.object.oclass) { 1212 case NVIF_CLASS_MEM_NV50: 1213 args.nv50.version = 0; 1214 args.nv50.ro = 0; 1215 args.nv50.kind = mem->kind; 1216 args.nv50.comp = mem->comp; 1217 argc = sizeof(args.nv50); 1218 break; 1219 case NVIF_CLASS_MEM_GF100: 1220 args.gf100.version = 0; 1221 args.gf100.ro = 0; 1222 args.gf100.kind = mem->kind; 1223 argc = sizeof(args.gf100); 1224 break; 1225 default: 1226 WARN_ON(1); 1227 break; 1228 } 1229 1230 ret = nvif_object_map_handle(&mem->mem.object, 1231 &args, argc, 1232 &handle, &length); 1233 if (ret != 1) { 1234 if (WARN_ON(ret == 0)) 1235 ret = -EINVAL; 1236 goto out; 1237 } 1238 1239 reg->bus.offset = handle; 1240 } 1241 ret = 0; 1242 break; 1243 default: 1244 ret = -EINVAL; 1245 } 1246 1247out: 1248 if (ret == -ENOSPC) { 1249 struct nouveau_bo *nvbo; 1250 1251 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru, 1252 typeof(*nvbo), 1253 io_reserve_lru); 1254 if (nvbo) { 1255 list_del_init(&nvbo->io_reserve_lru); 1256 drm_vma_node_unmap(&nvbo->bo.base.vma_node, 1257 bdev->dev_mapping); 1258 nouveau_ttm_io_mem_free_locked(drm, nvbo->bo.resource); 1259 nvbo->bo.resource->bus.offset = 0; 1260 nvbo->bo.resource->bus.addr = NULL; 1261 goto retry; 1262 } 1263 1264 } 1265 mutex_unlock(&drm->ttm.io_reserve_mutex); 1266 return ret; 1267} 1268 1269static void 1270nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg) 1271{ 1272 struct nouveau_drm *drm = nouveau_bdev(bdev); 1273 1274 mutex_lock(&drm->ttm.io_reserve_mutex); 1275 nouveau_ttm_io_mem_free_locked(drm, reg); 1276 mutex_unlock(&drm->ttm.io_reserve_mutex); 1277} 1278 1279vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) 1280{ 1281 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1282 struct nouveau_bo *nvbo = nouveau_bo(bo); 1283 struct nvkm_device *device = nvxx_device(&drm->client.device); 1284 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; 1285 int i, ret; 1286 1287 /* as long as the bo isn't in vram, and isn't tiled, we've got 1288 * nothing to do here. 1289 */ 1290 if (bo->resource->mem_type != TTM_PL_VRAM) { 1291 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || 1292 !nvbo->kind) 1293 return 0; 1294 1295 if (bo->resource->mem_type != TTM_PL_SYSTEM) 1296 return 0; 1297 1298 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0); 1299 1300 } else { 1301 /* make sure bo is in mappable vram */ 1302 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || 1303 bo->resource->start + PFN_UP(bo->resource->size) < mappable) 1304 return 0; 1305 1306 for (i = 0; i < nvbo->placement.num_placement; ++i) { 1307 nvbo->placements[i].fpfn = 0; 1308 nvbo->placements[i].lpfn = mappable; 1309 } 1310 1311 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0); 1312 } 1313 1314 ret = nouveau_bo_validate(nvbo, false, false); 1315 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS)) 1316 return VM_FAULT_NOPAGE; 1317 else if (unlikely(ret)) 1318 return VM_FAULT_SIGBUS; 1319 1320 ttm_bo_move_to_lru_tail_unlocked(bo); 1321 return 0; 1322} 1323 1324static int 1325nouveau_ttm_tt_populate(struct ttm_device *bdev, 1326 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx) 1327{ 1328 struct ttm_tt *ttm_dma = (void *)ttm; 1329 struct nouveau_drm *drm; 1330 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL); 1331 1332 if (ttm_tt_is_populated(ttm)) 1333 return 0; 1334 1335 if (slave && ttm->sg) { 1336 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address, 1337 ttm->num_pages); 1338 return 0; 1339 } 1340 1341 drm = nouveau_bdev(bdev); 1342 1343 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx); 1344} 1345 1346static void 1347nouveau_ttm_tt_unpopulate(struct ttm_device *bdev, 1348 struct ttm_tt *ttm) 1349{ 1350 struct nouveau_drm *drm; 1351 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL); 1352 1353 if (slave) 1354 return; 1355 1356 nouveau_ttm_tt_unbind(bdev, ttm); 1357 1358 drm = nouveau_bdev(bdev); 1359 1360 return ttm_pool_free(&drm->ttm.bdev.pool, ttm); 1361} 1362 1363static void 1364nouveau_ttm_tt_destroy(struct ttm_device *bdev, 1365 struct ttm_tt *ttm) 1366{ 1367#if IS_ENABLED(CONFIG_AGP) 1368 struct nouveau_drm *drm = nouveau_bdev(bdev); 1369 if (drm->agp.bridge) { 1370 ttm_agp_destroy(ttm); 1371 return; 1372 } 1373#endif 1374 nouveau_sgdma_destroy(bdev, ttm); 1375} 1376 1377void 1378nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) 1379{ 1380 struct dma_resv *resv = nvbo->bo.base.resv; 1381 1382 if (!fence) 1383 return; 1384 1385 dma_resv_add_fence(resv, &fence->base, exclusive ? 1386 DMA_RESV_USAGE_WRITE : DMA_RESV_USAGE_READ); 1387} 1388 1389static void 1390nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1391{ 1392 nouveau_bo_move_ntfy(bo, NULL); 1393} 1394 1395struct ttm_device_funcs nouveau_bo_driver = { 1396 .ttm_tt_create = &nouveau_ttm_tt_create, 1397 .ttm_tt_populate = &nouveau_ttm_tt_populate, 1398 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, 1399 .ttm_tt_destroy = &nouveau_ttm_tt_destroy, 1400 .eviction_valuable = ttm_bo_eviction_valuable, 1401 .evict_flags = nouveau_bo_evict_flags, 1402 .delete_mem_notify = nouveau_bo_delete_mem_notify, 1403 .move = nouveau_bo_move, 1404 .io_mem_reserve = &nouveau_ttm_io_mem_reserve, 1405 .io_mem_free = &nouveau_ttm_io_mem_free, 1406}; 1407