Searched refs:barrier (Results 276 - 300 of 545) sorted by last modified time

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/linux-master/drivers/net/ethernet/qlogic/qede/
H A Dqede_main.c2081 barrier();
/linux-master/drivers/scsi/qedi/
H A Dqedi_main.c1323 barrier();
/linux-master/arch/parisc/include/asm/
H A Dspinlock.h5 #include <asm/barrier.h>
/linux-master/arch/alpha/include/asm/
H A Dprocessor.h46 #define cpu_relax() barrier()
/linux-master/arch/powerpc/platforms/85xx/
H A Dsmp.c55 barrier();
89 barrier();
105 barrier();
418 barrier();
/linux-master/drivers/net/ethernet/qlogic/qed/
H A Dqed_hw.c596 barrier();
611 barrier();
/linux-master/drivers/gpu/drm/i915/
H A Di915_active.c141 /* Even if we have not used the cache, we may still have a barrier */
387 * we are actively using the barrier, we know that there will be
416 if (!is_barrier(active)) /* proto-node used by our idle barrier? */
591 err = flush_barrier(it); /* unconnected idle barrier? */
633 if (is_barrier(active)) /* XXX flush the barrier? */
694 void *arg, struct i915_sw_fence *barrier)
723 err = __await_barrier(ref, barrier);
784 * Try to reuse any existing barrier nodes already allocated for this
815 * the first pending barrier.
835 * the barrier befor
691 await_active(struct i915_active *ref, unsigned int flags, int (*fn)(void *arg, struct dma_fence *fence), void *arg, struct i915_sw_fence *barrier) argument
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/linux-master/arch/um/os-Linux/
H A Dsigio.c523 !({ barrier(); got_sigio; }))
/linux-master/kernel/trace/
H A Dfgraph.c96 barrier();
212 barrier();
264 barrier();
594 barrier();
/linux-master/arch/s390/lib/
H A Dspinlock.c123 barrier();
273 barrier();
285 barrier();
306 barrier();
/linux-master/arch/s390/kernel/
H A Dperf_cpum_sf.c1015 barrier();
/linux-master/arch/arm/mm/
H A Dproc-v7.S226 dsb @barrier
H A Dcache-fa.S97 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
/linux-master/drivers/usb/host/
H A Duhci-hcd.c801 barrier();
/linux-master/tools/testing/selftests/powerpc/include/
H A Dreg.h20 #define barrier() asm volatile("" : : : "memory"); macro
/linux-master/kernel/kcsan/
H A Dcore.c432 barrier();
438 barrier();
776 barrier();
805 * WRITE_ONCE without memory barrier is sufficient.
1124 * Access check to catch cases where write without a barrier
/linux-master/drivers/scsi/qla2xxx/
H A Dqla_mr.c620 barrier();
905 barrier();
/linux-master/arch/riscv/kernel/
H A Dhibernate.c10 #include <asm/barrier.h>
/linux-master/arch/powerpc/platforms/powernv/
H A Didle.c252 barrier();
/linux-master/arch/powerpc/include/asm/
H A Dsimple_spinlock.h103 barrier();
111 barrier();
/linux-master/arch/loongarch/include/asm/
H A Dbarrier.h12 * Bit3: barrier for previous read (0: true, 1: false)
13 * Bit2: barrier for previous write (0: true, 1: false)
14 * Bit1: barrier for succeeding read (0: true, 1: false)
15 * Bit0: barrier for succeeding write (0: true, 1: false)
17 * Hint 0x700: barrier for "read after read" from the same address
60 #define __smp_mb__before_atomic() barrier()
61 #define __smp_mb__after_atomic() barrier()
137 #include <asm-generic/barrier.h>
/linux-master/tools/virtio/ringtest/
H A Dmain.h91 /* Compiler barrier - similar to what Linux uses */
92 #define barrier() asm volatile("" ::: "memory") macro
98 #define cpu_relax() barrier()
113 barrier();
130 * adds a compiler barrier.
133 barrier(); \
139 barrier(); \
143 #define smp_wmb() barrier()
163 barrier();
165 barrier();
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/linux-master/kernel/
H A Dkcov.c179 * READ_ONCE()/barrier() effectively provides load-acquire wrt
180 * interrupts, there are paired barrier()/WRITE_ONCE() in
183 barrier();
222 barrier();
256 barrier();
357 barrier();
364 barrier();
810 barrier();
998 barrier();
/linux-master/include/asm-generic/bitops/
H A Datomic.h7 #include <asm/barrier.h>
/linux-master/include/asm-generic/
H A Datomic.h13 #include <asm/barrier.h>

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