1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Universal Host Controller Interface driver for USB. 4 * 5 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 6 * 7 * (C) Copyright 1999 Linus Torvalds 8 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com 9 * (C) Copyright 1999 Randy Dunlap 10 * (C) Copyright 1999 Georg Acher, acher@in.tum.de 11 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de 12 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch 13 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at 14 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface 15 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). 16 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) 17 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu 18 * 19 * Intel documents this fairly well, and as far as I know there 20 * are no royalties or anything like that, but even so there are 21 * people who decided that they want to do the same thing in a 22 * completely different way. 23 * 24 */ 25 26#include <linux/module.h> 27#include <linux/pci.h> 28#include <linux/kernel.h> 29#include <linux/init.h> 30#include <linux/delay.h> 31#include <linux/ioport.h> 32#include <linux/slab.h> 33#include <linux/errno.h> 34#include <linux/unistd.h> 35#include <linux/interrupt.h> 36#include <linux/spinlock.h> 37#include <linux/debugfs.h> 38#include <linux/pm.h> 39#include <linux/dmapool.h> 40#include <linux/dma-mapping.h> 41#include <linux/usb.h> 42#include <linux/usb/hcd.h> 43#include <linux/bitops.h> 44#include <linux/dmi.h> 45 46#include <linux/uaccess.h> 47#include <asm/io.h> 48#include <asm/irq.h> 49 50#include "uhci-hcd.h" 51 52/* 53 * Version Information 54 */ 55#define DRIVER_AUTHOR \ 56 "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, " \ 57 "Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, " \ 58 "Roman Weissgaerber, Alan Stern" 59#define DRIVER_DESC "USB Universal Host Controller Interface driver" 60 61/* for flakey hardware, ignore overcurrent indicators */ 62static bool ignore_oc; 63module_param(ignore_oc, bool, S_IRUGO); 64MODULE_PARM_DESC(ignore_oc, "ignore hardware overcurrent indications"); 65 66/* 67 * debug = 0, no debugging messages 68 * debug = 1, dump failed URBs except for stalls 69 * debug = 2, dump all failed URBs (including stalls) 70 * show all queues in /sys/kernel/debug/uhci/[pci_addr] 71 * debug = 3, show all TDs in URBs when dumping 72 */ 73#ifdef CONFIG_DYNAMIC_DEBUG 74 75static int debug = 1; 76module_param(debug, int, S_IRUGO | S_IWUSR); 77MODULE_PARM_DESC(debug, "Debug level"); 78static char *errbuf; 79 80#else 81 82#define debug 0 83#define errbuf NULL 84 85#endif 86 87 88#define ERRBUF_LEN (32 * 1024) 89 90static struct kmem_cache *uhci_up_cachep; /* urb_priv */ 91 92static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state); 93static void wakeup_rh(struct uhci_hcd *uhci); 94static void uhci_get_current_frame_number(struct uhci_hcd *uhci); 95 96/* 97 * Calculate the link pointer DMA value for the first Skeleton QH in a frame. 98 */ 99static __hc32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) 100{ 101 int skelnum; 102 103 /* 104 * The interrupt queues will be interleaved as evenly as possible. 105 * There's not much to be done about period-1 interrupts; they have 106 * to occur in every frame. But we can schedule period-2 interrupts 107 * in odd-numbered frames, period-4 interrupts in frames congruent 108 * to 2 (mod 4), and so on. This way each frame only has two 109 * interrupt QHs, which will help spread out bandwidth utilization. 110 * 111 * ffs (Find First bit Set) does exactly what we need: 112 * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8], 113 * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc. 114 * ffs >= 7 => not on any high-period queue, so use 115 * period-1 QH = skelqh[9]. 116 * Add in UHCI_NUMFRAMES to insure at least one bit is set. 117 */ 118 skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES); 119 if (skelnum <= 1) 120 skelnum = 9; 121 return LINK_TO_QH(uhci, uhci->skelqh[skelnum]); 122} 123 124#include "uhci-debug.c" 125#include "uhci-q.c" 126#include "uhci-hub.c" 127 128/* 129 * Finish up a host controller reset and update the recorded state. 130 */ 131static void finish_reset(struct uhci_hcd *uhci) 132{ 133 int port; 134 135 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect 136 * bits in the port status and control registers. 137 * We have to clear them by hand. 138 */ 139 for (port = 0; port < uhci->rh_numports; ++port) 140 uhci_writew(uhci, 0, USBPORTSC1 + (port * 2)); 141 142 uhci->port_c_suspend = uhci->resuming_ports = 0; 143 uhci->rh_state = UHCI_RH_RESET; 144 uhci->is_stopped = UHCI_IS_STOPPED; 145 clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 146} 147 148/* 149 * Last rites for a defunct/nonfunctional controller 150 * or one we don't want to use any more. 151 */ 152static void uhci_hc_died(struct uhci_hcd *uhci) 153{ 154 uhci_get_current_frame_number(uhci); 155 uhci->reset_hc(uhci); 156 finish_reset(uhci); 157 uhci->dead = 1; 158 159 /* The current frame may already be partway finished */ 160 ++uhci->frame_number; 161} 162 163/* 164 * Initialize a controller that was newly discovered or has lost power 165 * or otherwise been reset while it was suspended. In none of these cases 166 * can we be sure of its previous state. 167 */ 168static void check_and_reset_hc(struct uhci_hcd *uhci) 169{ 170 if (uhci->check_and_reset_hc(uhci)) 171 finish_reset(uhci); 172} 173 174#if defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC) 175/* 176 * The two functions below are generic reset functions that are used on systems 177 * that do not have keyboard and mouse legacy support. We assume that we are 178 * running on such a system if CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC is defined. 179 */ 180 181/* 182 * Make sure the controller is completely inactive, unable to 183 * generate interrupts or do DMA. 184 */ 185static void uhci_generic_reset_hc(struct uhci_hcd *uhci) 186{ 187 /* Reset the HC - this will force us to get a 188 * new notification of any already connected 189 * ports due to the virtual disconnect that it 190 * implies. 191 */ 192 uhci_writew(uhci, USBCMD_HCRESET, USBCMD); 193 mb(); 194 udelay(5); 195 if (uhci_readw(uhci, USBCMD) & USBCMD_HCRESET) 196 dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n"); 197 198 /* Just to be safe, disable interrupt requests and 199 * make sure the controller is stopped. 200 */ 201 uhci_writew(uhci, 0, USBINTR); 202 uhci_writew(uhci, 0, USBCMD); 203} 204 205/* 206 * Initialize a controller that was newly discovered or has just been 207 * resumed. In either case we can't be sure of its previous state. 208 * 209 * Returns: 1 if the controller was reset, 0 otherwise. 210 */ 211static int uhci_generic_check_and_reset_hc(struct uhci_hcd *uhci) 212{ 213 unsigned int cmd, intr; 214 215 /* 216 * When restarting a suspended controller, we expect all the 217 * settings to be the same as we left them: 218 * 219 * Controller is stopped and configured with EGSM set; 220 * No interrupts enabled except possibly Resume Detect. 221 * 222 * If any of these conditions are violated we do a complete reset. 223 */ 224 225 cmd = uhci_readw(uhci, USBCMD); 226 if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) { 227 dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n", 228 __func__, cmd); 229 goto reset_needed; 230 } 231 232 intr = uhci_readw(uhci, USBINTR); 233 if (intr & (~USBINTR_RESUME)) { 234 dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n", 235 __func__, intr); 236 goto reset_needed; 237 } 238 return 0; 239 240reset_needed: 241 dev_dbg(uhci_dev(uhci), "Performing full reset\n"); 242 uhci_generic_reset_hc(uhci); 243 return 1; 244} 245#endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ 246 247/* 248 * Store the basic register settings needed by the controller. 249 */ 250static void configure_hc(struct uhci_hcd *uhci) 251{ 252 /* Set the frame length to the default: 1 ms exactly */ 253 uhci_writeb(uhci, USBSOF_DEFAULT, USBSOF); 254 255 /* Store the frame list base address */ 256 uhci_writel(uhci, uhci->frame_dma_handle, USBFLBASEADD); 257 258 /* Set the current frame number */ 259 uhci_writew(uhci, uhci->frame_number & UHCI_MAX_SOF_NUMBER, 260 USBFRNUM); 261 262 /* perform any arch/bus specific configuration */ 263 if (uhci->configure_hc) 264 uhci->configure_hc(uhci); 265} 266 267static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) 268{ 269 /* 270 * If we have to ignore overcurrent events then almost by definition 271 * we can't depend on resume-detect interrupts. 272 * 273 * Those interrupts also don't seem to work on ASpeed SoCs. 274 */ 275 if (ignore_oc || uhci_is_aspeed(uhci)) 276 return 1; 277 278 return uhci->resume_detect_interrupts_are_broken ? 279 uhci->resume_detect_interrupts_are_broken(uhci) : 0; 280} 281 282static int global_suspend_mode_is_broken(struct uhci_hcd *uhci) 283{ 284 return uhci->global_suspend_mode_is_broken ? 285 uhci->global_suspend_mode_is_broken(uhci) : 0; 286} 287 288static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) 289__releases(uhci->lock) 290__acquires(uhci->lock) 291{ 292 int auto_stop; 293 int int_enable, egsm_enable, wakeup_enable; 294 struct usb_device *rhdev = uhci_to_hcd(uhci)->self.root_hub; 295 296 auto_stop = (new_state == UHCI_RH_AUTO_STOPPED); 297 dev_dbg(&rhdev->dev, "%s%s\n", __func__, 298 (auto_stop ? " (auto-stop)" : "")); 299 300 /* Start off by assuming Resume-Detect interrupts and EGSM work 301 * and that remote wakeups should be enabled. 302 */ 303 egsm_enable = USBCMD_EGSM; 304 int_enable = USBINTR_RESUME; 305 wakeup_enable = 1; 306 307 /* 308 * In auto-stop mode, we must be able to detect new connections. 309 * The user can force us to poll by disabling remote wakeup; 310 * otherwise we will use the EGSM/RD mechanism. 311 */ 312 if (auto_stop) { 313 if (!device_may_wakeup(&rhdev->dev)) 314 egsm_enable = int_enable = 0; 315 } 316 317#ifdef CONFIG_PM 318 /* 319 * In bus-suspend mode, we use the wakeup setting specified 320 * for the root hub. 321 */ 322 else { 323 if (!rhdev->do_remote_wakeup) 324 wakeup_enable = 0; 325 } 326#endif 327 328 /* 329 * UHCI doesn't distinguish between wakeup requests from downstream 330 * devices and local connect/disconnect events. There's no way to 331 * enable one without the other; both are controlled by EGSM. Thus 332 * if wakeups are disallowed then EGSM must be turned off -- in which 333 * case remote wakeup requests from downstream during system sleep 334 * will be lost. 335 * 336 * In addition, if EGSM is broken then we can't use it. Likewise, 337 * if Resume-Detect interrupts are broken then we can't use them. 338 * 339 * Finally, neither EGSM nor RD is useful by itself. Without EGSM, 340 * the RD status bit will never get set. Without RD, the controller 341 * won't generate interrupts to tell the system about wakeup events. 342 */ 343 if (!wakeup_enable || global_suspend_mode_is_broken(uhci) || 344 resume_detect_interrupts_are_broken(uhci)) 345 egsm_enable = int_enable = 0; 346 347 uhci->RD_enable = !!int_enable; 348 uhci_writew(uhci, int_enable, USBINTR); 349 uhci_writew(uhci, egsm_enable | USBCMD_CF, USBCMD); 350 mb(); 351 udelay(5); 352 353 /* If we're auto-stopping then no devices have been attached 354 * for a while, so there shouldn't be any active URBs and the 355 * controller should stop after a few microseconds. Otherwise 356 * we will give the controller one frame to stop. 357 */ 358 if (!auto_stop && !(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) { 359 uhci->rh_state = UHCI_RH_SUSPENDING; 360 spin_unlock_irq(&uhci->lock); 361 msleep(1); 362 spin_lock_irq(&uhci->lock); 363 if (uhci->dead) 364 return; 365 } 366 if (!(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) 367 dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); 368 369 uhci_get_current_frame_number(uhci); 370 371 uhci->rh_state = new_state; 372 uhci->is_stopped = UHCI_IS_STOPPED; 373 374 /* 375 * If remote wakeup is enabled but either EGSM or RD interrupts 376 * doesn't work, then we won't get an interrupt when a wakeup event 377 * occurs. Thus the suspended root hub needs to be polled. 378 */ 379 if (wakeup_enable && (!int_enable || !egsm_enable)) 380 set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 381 else 382 clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 383 384 uhci_scan_schedule(uhci); 385 uhci_fsbr_off(uhci); 386} 387 388static void start_rh(struct uhci_hcd *uhci) 389{ 390 uhci->is_stopped = 0; 391 392 /* 393 * Clear stale status bits on Aspeed as we get a stale HCH 394 * which causes problems later on 395 */ 396 if (uhci_is_aspeed(uhci)) 397 uhci_writew(uhci, uhci_readw(uhci, USBSTS), USBSTS); 398 399 /* Mark it configured and running with a 64-byte max packet. 400 * All interrupts are enabled, even though RESUME won't do anything. 401 */ 402 uhci_writew(uhci, USBCMD_RS | USBCMD_CF | USBCMD_MAXP, USBCMD); 403 uhci_writew(uhci, USBINTR_TIMEOUT | USBINTR_RESUME | 404 USBINTR_IOC | USBINTR_SP, USBINTR); 405 mb(); 406 uhci->rh_state = UHCI_RH_RUNNING; 407 set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 408} 409 410static void wakeup_rh(struct uhci_hcd *uhci) 411__releases(uhci->lock) 412__acquires(uhci->lock) 413{ 414 dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, 415 "%s%s\n", __func__, 416 uhci->rh_state == UHCI_RH_AUTO_STOPPED ? 417 " (auto-start)" : ""); 418 419 /* If we are auto-stopped then no devices are attached so there's 420 * no need for wakeup signals. Otherwise we send Global Resume 421 * for 20 ms. 422 */ 423 if (uhci->rh_state == UHCI_RH_SUSPENDED) { 424 unsigned egsm; 425 426 /* Keep EGSM on if it was set before */ 427 egsm = uhci_readw(uhci, USBCMD) & USBCMD_EGSM; 428 uhci->rh_state = UHCI_RH_RESUMING; 429 uhci_writew(uhci, USBCMD_FGR | USBCMD_CF | egsm, USBCMD); 430 spin_unlock_irq(&uhci->lock); 431 msleep(20); 432 spin_lock_irq(&uhci->lock); 433 if (uhci->dead) 434 return; 435 436 /* End Global Resume and wait for EOP to be sent */ 437 uhci_writew(uhci, USBCMD_CF, USBCMD); 438 mb(); 439 udelay(4); 440 if (uhci_readw(uhci, USBCMD) & USBCMD_FGR) 441 dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); 442 } 443 444 start_rh(uhci); 445 446 /* Restart root hub polling */ 447 mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); 448} 449 450static irqreturn_t uhci_irq(struct usb_hcd *hcd) 451{ 452 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 453 unsigned short status; 454 455 /* 456 * Read the interrupt status, and write it back to clear the 457 * interrupt cause. Contrary to the UHCI specification, the 458 * "HC Halted" status bit is persistent: it is RO, not R/WC. 459 */ 460 status = uhci_readw(uhci, USBSTS); 461 if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ 462 return IRQ_NONE; 463 uhci_writew(uhci, status, USBSTS); /* Clear it */ 464 465 spin_lock(&uhci->lock); 466 if (unlikely(!uhci->is_initialized)) /* not yet configured */ 467 goto done; 468 469 if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { 470 if (status & USBSTS_HSE) 471 dev_err(uhci_dev(uhci), 472 "host system error, PCI problems?\n"); 473 if (status & USBSTS_HCPE) 474 dev_err(uhci_dev(uhci), 475 "host controller process error, something bad happened!\n"); 476 if (status & USBSTS_HCH) { 477 if (uhci->rh_state >= UHCI_RH_RUNNING) { 478 dev_err(uhci_dev(uhci), 479 "host controller halted, very bad!\n"); 480 if (debug > 1 && errbuf) { 481 /* Print the schedule for debugging */ 482 uhci_sprint_schedule(uhci, errbuf, 483 ERRBUF_LEN - EXTRA_SPACE); 484 lprintk(errbuf); 485 } 486 uhci_hc_died(uhci); 487 usb_hc_died(hcd); 488 489 /* Force a callback in case there are 490 * pending unlinks */ 491 mod_timer(&hcd->rh_timer, jiffies); 492 } 493 } 494 } 495 496 if (status & USBSTS_RD) { 497 spin_unlock(&uhci->lock); 498 usb_hcd_poll_rh_status(hcd); 499 } else { 500 uhci_scan_schedule(uhci); 501 done: 502 spin_unlock(&uhci->lock); 503 } 504 505 return IRQ_HANDLED; 506} 507 508/* 509 * Store the current frame number in uhci->frame_number if the controller 510 * is running. Expand from 11 bits (of which we use only 10) to a 511 * full-sized integer. 512 * 513 * Like many other parts of the driver, this code relies on being polled 514 * more than once per second as long as the controller is running. 515 */ 516static void uhci_get_current_frame_number(struct uhci_hcd *uhci) 517{ 518 if (!uhci->is_stopped) { 519 unsigned delta; 520 521 delta = (uhci_readw(uhci, USBFRNUM) - uhci->frame_number) & 522 (UHCI_NUMFRAMES - 1); 523 uhci->frame_number += delta; 524 } 525} 526 527/* 528 * De-allocate all resources 529 */ 530static void release_uhci(struct uhci_hcd *uhci) 531{ 532 int i; 533 534 535 spin_lock_irq(&uhci->lock); 536 uhci->is_initialized = 0; 537 spin_unlock_irq(&uhci->lock); 538 539 debugfs_lookup_and_remove(uhci_to_hcd(uhci)->self.bus_name, 540 uhci_debugfs_root); 541 542 for (i = 0; i < UHCI_NUM_SKELQH; i++) 543 uhci_free_qh(uhci, uhci->skelqh[i]); 544 545 uhci_free_td(uhci, uhci->term_td); 546 547 dma_pool_destroy(uhci->qh_pool); 548 549 dma_pool_destroy(uhci->td_pool); 550 551 kfree(uhci->frame_cpu); 552 553 dma_free_coherent(uhci_dev(uhci), 554 UHCI_NUMFRAMES * sizeof(*uhci->frame), 555 uhci->frame, uhci->frame_dma_handle); 556} 557 558/* 559 * Allocate a frame list, and then setup the skeleton 560 * 561 * The hardware doesn't really know any difference 562 * in the queues, but the order does matter for the 563 * protocols higher up. The order in which the queues 564 * are encountered by the hardware is: 565 * 566 * - All isochronous events are handled before any 567 * of the queues. We don't do that here, because 568 * we'll create the actual TD entries on demand. 569 * - The first queue is the high-period interrupt queue. 570 * - The second queue is the period-1 interrupt and async 571 * (low-speed control, full-speed control, then bulk) queue. 572 * - The third queue is the terminating bandwidth reclamation queue, 573 * which contains no members, loops back to itself, and is present 574 * only when FSBR is on and there are no full-speed control or bulk QHs. 575 */ 576static int uhci_start(struct usb_hcd *hcd) 577{ 578 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 579 int retval = -EBUSY; 580 int i; 581 582 hcd->uses_new_polling = 1; 583 /* Accept arbitrarily long scatter-gather lists */ 584 if (!hcd->localmem_pool) 585 hcd->self.sg_tablesize = ~0; 586 587 spin_lock_init(&uhci->lock); 588 timer_setup(&uhci->fsbr_timer, uhci_fsbr_timeout, 0); 589 INIT_LIST_HEAD(&uhci->idle_qh_list); 590 init_waitqueue_head(&uhci->waitqh); 591 592#ifdef UHCI_DEBUG_OPS 593 debugfs_create_file(hcd->self.bus_name, S_IFREG|S_IRUGO|S_IWUSR, 594 uhci_debugfs_root, uhci, &uhci_debug_operations); 595#endif 596 597 uhci->frame = dma_alloc_coherent(uhci_dev(uhci), 598 UHCI_NUMFRAMES * sizeof(*uhci->frame), 599 &uhci->frame_dma_handle, GFP_KERNEL); 600 if (!uhci->frame) { 601 dev_err(uhci_dev(uhci), 602 "unable to allocate consistent memory for frame list\n"); 603 goto err_alloc_frame; 604 } 605 606 uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu), 607 GFP_KERNEL); 608 if (!uhci->frame_cpu) 609 goto err_alloc_frame_cpu; 610 611 uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), 612 sizeof(struct uhci_td), 16, 0); 613 if (!uhci->td_pool) { 614 dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); 615 goto err_create_td_pool; 616 } 617 618 uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), 619 sizeof(struct uhci_qh), 16, 0); 620 if (!uhci->qh_pool) { 621 dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); 622 goto err_create_qh_pool; 623 } 624 625 uhci->term_td = uhci_alloc_td(uhci); 626 if (!uhci->term_td) { 627 dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); 628 goto err_alloc_term_td; 629 } 630 631 for (i = 0; i < UHCI_NUM_SKELQH; i++) { 632 uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL); 633 if (!uhci->skelqh[i]) { 634 dev_err(uhci_dev(uhci), "unable to allocate QH\n"); 635 goto err_alloc_skelqh; 636 } 637 } 638 639 /* 640 * 8 Interrupt queues; link all higher int queues to int1 = async 641 */ 642 for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i) 643 uhci->skelqh[i]->link = LINK_TO_QH(uhci, uhci->skel_async_qh); 644 uhci->skel_async_qh->link = UHCI_PTR_TERM(uhci); 645 uhci->skel_term_qh->link = LINK_TO_QH(uhci, uhci->skel_term_qh); 646 647 /* This dummy TD is to work around a bug in Intel PIIX controllers */ 648 uhci_fill_td(uhci, uhci->term_td, 0, uhci_explen(0) | 649 (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); 650 uhci->term_td->link = UHCI_PTR_TERM(uhci); 651 uhci->skel_async_qh->element = uhci->skel_term_qh->element = 652 LINK_TO_TD(uhci, uhci->term_td); 653 654 /* 655 * Fill the frame list: make all entries point to the proper 656 * interrupt queue. 657 */ 658 for (i = 0; i < UHCI_NUMFRAMES; i++) { 659 660 /* Only place we don't use the frame list routines */ 661 uhci->frame[i] = uhci_frame_skel_link(uhci, i); 662 } 663 664 /* 665 * Some architectures require a full mb() to enforce completion of 666 * the memory writes above before the I/O transfers in configure_hc(). 667 */ 668 mb(); 669 670 spin_lock_irq(&uhci->lock); 671 configure_hc(uhci); 672 uhci->is_initialized = 1; 673 start_rh(uhci); 674 spin_unlock_irq(&uhci->lock); 675 return 0; 676 677/* 678 * error exits: 679 */ 680err_alloc_skelqh: 681 for (i = 0; i < UHCI_NUM_SKELQH; i++) { 682 if (uhci->skelqh[i]) 683 uhci_free_qh(uhci, uhci->skelqh[i]); 684 } 685 686 uhci_free_td(uhci, uhci->term_td); 687 688err_alloc_term_td: 689 dma_pool_destroy(uhci->qh_pool); 690 691err_create_qh_pool: 692 dma_pool_destroy(uhci->td_pool); 693 694err_create_td_pool: 695 kfree(uhci->frame_cpu); 696 697err_alloc_frame_cpu: 698 dma_free_coherent(uhci_dev(uhci), 699 UHCI_NUMFRAMES * sizeof(*uhci->frame), 700 uhci->frame, uhci->frame_dma_handle); 701 702err_alloc_frame: 703 debugfs_lookup_and_remove(hcd->self.bus_name, uhci_debugfs_root); 704 705 return retval; 706} 707 708static void uhci_stop(struct usb_hcd *hcd) 709{ 710 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 711 712 spin_lock_irq(&uhci->lock); 713 if (HCD_HW_ACCESSIBLE(hcd) && !uhci->dead) 714 uhci_hc_died(uhci); 715 uhci_scan_schedule(uhci); 716 spin_unlock_irq(&uhci->lock); 717 synchronize_irq(hcd->irq); 718 719 del_timer_sync(&uhci->fsbr_timer); 720 release_uhci(uhci); 721} 722 723#ifdef CONFIG_PM 724static int uhci_rh_suspend(struct usb_hcd *hcd) 725{ 726 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 727 int rc = 0; 728 729 spin_lock_irq(&uhci->lock); 730 if (!HCD_HW_ACCESSIBLE(hcd)) 731 rc = -ESHUTDOWN; 732 else if (uhci->dead) 733 ; /* Dead controllers tell no tales */ 734 735 /* Once the controller is stopped, port resumes that are already 736 * in progress won't complete. Hence if remote wakeup is enabled 737 * for the root hub and any ports are in the middle of a resume or 738 * remote wakeup, we must fail the suspend. 739 */ 740 else if (hcd->self.root_hub->do_remote_wakeup && 741 uhci->resuming_ports) { 742 dev_dbg(uhci_dev(uhci), 743 "suspend failed because a port is resuming\n"); 744 rc = -EBUSY; 745 } else 746 suspend_rh(uhci, UHCI_RH_SUSPENDED); 747 spin_unlock_irq(&uhci->lock); 748 return rc; 749} 750 751static int uhci_rh_resume(struct usb_hcd *hcd) 752{ 753 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 754 int rc = 0; 755 756 spin_lock_irq(&uhci->lock); 757 if (!HCD_HW_ACCESSIBLE(hcd)) 758 rc = -ESHUTDOWN; 759 else if (!uhci->dead) 760 wakeup_rh(uhci); 761 spin_unlock_irq(&uhci->lock); 762 return rc; 763} 764 765#endif 766 767/* Wait until a particular device/endpoint's QH is idle, and free it */ 768static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, 769 struct usb_host_endpoint *hep) 770{ 771 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 772 struct uhci_qh *qh; 773 774 spin_lock_irq(&uhci->lock); 775 qh = (struct uhci_qh *) hep->hcpriv; 776 if (qh == NULL) 777 goto done; 778 779 while (qh->state != QH_STATE_IDLE) { 780 ++uhci->num_waiting; 781 spin_unlock_irq(&uhci->lock); 782 wait_event_interruptible(uhci->waitqh, 783 qh->state == QH_STATE_IDLE); 784 spin_lock_irq(&uhci->lock); 785 --uhci->num_waiting; 786 } 787 788 uhci_free_qh(uhci, qh); 789done: 790 spin_unlock_irq(&uhci->lock); 791} 792 793static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) 794{ 795 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 796 unsigned frame_number; 797 unsigned delta; 798 799 /* Minimize latency by avoiding the spinlock */ 800 frame_number = uhci->frame_number; 801 barrier(); 802 delta = (uhci_readw(uhci, USBFRNUM) - frame_number) & 803 (UHCI_NUMFRAMES - 1); 804 return frame_number + delta; 805} 806 807/* Determines number of ports on controller */ 808static int uhci_count_ports(struct usb_hcd *hcd) 809{ 810 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 811 unsigned io_size = (unsigned) hcd->rsrc_len; 812 int port; 813 814 /* The UHCI spec says devices must have 2 ports, and goes on to say 815 * they may have more but gives no way to determine how many there 816 * are. However according to the UHCI spec, Bit 7 of the port 817 * status and control register is always set to 1. So we try to 818 * use this to our advantage. Another common failure mode when 819 * a nonexistent register is addressed is to return all ones, so 820 * we test for that also. 821 */ 822 for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { 823 unsigned int portstatus; 824 825 portstatus = uhci_readw(uhci, USBPORTSC1 + (port * 2)); 826 if (!(portstatus & 0x0080) || portstatus == 0xffff) 827 break; 828 } 829 if (debug) 830 dev_info(uhci_dev(uhci), "detected %d ports\n", port); 831 832 /* Anything greater than 7 is weird so we'll ignore it. */ 833 if (port > UHCI_RH_MAXCHILD) { 834 dev_info(uhci_dev(uhci), 835 "port count misdetected? forcing to 2 ports\n"); 836 port = 2; 837 } 838 839 return port; 840} 841 842static const char hcd_name[] = "uhci_hcd"; 843 844#if defined(CONFIG_USB_PCI) && defined(CONFIG_HAS_IOPORT) 845#include "uhci-pci.c" 846#define PCI_DRIVER uhci_pci_driver 847#endif 848 849#ifdef CONFIG_SPARC_LEON 850#include "uhci-grlib.c" 851#define PLATFORM_DRIVER uhci_grlib_driver 852#endif 853 854#ifdef CONFIG_USB_UHCI_PLATFORM 855#include "uhci-platform.c" 856#define PLATFORM_DRIVER uhci_platform_driver 857#endif 858 859#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) 860#error "missing bus glue for uhci-hcd" 861#endif 862 863static int __init uhci_hcd_init(void) 864{ 865 int retval = -ENOMEM; 866 867 if (usb_disabled()) 868 return -ENODEV; 869 870 set_bit(USB_UHCI_LOADED, &usb_hcds_loaded); 871 872#ifdef CONFIG_DYNAMIC_DEBUG 873 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); 874 if (!errbuf) 875 goto errbuf_failed; 876 uhci_debugfs_root = debugfs_create_dir("uhci", usb_debug_root); 877#endif 878 879 uhci_up_cachep = kmem_cache_create("uhci_urb_priv", 880 sizeof(struct urb_priv), 0, 0, NULL); 881 if (!uhci_up_cachep) 882 goto up_failed; 883 884#ifdef PLATFORM_DRIVER 885 retval = platform_driver_register(&PLATFORM_DRIVER); 886 if (retval < 0) 887 goto clean0; 888#endif 889 890#ifdef PCI_DRIVER 891 retval = pci_register_driver(&PCI_DRIVER); 892 if (retval < 0) 893 goto clean1; 894#endif 895 896 return 0; 897 898#ifdef PCI_DRIVER 899clean1: 900#endif 901#ifdef PLATFORM_DRIVER 902 platform_driver_unregister(&PLATFORM_DRIVER); 903clean0: 904#endif 905 kmem_cache_destroy(uhci_up_cachep); 906 907up_failed: 908#if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) 909 debugfs_remove(uhci_debugfs_root); 910 911 kfree(errbuf); 912 913errbuf_failed: 914#endif 915 916 clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); 917 return retval; 918} 919 920static void __exit uhci_hcd_cleanup(void) 921{ 922#ifdef PLATFORM_DRIVER 923 platform_driver_unregister(&PLATFORM_DRIVER); 924#endif 925#ifdef PCI_DRIVER 926 pci_unregister_driver(&PCI_DRIVER); 927#endif 928 kmem_cache_destroy(uhci_up_cachep); 929 debugfs_remove(uhci_debugfs_root); 930#ifdef CONFIG_DYNAMIC_DEBUG 931 kfree(errbuf); 932#endif 933 clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); 934} 935 936module_init(uhci_hcd_init); 937module_exit(uhci_hcd_cleanup); 938 939MODULE_AUTHOR(DRIVER_AUTHOR); 940MODULE_DESCRIPTION(DRIVER_DESC); 941MODULE_LICENSE("GPL"); 942