/linux-master/drivers/pwm/ |
H A D | pwm-ab8500.c | 51 * The period is always 1024 q, duty_cycle is between 1q and 1024q. 53 * FreqPWMOutx[3:0] | output frequency | output frequency | 1024q = period 77 div = min_t(u64, mul_u64_u64_div_u64(state->period, 81 /* requested period < 3413333.33 */ 174 state->period = DIV64_U64_ROUND_UP((u64)div << 10, AB8500_PWM_CLKRATE);
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H A D | pwm-apple.c | 62 state->period, NSEC_PER_SEC) - on_cycles; 92 state->period = DIV64_U64_ROUND_UP(((u64)off_cycles + (u64)on_cycles) *
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H A D | pwm-atmel-hlcdc.c | 68 clk_period_ns > state->period) { 84 if ((clk_period_ns << pres) >= state->period) 115 do_div(pwmcval, state->period); 119 * the period cycle. Hence we can't set a duty cycle occupying 120 * the whole period cycle if we're asked to.
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H A D | pwm-atmel-tcb.c | 38 unsigned period; /* PWM period expressed in clk cycles */ member in struct:atmel_tcb_pwm_device 81 tcbpwm->period = 0; 102 &tcbpwm->period); 220 * If duty is 0 or equal to period there's no need to register 225 if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) { 253 tcbpwm->period); 271 unsigned period; local 305 /* If period is too big return ERANGE error */ 311 period 344 int duty_cycle, period; local [all...] |
H A D | pwm-atmel.c | 18 * - Instead of sleeping to wait for a completed period, the interrupt 64 u8 period; member in struct:atmel_pwm_registers 86 * the end of the currently running period. When such an update is 136 * Each channel that has its bit in ISR set started a new period since 197 unsigned long long cycles = state->period; 200 /* Calculate the period cycles and prescale value */ 205 * The register for the period length is cfg.period_bits bits wide. 265 atmel_pwm->data->regs.period, cprd); 305 pwm->state.period == state->period) { [all...] |
H A D | pwm-bcm-iproc.c | 91 state->period = 0; 104 state->period = div64_u64(tmp, rate); 118 u32 value, period, duty; local 124 * Find period count, duty count and prescale to suit duty_cycle and 125 * period. This is done according to formulas described below: 137 value = rate * state->period; 138 period = div64_u64(value, div); 142 if (period < IPROC_PWM_PERIOD_MIN) 145 if (period <= IPROC_PWM_PERIOD_MAX && 162 /* set period an [all...] |
H A D | pwm-bcm-kona.c | 23 * 2) Changes to prescale, duty, period, and polarity do not take effect until 30 * will transition to the new settings on a period boundary (which could be 109 * Find period count, duty count and prescale to suit duty_ns and 251 * enabled when duty and period are setup. But before this 262 err = kona_pwmc_config(chip, pwm, state->duty_cycle, state->period);
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H A D | pwm-bcm2835.c | 71 * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC 73 * multiplication period * rate doesn't overflow. 74 * To calculate the maximal possible period that guarantees the 77 * round(period * rate / NSEC_PER_SEC) <= U32_MAX 78 * <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5 79 * <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC 80 * <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate 81 * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate 82 * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1 86 if (state->period > max_perio [all...] |
H A D | pwm-berlin.c | 80 u32 value, duty, period; local 95 period = cycles; 108 berlin_pwm_writel(bpc, pwm->hwpwm, period, BERLIN_PWM_TCNT); 178 err = berlin_pwm_config(chip, pwm, state->duty_cycle, state->period);
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H A D | pwm-brcmstb.c | 90 * The period is: (period + 1) / Fv and "on" time is on / (period + 1) 105 * the period value by 1 to make it shorter than the "on" time and 128 * We can be called with separate duty and period updates, 168 /* Configure on and period value */ 210 err = brcmstb_pwm_config(chip, pwm, state->duty_cycle, state->period);
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H A D | pwm-clk.c | 46 u64 period = state->period; local 65 * (potentially) different setting. Also setting period and duty_cycle 69 rate = DIV64_U64_ROUND_UP(NSEC_PER_SEC, period); 75 duty_cycle = period - duty_cycle; 77 return clk_set_duty_cycle(pcchip->clk, duty_cycle, period);
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H A D | pwm-clps711x.c | 33 /* Store constant period value */ 34 pwm->args.period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq); 51 if (state->period != pwm->args.period) 55 val = mul_u64_u64_div_u64(state->duty_cycle, 0xf, state->period);
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H A D | pwm-crc.c | 59 if (state->period > PWM_MAX_PERIOD_NS) { 76 pwm_get_period(pwm) != state->period) { 79 do_div(level, state->period); 89 pwm_get_period(pwm) != state->period) { 98 if (pwm_get_period(pwm) != state->period || 100 int clk_div = crc_pwm_calc_clk_div(state->period); 144 state->period = 147 DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
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H A D | pwm-cros-ec.c | 142 /* The EC won't let us change the period */ 143 if (state->period != EC_PWM_MAX_DUTY) 178 state->period = EC_PWM_MAX_DUTY; 210 /* The EC won't let us change the period */ 211 pwm->args.period = EC_PWM_MAX_DUTY;
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H A D | pwm-dwc-core.c | 48 * Calculate width of low and high period in terms of input clock 57 tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, 74 * width of low period and latter the width of high period in terms 76 * Width = ((Count + 1) * input clock period). 91 * Enable timer. Output starts from low period. 124 u64 duty, period; local 141 period = (ld2 + 1) * dwc->clk_ns; 142 period += duty; 145 period [all...] |
H A D | pwm-ep93xx.c | 115 c *= state->period; 121 do_div(c, state->period);
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H A D | pwm-fsl-ftm.c | 47 struct fsl_pwm_periodcfg period; member in struct:fsl_pwm_chip 120 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]); 123 do_div(exval, rate >> fpc->period.clk_ps); 190 unsigned int period = fpc->period.mod_period + 1; local 191 unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period); 193 duty = (unsigned long long)duty_ns * period; 234 if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) { 235 dev_err(pwmchip_parent(chip), "failed to calculate new period\n"); 242 * The Freescale FTM controller supports only a single period fo [all...] |
H A D | pwm-hibvt.c | 102 u32 freq, period, duty; local 106 period = div_u64(freq * period_ns, 1000); 107 duty = div_u64(period * duty_cycle_ns, period_ns); 110 PWM_PERIOD_MASK, period); 141 state->period = div_u64(value * 1000, freq); 161 if (state->period != pwm->state.period || 163 hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);
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H A D | pwm-img.c | 43 * PWM period is specified with a timebase register, 100 dev_err(pwmchip_parent(chip), "configured period not in range\n"); 197 err = img_pwm_config(chip, pwm, state->duty_cycle, state->period);
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H A D | pwm-imx-tpm.c | 6 * - The TPM counter and period counter are shared between 7 * multiple channels, so all channels should use same period 10 * next period start. 11 * - Changing period and duty cycle together isn't atomic, 12 * with the wrong timing it might happen that a period is 13 * produced with old duty cycle but new period settings. 96 tmp = (u64)state->period * rate; 110 /* calculate real period HW can support */ 113 real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); 126 p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period); [all...] |
H A D | pwm-imx1.c | 139 err = pwm_imx1_config(chip, pwm, state->duty_cycle, state->period);
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H A D | pwm-imx27.c | 127 u32 period, prescaler, pwm_clk, val; local 156 period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val; 159 tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler; 160 state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk); 209 period_ms = DIV_ROUND_UP_ULL(pwm->state.period, 230 c = clkrate * state->period; 244 * according to imx pwm RM, the real period value should be PERIOD
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H A D | pwm-intel-lgm.c | 6 * - The hardware supports fixed period & configures only 2-wire mode. 9 * keep track of running period. 11 * and new setting for the first period. From second period, the output is 46 u32 period; member in struct:lgm_pwm_chip 70 /* The hardware only supports normal polarity and fixed period. */ 71 if (state->polarity != PWM_POLARITY_NORMAL || state->period < pc->period) 77 duty_cycle = min_t(u64, state->duty_cycle, pc->period); 78 val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period; [all...] |
H A D | pwm-iqs620a.c | 8 * - The period is fixed to 1 ms and is generated continuously despite changes 11 * and may result in a glitch during the period in which the change is made. 78 if (state->period < IQS620_PWM_PERIOD_NS) 133 state->period = IQS620_PWM_PERIOD_NS;
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H A D | pwm-jz4740.c | 7 * - The .apply callback doesn't complete the currently running period before 106 * Set duty > period. This trick allows the TCU channels in TCU2 mode to 129 unsigned long period, duty; local 134 * Limit the clock to a maximum rate that still gives us a period value 137 do_div(tmp, state->period); 156 /* Calculate period value */ 157 tmp = (unsigned long long)rate * state->period; 159 period = tmp; 166 if (duty >= period) 167 duty = period [all...] |