Lines Matching refs:period
18 * - Instead of sleeping to wait for a completed period, the interrupt
64 u8 period;
86 * the end of the currently running period. When such an update is
136 * Each channel that has its bit in ISR set started a new period since
197 unsigned long long cycles = state->period;
200 /* Calculate the period cycles and prescale value */
205 * The register for the period length is cfg.period_bits bits wide.
265 atmel_pwm->data->regs.period, cprd);
305 pwm->state.period == state->period) {
309 atmel_pwm->data->regs.period);
371 atmel_pwm->data->regs.period);
374 state->period = DIV64_U64_ROUND_UP(tmp, rate);
405 .period = PWMV1_CPRD,
411 /* 16 bits to keep period and duty. */
418 .period = PWMV2_CPRD,
424 /* 16 bits to keep period and duty. */
431 .period = PWMV1_CPRD,
437 /* 32 bits to keep period and duty. */