Searched refs:reg_val (Results 26 - 50 of 55) sorted by relevance

123

/freebsd-11-stable/sys/dev/ixgbe/
H A Dixgbe_common.h125 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);
126 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);
H A Dixgbe_common.c1113 u32 reg_val; local
1139 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1140 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1141 reg_val |= IXGBE_RXDCTL_SWFLSH;
1142 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
3387 * @reg_val: Value we read from AUTOC
3391 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) argument
3394 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3401 * @reg_val: value to write to AUTOC
3407 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, boo argument
[all...]
H A Dixgbe_82599.c244 * @reg_val: Value we read from AUTOC
250 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) argument
265 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
272 * @reg_val: value to write to AUTOC
/freebsd-11-stable/sys/dev/ntb/ntb_hw/
H A Dntb_hw_intel.c1690 uint64_t reg_val; local
1703 reg_val = intel_ntb_reg_read(4, base_reg);
1704 (void)reg_val;
1707 reg_val = intel_ntb_reg_read(4, lmt_reg);
1708 (void)reg_val;
1711 reg_val = intel_ntb_reg_read(8, base_reg);
1712 (void)reg_val;
1715 reg_val = intel_ntb_reg_read(8, lmt_reg);
1716 (void)reg_val;
2104 uint16_t reg_val; local
2844 uint64_t base, limit, reg_val; local
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/freebsd-11-stable/sys/dev/cxgb/common/
H A Dcxgb_ael1002.c91 struct reg_val { struct
100 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)
527 static struct reg_val regs[] = {
824 static struct reg_val regs[] = {
828 static struct reg_val preemphasis[] = {
1254 static struct reg_val regs0[] = {
1264 static struct reg_val regs1[] = {
1409 static struct reg_val regs[] = {
1435 static struct reg_val uCclock40MHz[] = {
1441 static struct reg_val uCclockActivat
[all...]
/freebsd-11-stable/sys/dev/ixl/
H A Di40e_common.c1161 u32 reg_val; local
1168 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1169 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1170 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1173 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1175 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1177 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
3338 * @reg_val: register value
3344 u32 reg_addr, u64 *reg_val,
3352 if (reg_val
3343 i40e_aq_debug_read_register(struct i40e_hw *hw, u32 reg_addr, u64 *reg_val, struct i40e_asq_cmd_details *cmd_details) argument
3378 i40e_aq_debug_write_register(struct i40e_hw *hw, u32 reg_addr, u64 reg_val, struct i40e_asq_cmd_details *cmd_details) argument
6496 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); local
6581 i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, u32 *reg_val) argument
6610 i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, u32 reg_val) argument
6648 u16 reg_val; local
6850 i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, u32 reg_addr, u32 *reg_val, struct i40e_asq_cmd_details *cmd_details) argument
6916 i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, u32 reg_addr, u32 reg_val, struct i40e_asq_cmd_details *cmd_details) argument
6941 i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) argument
6978 i40e_aq_set_phy_register(struct i40e_hw *hw, u8 phy_select, u8 dev_addr, bool page_change, u32 reg_addr, u32 reg_val, struct i40e_asq_cmd_details *cmd_details) argument
7016 i40e_aq_get_phy_register(struct i40e_hw *hw, u8 phy_select, u8 dev_addr, bool page_change, u32 reg_addr, u32 *reg_val, struct i40e_asq_cmd_details *cmd_details) argument
[all...]
/freebsd-11-stable/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_xmit_ds.c644 u_int32_t reg_val; local
645 reg_val = OS_REG_READ(ah, AR_LOC_CTL_REG);
647 if (!(reg_val & AR_LOC_CTL_REG_FS)) {
649 OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val | AR_LOC_CTL_REG_FS));
654 OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val & ~AR_LOC_CTL_REG_FS));
H A Dar9300_eeprom.c1271 u_int32_t reg_val, reg_usb = 0, reg_pmu = 0; local
1290 ar9300_otp_read(ah, eep_addr / 4, &reg_val, 1);
1292 if ((reg_val & 0x80) == 0x80){
1294 reg_usb = reg_val & 0x000000ff;
1297 if ((reg_val & 0x80000000) == 0x80000000){
1299 reg_pmu = (reg_val & 0xff000000) >> 24;
1816 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); local
1817 reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK |
1826 reg_val |= (HAL_ANT_DIV_COMB_LNA1 <<
1828 reg_val |
[all...]
H A Dar9300_attach.c4039 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); local
4041 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val);
4043 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val);
4045 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val);
4064 u_int32_t reg_val; local
4072 reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
4073 reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK |
4078 reg_val |=
4081 reg_val |=
4084 reg_val |
[all...]
H A Dar9300_misc.c2083 u_int32_t reg_val; local
2085 reg_val = OS_REG_READ(ah, AR_MIBC);
2086 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC);
2087 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC);
/freebsd-11-stable/sys/contrib/alpine-hal/
H A Dal_hal_pcie.c2619 uint32_t reg_val; local
2621 reg_val = al_reg_read32(&aer_regs->header);
2623 if (((reg_val & PCIE_AER_CAP_ID_MASK) >> PCIE_AER_CAP_ID_SHIFT) !=
2627 if (((reg_val & PCIE_AER_CAP_VER_MASK) >> PCIE_AER_CAP_VER_SHIFT) !=
2672 uint32_t reg_val; local
2674 reg_val = al_reg_read32(&aer_regs->uncorr_err_stat);
2675 al_reg_write32(&aer_regs->uncorr_err_stat, reg_val);
2677 return reg_val;
2686 uint32_t reg_val; local
2688 reg_val
[all...]
H A Dal_hal_serdes.c1772 uint8_t reg_val = 0; local
1776 &reg_val);
1777 tx_params->amp = (reg_val & SERDES_IREG_TX_DRV_1_HLEV_MASK) >>
1779 tx_params->total_driver_units = (reg_val &
1785 &reg_val);
1786 tx_params->c_plus_1 = (reg_val & SERDES_IREG_TX_DRV_2_LEVNM1_MASK) >>
1788 tx_params->c_plus_2 = (reg_val & SERDES_IREG_TX_DRV_2_LEVNM2_MASK) >>
1793 &reg_val);
1794 tx_params->c_minus_1 = (reg_val & SERDES_IREG_TX_DRV_3_LEVNP1_MASK) >>
1796 tx_params->slew_rate = (reg_val
[all...]
/freebsd-11-stable/sys/dev/vnic/
H A Dthunder_bgx.c255 uint64_t reg_val; local
258 reg_val = bgx_reg_read(bgx, lmac, reg);
259 if (zero && !(reg_val & mask))
261 if (!zero && (reg_val & mask))
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/LanguageRuntime/RenderScript/RenderScriptRuntime/
H A DRenderScriptRuntime.cpp195 RegisterValue reg_val; local
196 if (ctx.reg_ctx->ReadRegister(reg, reg_val))
197 arg.value = reg_val.GetAsUInt64(0, &success);
239 RegisterValue reg_val; local
240 if (ctx.reg_ctx->ReadRegister(reg, reg_val))
241 arg.value = reg_val.GetAsUInt32(0, &success);
278 RegisterValue reg_val; local
279 if (ctx.reg_ctx->ReadRegister(reg, reg_val))
280 arg.value = reg_val.GetAsUInt64(0, &success);
318 RegisterValue reg_val; local
362 RegisterValue reg_val; local
[all...]
/freebsd-11-stable/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_main.c2362 uint32_t reg_val = 0; local
2364 reg_val |= (lro_sel == AL_ETH_L4_OFFSET) ?
2367 reg_val |= (l4_sel == AL_ETH_L4_INNER_OUTER_CHK) ?
2370 reg_val |= l3_sel << EC_RFW_CFG_A_0_META_L3_CHK_RES_SEL_SHIFT;
2372 al_reg_write32(&adapter->ec_regs_base->rfw.cfg_a_0, reg_val);
2374 reg_val = al_reg_read32(&adapter->ec_regs_base->rfw.meta);
2376 reg_val |= EC_RFW_META_L3_PROT_SEL;
2378 reg_val &= ~EC_RFW_META_L3_PROT_SEL;
2381 reg_val |= EC_RFW_META_L4_PROT_SEL;
2383 reg_val
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/freebsd-11-stable/sys/mips/mediatek/
H A Dmtk_pcie.c1091 uint32_t reg_val; local
1096 reg_val = PHY_MODE_WRITE | ((reg & 0xff) << PHY_ADDR_OFFSET) |
1098 MT_WRITE32(sc, MT7620_PCIE_PHY_CFG, reg_val);
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/ABI/SysV-ppc64/
H A DABISysV_ppc64.cpp455 RegisterValue reg_val; local
456 if (!m_reg_ctx->ReadRegister(reg_info, reg_val)) {
462 uint32_t rc = reg_val.GetAsMemoryData(
/freebsd-11-stable/tools/tools/cxgbtool/
H A Dcxgbtool.c247 uint32_t reg_val = 0; // silence compiler warning local
251 reg_val = regs[reg_array->addr / 4];
253 reg_array->name, reg_val, reg_val);
255 uint32_t v = xtract(reg_val, reg_array->addr,
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterContextLLDB.cpp304 addr_t reg_val; local
305 if (ReadGPRValue(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FP, reg_val))
306 UnwindLogMsg("fp = 0x%" PRIx64, reg_val);
307 if (ReadGPRValue(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, reg_val))
308 UnwindLogMsg("sp = 0x%" PRIx64, reg_val);
/freebsd-11-stable/sys/dev/e1000/
H A De1000_82575.c2277 u32 reg_val, reg_offset; local
2291 reg_val = E1000_READ_REG(hw, reg_offset);
2293 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2298 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2300 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2303 E1000_WRITE_REG(hw, reg_offset, reg_val);
/freebsd-11-stable/sys/dev/qlxge/
H A Dqls_dump.c1596 uint32_t reg, reg_val; local
1933 ret = qls_mpi_risc_rd_reg(ha, reg, &reg_val);
1934 mpi_dump->sem_regs[i] = reg_val;
/freebsd-11-stable/sys/dev/bxe/
H A Dbxe_elink.c5872 uint16_t reg_val; local
5877 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5881 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5883 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5888 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5894 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5895 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5897 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5899 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5901 reg_val
5975 uint16_t reg_val; local
[all...]
/freebsd-11-stable/usr.sbin/cxgbetool/
H A Dcxgbetool.c273 uint32_t reg_val = 0; local
277 reg_val = regs[reg_array->addr / 4];
279 reg_array->name, reg_val, reg_val);
281 uint32_t v = xtract(reg_val, reg_array->addr,
/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Decore_dbg_fw_funcs.c2237 u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; local
2243 reg_val[i] = ecore_rd(p_hwfn, p_ptt, s_reset_regs_defs[i].addr);
2249 dev_data->block_in_reset[i] = block->has_reset_bit && !(reg_val[block->reset_reg] & (1 << block->reset_bit_offset));
2869 u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; local
2877 reg_val[block->reset_reg] |= (1 << block->reset_bit_offset);
2885 reg_val[i] |= s_reset_regs_defs[i].unreset_val[dev_data->chip_id];
2887 if (reg_val[i])
2888 ecore_wr(p_hwfn, p_ptt, s_reset_regs_defs[i].addr + RESET_REG_UNRESET_OFFSET, reg_val[i]);
3845 u32 block_size, ram_size, offset = 0, reg_val, i; local
3853 reg_val
[all...]
/freebsd-11-stable/sys/dev/iwm/
H A Dif_iwm.c1362 uint32_t reg_val = 0; local
1373 reg_val |= IWM_CSR_HW_REV_STEP(sc->sc_hw_rev) <<
1375 reg_val |= IWM_CSR_HW_REV_DASH(sc->sc_hw_rev) <<
1379 reg_val |= radio_cfg_type << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE;
1380 reg_val |= radio_cfg_step << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP;
1381 reg_val |= radio_cfg_dash << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH;
1383 IWM_WRITE(sc, IWM_CSR_HW_IF_CONFIG_REG, reg_val);

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