1/****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_common.h 320897 2017-07-11 21:25:07Z erj $*/ 34 35#ifndef _IXGBE_COMMON_H_ 36#define _IXGBE_COMMON_H_ 37 38#include "ixgbe_type.h" 39#define IXGBE_WRITE_REG64(hw, reg, value) \ 40 do { \ 41 IXGBE_WRITE_REG(hw, reg, (u32) value); \ 42 IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \ 43 } while (0) 44#define IXGBE_REMOVED(a) (0) 45#if !defined(NO_READ_PBA_RAW) || !defined(NO_WRITE_PBA_RAW) 46struct ixgbe_pba { 47 u16 word[2]; 48 u16 *pba_block; 49}; 50#endif 51 52void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map); 53 54u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw); 55s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw); 56s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw); 57s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw); 58s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw); 59s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw); 60s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num); 61s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 62 u32 pba_num_size); 63s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 64 u32 eeprom_buf_size, u16 max_pba_block_size, 65 struct ixgbe_pba *pba); 66s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 67 u32 eeprom_buf_size, struct ixgbe_pba *pba); 68s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 69 u32 eeprom_buf_size, u16 *pba_block_size); 70s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr); 71s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw); 72void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status); 73void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw); 74s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw); 75 76s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index); 77s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index); 78s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw); 79 80s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw); 81s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data); 82s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 83 u16 words, u16 *data); 84s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data); 85s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 86 u16 words, u16 *data); 87s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data); 88s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 89 u16 words, u16 *data); 90s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 91 u16 *data); 92s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 93 u16 words, u16 *data); 94s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw); 95s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 96 u16 *checksum_val); 97s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw); 98s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 99 100s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 101 u32 enable_addr); 102s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index); 103s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw); 104s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 105 u32 mc_addr_count, 106 ixgbe_mc_addr_itr func, bool clear); 107s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 108 u32 addr_count, ixgbe_mc_addr_itr func); 109s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw); 110s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw); 111s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval); 112s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw); 113s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw); 114 115s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw); 116bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw); 117void ixgbe_fc_autoneg(struct ixgbe_hw *hw); 118s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw); 119 120s32 ixgbe_validate_mac_addr(u8 *mac_addr); 121s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask); 122void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask); 123s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 124 125s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val); 126s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked); 127 128s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index); 129s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index); 130 131s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr); 132s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr); 133 134s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 135s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq); 136s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 137s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); 138s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw); 139s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, 140 u32 vind, bool vlan_on, bool vlvf_bypass); 141s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 142 bool vlan_on, u32 *vfta_delta, u32 vfta, 143 bool vlvf_bypass); 144s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw); 145s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass); 146 147s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, 148 ixgbe_link_speed *speed, 149 bool *link_up, bool link_up_wait_to_complete); 150 151s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 152 u16 *wwpn_prefix); 153 154s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs); 155void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf); 156void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf); 157s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps); 158void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 159 int strategy); 160void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw); 161s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 162 u8 build, u8 ver, u16 len, const char *str); 163u8 ixgbe_calculate_checksum(u8 *buffer, u32 length); 164s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 165 u32 length, u32 timeout, bool return_data); 166s32 ixgbe_hic_unlocked(struct ixgbe_hw *, u32 *buffer, u32 length, u32 timeout); 167s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *); 168s32 ixgbe_fw_phy_activity(struct ixgbe_hw *, u16 activity, 169 u32 (*data)[FW_PHY_ACT_DATA_COUNT]); 170void ixgbe_clear_tx_pending(struct ixgbe_hw *hw); 171s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status); 172bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg); 173s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, 174 u32 action); 175s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value); 176 177extern s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw); 178extern void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw); 179bool ixgbe_mng_present(struct ixgbe_hw *hw); 180bool ixgbe_mng_enabled(struct ixgbe_hw *hw); 181 182void ixgbe_disable_rx_generic(struct ixgbe_hw *hw); 183void ixgbe_enable_rx_generic(struct ixgbe_hw *hw); 184s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 185 ixgbe_link_speed speed, 186 bool autoneg_wait_to_complete); 187void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 188 ixgbe_link_speed speed); 189#endif /* IXGBE_COMMON */ 190