1176667Sjfv/****************************************************************************** 2176667Sjfv 3286833Ssbruno Copyright (c) 2001-2015, Intel Corporation 4176667Sjfv All rights reserved. 5176667Sjfv 6176667Sjfv Redistribution and use in source and binary forms, with or without 7176667Sjfv modification, are permitted provided that the following conditions are met: 8176667Sjfv 9176667Sjfv 1. Redistributions of source code must retain the above copyright notice, 10176667Sjfv this list of conditions and the following disclaimer. 11176667Sjfv 12176667Sjfv 2. Redistributions in binary form must reproduce the above copyright 13176667Sjfv notice, this list of conditions and the following disclaimer in the 14176667Sjfv documentation and/or other materials provided with the distribution. 15176667Sjfv 16176667Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17176667Sjfv contributors may be used to endorse or promote products derived from 18176667Sjfv this software without specific prior written permission. 19176667Sjfv 20176667Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21176667Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22176667Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23176667Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24176667Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25176667Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26176667Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27176667Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28176667Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29176667Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30176667Sjfv POSSIBILITY OF SUCH DAMAGE. 31176667Sjfv 32176667Sjfv******************************************************************************/ 33176667Sjfv/*$FreeBSD: stable/11/sys/dev/e1000/e1000_82575.c 333215 2018-05-03 15:47:42Z marius $*/ 34176667Sjfv 35185353Sjfv/* 36185353Sjfv * 82575EB Gigabit Network Connection 37185353Sjfv * 82575EB Gigabit Backplane Connection 38185353Sjfv * 82575GB Gigabit Network Connection 39185353Sjfv * 82576 Gigabit Network Connection 40194865Sjfv * 82576 Quad Port Gigabit Mezzanine Adapter 41238148Sjfv * 82580 Gigabit Network Connection 42238148Sjfv * I350 Gigabit Network Connection 43176667Sjfv */ 44176667Sjfv 45176667Sjfv#include "e1000_api.h" 46238148Sjfv#include "e1000_i210.h" 47176667Sjfv 48176667Sjfvstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 49176667Sjfvstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 50176667Sjfvstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 51176667Sjfvstatic void e1000_release_phy_82575(struct e1000_hw *hw); 52176667Sjfvstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 53176667Sjfvstatic void e1000_release_nvm_82575(struct e1000_hw *hw); 54176667Sjfvstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw); 55256200Sjfvstatic s32 e1000_check_for_link_media_swap(struct e1000_hw *hw); 56176667Sjfvstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 57176667Sjfvstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 58228386Sjfv u16 *duplex); 59176667Sjfvstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 60176667Sjfvstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 61228386Sjfv u16 *data); 62176667Sjfvstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw); 63200243Sjfvstatic s32 e1000_reset_hw_82580(struct e1000_hw *hw); 64218530Sjfvstatic s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 65228386Sjfv u32 offset, u16 *data); 66218530Sjfvstatic s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 67228386Sjfv u32 offset, u16 data); 68218530Sjfvstatic s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, 69228386Sjfv bool active); 70218530Sjfvstatic s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, 71228386Sjfv bool active); 72176667Sjfvstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 73228386Sjfv bool active); 74176667Sjfvstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 75200243Sjfvstatic s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 76228386Sjfvstatic s32 e1000_get_media_type_82575(struct e1000_hw *hw); 77228386Sjfvstatic s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw); 78181027Sjfvstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 79176667Sjfvstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 80228386Sjfv u32 offset, u16 data); 81176667Sjfvstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 82176667Sjfvstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 83176667Sjfvstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 84228386Sjfv u16 *speed, u16 *duplex); 85176667Sjfvstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 86176667Sjfvstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 87176667Sjfvstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw); 88176667Sjfvstatic s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 89176667Sjfvstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 90203049Sjfvstatic void e1000_config_collision_dist_82575(struct e1000_hw *hw); 91176667Sjfvstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 92200243Sjfvstatic void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 93203049Sjfvstatic void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 94194865Sjfvstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 95213234Sjfvstatic s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); 96218530Sjfvstatic s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); 97218530Sjfvstatic s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); 98218530Sjfvstatic s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, 99228386Sjfv u16 offset); 100218530Sjfvstatic s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 101228386Sjfv u16 offset); 102218530Sjfvstatic s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); 103218530Sjfvstatic s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); 104228386Sjfvstatic void e1000_clear_vfta_i350(struct e1000_hw *hw); 105176667Sjfv 106228386Sjfvstatic void e1000_i2c_start(struct e1000_hw *hw); 107228386Sjfvstatic void e1000_i2c_stop(struct e1000_hw *hw); 108228386Sjfvstatic s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data); 109228386Sjfvstatic s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data); 110228386Sjfvstatic s32 e1000_get_i2c_ack(struct e1000_hw *hw); 111228386Sjfvstatic s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data); 112228386Sjfvstatic s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data); 113228386Sjfvstatic void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 114228386Sjfvstatic void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 115228386Sjfvstatic s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data); 116228386Sjfvstatic bool e1000_get_i2c_data(u32 *i2cctl); 117228386Sjfv 118228386Sjfvstatic const u16 e1000_82580_rxpbs_table[] = { 119228386Sjfv 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 120200243Sjfv#define E1000_82580_RXPBS_TABLE_SIZE \ 121267935Sjfv (sizeof(e1000_82580_rxpbs_table) / \ 122267935Sjfv sizeof(e1000_82580_rxpbs_table[0])) 123200243Sjfv 124213234Sjfv 125176667Sjfv/** 126213234Sjfv * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 127213234Sjfv * @hw: pointer to the HW structure 128213234Sjfv * 129213234Sjfv * Called to determine if the I2C pins are being used for I2C or as an 130213234Sjfv * external MDIO interface since the two options are mutually exclusive. 131213234Sjfv **/ 132213234Sjfvstatic bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) 133213234Sjfv{ 134213234Sjfv u32 reg = 0; 135213234Sjfv bool ext_mdio = FALSE; 136213234Sjfv 137213234Sjfv DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); 138213234Sjfv 139213234Sjfv switch (hw->mac.type) { 140213234Sjfv case e1000_82575: 141213234Sjfv case e1000_82576: 142213234Sjfv reg = E1000_READ_REG(hw, E1000_MDIC); 143213234Sjfv ext_mdio = !!(reg & E1000_MDIC_DEST); 144213234Sjfv break; 145213234Sjfv case e1000_82580: 146218530Sjfv case e1000_i350: 147256200Sjfv case e1000_i354: 148247064Sjfv case e1000_i210: 149247064Sjfv case e1000_i211: 150213234Sjfv reg = E1000_READ_REG(hw, E1000_MDICNFG); 151213234Sjfv ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 152213234Sjfv break; 153213234Sjfv default: 154213234Sjfv break; 155213234Sjfv } 156213234Sjfv return ext_mdio; 157213234Sjfv} 158213234Sjfv 159213234Sjfv/** 160176667Sjfv * e1000_init_phy_params_82575 - Init PHY func ptrs. 161176667Sjfv * @hw: pointer to the HW structure 162176667Sjfv **/ 163176667Sjfvstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 164176667Sjfv{ 165176667Sjfv struct e1000_phy_info *phy = &hw->phy; 166176667Sjfv s32 ret_val = E1000_SUCCESS; 167213234Sjfv u32 ctrl_ext; 168176667Sjfv 169176667Sjfv DEBUGFUNC("e1000_init_phy_params_82575"); 170176667Sjfv 171238148Sjfv phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; 172238148Sjfv phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; 173238148Sjfv 174176667Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 175176667Sjfv phy->type = e1000_phy_none; 176176667Sjfv goto out; 177176667Sjfv } 178176667Sjfv 179200243Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 180200243Sjfv phy->ops.power_down = e1000_power_down_phy_copper_82575; 181200243Sjfv 182228386Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 183228386Sjfv phy->reset_delay_us = 100; 184176667Sjfv 185228386Sjfv phy->ops.acquire = e1000_acquire_phy_82575; 186228386Sjfv phy->ops.check_reset_block = e1000_check_reset_block_generic; 187228386Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 188228386Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 189228386Sjfv phy->ops.release = e1000_release_phy_82575; 190176667Sjfv 191213234Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 192213234Sjfv 193176667Sjfv if (e1000_sgmii_active_82575(hw)) { 194228386Sjfv phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 195213234Sjfv ctrl_ext |= E1000_CTRL_I2C_ENA; 196213234Sjfv } else { 197228386Sjfv phy->ops.reset = e1000_phy_hw_reset_generic; 198213234Sjfv ctrl_ext &= ~E1000_CTRL_I2C_ENA; 199213234Sjfv } 200213234Sjfv 201213234Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 202213234Sjfv e1000_reset_mdicnfg_82580(hw); 203218530Sjfv 204213234Sjfv if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { 205228386Sjfv phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 206228386Sjfv phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 207176667Sjfv } else { 208238148Sjfv switch (hw->mac.type) { 209238148Sjfv case e1000_82580: 210238148Sjfv case e1000_i350: 211256200Sjfv case e1000_i354: 212238148Sjfv phy->ops.read_reg = e1000_read_phy_reg_82580; 213238148Sjfv phy->ops.write_reg = e1000_write_phy_reg_82580; 214238148Sjfv break; 215238148Sjfv case e1000_i210: 216238148Sjfv case e1000_i211: 217238148Sjfv phy->ops.read_reg = e1000_read_phy_reg_gs40g; 218238148Sjfv phy->ops.write_reg = e1000_write_phy_reg_gs40g; 219238148Sjfv break; 220238148Sjfv default: 221238148Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 222238148Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 223238148Sjfv } 224176667Sjfv } 225176667Sjfv 226176667Sjfv /* Set phy->phy_addr and phy->id. */ 227176667Sjfv ret_val = e1000_get_phy_id_82575(hw); 228176667Sjfv 229176667Sjfv /* Verify phy id and set remaining function pointers */ 230176667Sjfv switch (phy->id) { 231256200Sjfv case M88E1543_E_PHY_ID: 232256200Sjfv case M88E1512_E_PHY_ID: 233218530Sjfv case I347AT4_E_PHY_ID: 234218530Sjfv case M88E1112_E_PHY_ID: 235219753Sjfv case M88E1340M_E_PHY_ID: 236176667Sjfv case M88E1111_I_PHY_ID: 237228386Sjfv phy->type = e1000_phy_m88; 238228386Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 239228386Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 240218530Sjfv if (phy->id == I347AT4_E_PHY_ID || 241219753Sjfv phy->id == M88E1112_E_PHY_ID || 242219753Sjfv phy->id == M88E1340M_E_PHY_ID) 243228386Sjfv phy->ops.get_cable_length = 244228386Sjfv e1000_get_cable_length_m88_gen2; 245256200Sjfv else if (phy->id == M88E1543_E_PHY_ID || 246256200Sjfv phy->id == M88E1512_E_PHY_ID) 247256200Sjfv phy->ops.get_cable_length = 248256200Sjfv e1000_get_cable_length_m88_gen2; 249218530Sjfv else 250218530Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 251176667Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 252256200Sjfv /* Check if this PHY is confgured for media swap. */ 253256200Sjfv if (phy->id == M88E1112_E_PHY_ID) { 254256200Sjfv u16 data; 255256200Sjfv 256256200Sjfv ret_val = phy->ops.write_reg(hw, 257256200Sjfv E1000_M88E1112_PAGE_ADDR, 258256200Sjfv 2); 259256200Sjfv if (ret_val) 260256200Sjfv goto out; 261256200Sjfv 262256200Sjfv ret_val = phy->ops.read_reg(hw, 263256200Sjfv E1000_M88E1112_MAC_CTRL_1, 264256200Sjfv &data); 265256200Sjfv if (ret_val) 266256200Sjfv goto out; 267256200Sjfv 268256200Sjfv data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> 269256200Sjfv E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; 270256200Sjfv if (data == E1000_M88E1112_AUTO_COPPER_SGMII || 271256200Sjfv data == E1000_M88E1112_AUTO_COPPER_BASEX) 272256200Sjfv hw->mac.ops.check_for_link = 273256200Sjfv e1000_check_for_link_media_swap; 274256200Sjfv } 275267935Sjfv if (phy->id == M88E1512_E_PHY_ID) { 276267935Sjfv ret_val = e1000_initialize_M88E1512_phy(hw); 277267935Sjfv if (ret_val) 278267935Sjfv goto out; 279267935Sjfv } 280295323Serj if (phy->id == M88E1543_E_PHY_ID) { 281295323Serj ret_val = e1000_initialize_M88E1543_phy(hw); 282295323Serj if (ret_val) 283295323Serj goto out; 284295323Serj } 285176667Sjfv break; 286176667Sjfv case IGP03E1000_E_PHY_ID: 287181027Sjfv case IGP04E1000_E_PHY_ID: 288228386Sjfv phy->type = e1000_phy_igp_3; 289228386Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 290228386Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 291228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 292176667Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 293228386Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 294228386Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 295176667Sjfv break; 296200243Sjfv case I82580_I_PHY_ID: 297218530Sjfv case I350_I_PHY_ID: 298228386Sjfv phy->type = e1000_phy_82580; 299228386Sjfv phy->ops.check_polarity = e1000_check_polarity_82577; 300228386Sjfv phy->ops.force_speed_duplex = 301228386Sjfv e1000_phy_force_speed_duplex_82577; 302228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_82577; 303228386Sjfv phy->ops.get_info = e1000_get_phy_info_82577; 304228386Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 305228386Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 306200243Sjfv break; 307238148Sjfv case I210_I_PHY_ID: 308238148Sjfv phy->type = e1000_phy_i210; 309238148Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 310238148Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 311238148Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; 312238148Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 313238148Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 314238148Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 315238148Sjfv break; 316176667Sjfv default: 317176667Sjfv ret_val = -E1000_ERR_PHY; 318176667Sjfv goto out; 319176667Sjfv } 320176667Sjfv 321176667Sjfvout: 322176667Sjfv return ret_val; 323176667Sjfv} 324176667Sjfv 325176667Sjfv/** 326176667Sjfv * e1000_init_nvm_params_82575 - Init NVM func ptrs. 327176667Sjfv * @hw: pointer to the HW structure 328176667Sjfv **/ 329219753Sjfvs32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 330176667Sjfv{ 331176667Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 332176667Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 333176667Sjfv u16 size; 334176667Sjfv 335176667Sjfv DEBUGFUNC("e1000_init_nvm_params_82575"); 336176667Sjfv 337218530Sjfv size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 338228386Sjfv E1000_EECD_SIZE_EX_SHIFT); 339218530Sjfv /* 340218530Sjfv * Added to a constant, "size" becomes the left-shift value 341218530Sjfv * for setting word_size. 342218530Sjfv */ 343218530Sjfv size += NVM_WORD_SIZE_BASE_SHIFT; 344218530Sjfv 345228386Sjfv /* Just in case size is out of range, cap it to the largest 346228386Sjfv * EEPROM size supported 347228386Sjfv */ 348228386Sjfv if (size > 15) 349228386Sjfv size = 15; 350228386Sjfv 351218530Sjfv nvm->word_size = 1 << size; 352238148Sjfv if (hw->mac.type < e1000_i210) { 353238148Sjfv nvm->opcode_bits = 8; 354238148Sjfv nvm->delay_usec = 1; 355176667Sjfv 356238148Sjfv switch (nvm->override) { 357238148Sjfv case e1000_nvm_override_spi_large: 358238148Sjfv nvm->page_size = 32; 359238148Sjfv nvm->address_bits = 16; 360238148Sjfv break; 361238148Sjfv case e1000_nvm_override_spi_small: 362238148Sjfv nvm->page_size = 8; 363238148Sjfv nvm->address_bits = 8; 364238148Sjfv break; 365238148Sjfv default: 366238148Sjfv nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 367238148Sjfv nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 368238148Sjfv 16 : 8; 369238148Sjfv break; 370238148Sjfv } 371238148Sjfv if (nvm->word_size == (1 << 15)) 372238148Sjfv nvm->page_size = 128; 373176667Sjfv 374238148Sjfv nvm->type = e1000_nvm_eeprom_spi; 375238148Sjfv } else { 376238148Sjfv nvm->type = e1000_nvm_flash_hw; 377238148Sjfv } 378247064Sjfv 379219753Sjfv /* Function Pointers */ 380228386Sjfv nvm->ops.acquire = e1000_acquire_nvm_82575; 381228386Sjfv nvm->ops.release = e1000_release_nvm_82575; 382219753Sjfv if (nvm->word_size < (1 << 15)) 383228386Sjfv nvm->ops.read = e1000_read_nvm_eerd; 384219753Sjfv else 385228386Sjfv nvm->ops.read = e1000_read_nvm_spi; 386176667Sjfv 387228386Sjfv nvm->ops.write = e1000_write_nvm_spi; 388228386Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_generic; 389228386Sjfv nvm->ops.update = e1000_update_nvm_checksum_generic; 390228386Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_82575; 391219753Sjfv 392238148Sjfv /* override generic family function pointers for specific descendants */ 393218530Sjfv switch (hw->mac.type) { 394218530Sjfv case e1000_82580: 395218530Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_82580; 396218530Sjfv nvm->ops.update = e1000_update_nvm_checksum_82580; 397218530Sjfv break; 398218530Sjfv case e1000_i350: 399256200Sjfv case e1000_i354: 400218530Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_i350; 401218530Sjfv nvm->ops.update = e1000_update_nvm_checksum_i350; 402218530Sjfv break; 403218530Sjfv default: 404219753Sjfv break; 405218530Sjfv } 406176667Sjfv 407176667Sjfv return E1000_SUCCESS; 408176667Sjfv} 409176667Sjfv 410176667Sjfv/** 411176667Sjfv * e1000_init_mac_params_82575 - Init MAC func ptrs. 412176667Sjfv * @hw: pointer to the HW structure 413176667Sjfv **/ 414176667Sjfvstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 415176667Sjfv{ 416176667Sjfv struct e1000_mac_info *mac = &hw->mac; 417185353Sjfv struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 418176667Sjfv 419176667Sjfv DEBUGFUNC("e1000_init_mac_params_82575"); 420176667Sjfv 421228386Sjfv /* Derives media type */ 422228386Sjfv e1000_get_media_type_82575(hw); 423176667Sjfv /* Set mta register count */ 424176667Sjfv mac->mta_reg_count = 128; 425200243Sjfv /* Set uta register count */ 426200243Sjfv mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 427176667Sjfv /* Set rar entry count */ 428176667Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 429181027Sjfv if (mac->type == e1000_82576) 430181027Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 431203049Sjfv if (mac->type == e1000_82580) 432200243Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 433256200Sjfv if (mac->type == e1000_i350 || mac->type == e1000_i354) 434218530Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 435247064Sjfv 436247064Sjfv /* Enable EEE default settings for EEE supported devices */ 437247064Sjfv if (mac->type >= e1000_i350) 438218530Sjfv dev_spec->eee_disable = FALSE; 439218530Sjfv 440247064Sjfv /* Allow a single clear of the SW semaphore on I210 and newer */ 441247064Sjfv if (mac->type >= e1000_i210) 442247064Sjfv dev_spec->clear_semaphore_once = TRUE; 443247064Sjfv 444176667Sjfv /* Set if part includes ASF firmware */ 445176667Sjfv mac->asf_firmware_present = TRUE; 446205869Sjfv /* FWSM register */ 447205869Sjfv mac->has_fwsm = TRUE; 448205869Sjfv /* ARC supported; valid only if manageability features are enabled. */ 449176667Sjfv mac->arc_subsystem_valid = 450238148Sjfv !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK); 451176667Sjfv 452176667Sjfv /* Function pointers */ 453176667Sjfv 454176667Sjfv /* bus type/speed/width */ 455176667Sjfv mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 456176667Sjfv /* reset */ 457203049Sjfv if (mac->type >= e1000_82580) 458200243Sjfv mac->ops.reset_hw = e1000_reset_hw_82580; 459200243Sjfv else 460176667Sjfv mac->ops.reset_hw = e1000_reset_hw_82575; 461176667Sjfv /* hw initialization */ 462267935Sjfv if ((mac->type == e1000_i210) || (mac->type == e1000_i211)) 463267935Sjfv mac->ops.init_hw = e1000_init_hw_i210; 464267935Sjfv else 465176667Sjfv mac->ops.init_hw = e1000_init_hw_82575; 466176667Sjfv /* link setup */ 467176667Sjfv mac->ops.setup_link = e1000_setup_link_generic; 468176667Sjfv /* physical interface link setup */ 469176667Sjfv mac->ops.setup_physical_interface = 470228386Sjfv (hw->phy.media_type == e1000_media_type_copper) 471228386Sjfv ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575; 472181027Sjfv /* physical interface shutdown */ 473200243Sjfv mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 474203049Sjfv /* physical interface power up */ 475203049Sjfv mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 476176667Sjfv /* check for link */ 477176667Sjfv mac->ops.check_for_link = e1000_check_for_link_82575; 478176667Sjfv /* read mac address */ 479176667Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 480203049Sjfv /* configure collision distance */ 481203049Sjfv mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 482176667Sjfv /* multicast address update */ 483190872Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 484256200Sjfv if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) { 485228386Sjfv /* writing VFTA */ 486228386Sjfv mac->ops.write_vfta = e1000_write_vfta_i350; 487228386Sjfv /* clearing VFTA */ 488228386Sjfv mac->ops.clear_vfta = e1000_clear_vfta_i350; 489228386Sjfv } else { 490228386Sjfv /* writing VFTA */ 491228386Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 492228386Sjfv /* clearing VFTA */ 493228386Sjfv mac->ops.clear_vfta = e1000_clear_vfta_generic; 494228386Sjfv } 495247064Sjfv if (hw->mac.type >= e1000_82580) 496247064Sjfv mac->ops.validate_mdi_setting = 497247064Sjfv e1000_validate_mdi_setting_crossover_generic; 498190872Sjfv /* ID LED init */ 499190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 500176667Sjfv /* blink LED */ 501176667Sjfv mac->ops.blink_led = e1000_blink_led_generic; 502176667Sjfv /* setup LED */ 503176667Sjfv mac->ops.setup_led = e1000_setup_led_generic; 504176667Sjfv /* cleanup LED */ 505176667Sjfv mac->ops.cleanup_led = e1000_cleanup_led_generic; 506176667Sjfv /* turn on/off LED */ 507176667Sjfv mac->ops.led_on = e1000_led_on_generic; 508176667Sjfv mac->ops.led_off = e1000_led_off_generic; 509176667Sjfv /* clear hardware counters */ 510176667Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 511176667Sjfv /* link info */ 512176667Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 513238148Sjfv /* acquire SW_FW sync */ 514238148Sjfv mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575; 515238148Sjfv mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575; 516238148Sjfv if (mac->type >= e1000_i210) { 517238148Sjfv mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210; 518238148Sjfv mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210; 519238148Sjfv } 520176667Sjfv 521200243Sjfv /* set lan id for port to determine which phy lock to use */ 522200243Sjfv hw->mac.ops.set_lan_id(hw); 523200243Sjfv 524185353Sjfv return E1000_SUCCESS; 525176667Sjfv} 526176667Sjfv 527176667Sjfv/** 528176667Sjfv * e1000_init_function_pointers_82575 - Init func ptrs. 529176667Sjfv * @hw: pointer to the HW structure 530176667Sjfv * 531185353Sjfv * Called to initialize all function pointers and parameters. 532176667Sjfv **/ 533176667Sjfvvoid e1000_init_function_pointers_82575(struct e1000_hw *hw) 534176667Sjfv{ 535176667Sjfv DEBUGFUNC("e1000_init_function_pointers_82575"); 536176667Sjfv 537176667Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82575; 538176667Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 539176667Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82575; 540213234Sjfv hw->mbx.ops.init_params = e1000_init_mbx_params_pf; 541176667Sjfv} 542176667Sjfv 543176667Sjfv/** 544176667Sjfv * e1000_acquire_phy_82575 - Acquire rights to access PHY 545176667Sjfv * @hw: pointer to the HW structure 546176667Sjfv * 547185353Sjfv * Acquire access rights to the correct PHY. 548176667Sjfv **/ 549176667Sjfvstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 550176667Sjfv{ 551194865Sjfv u16 mask = E1000_SWFW_PHY0_SM; 552176667Sjfv 553176667Sjfv DEBUGFUNC("e1000_acquire_phy_82575"); 554176667Sjfv 555194865Sjfv if (hw->bus.func == E1000_FUNC_1) 556194865Sjfv mask = E1000_SWFW_PHY1_SM; 557200243Sjfv else if (hw->bus.func == E1000_FUNC_2) 558200243Sjfv mask = E1000_SWFW_PHY2_SM; 559200243Sjfv else if (hw->bus.func == E1000_FUNC_3) 560200243Sjfv mask = E1000_SWFW_PHY3_SM; 561176667Sjfv 562238148Sjfv return hw->mac.ops.acquire_swfw_sync(hw, mask); 563176667Sjfv} 564176667Sjfv 565176667Sjfv/** 566176667Sjfv * e1000_release_phy_82575 - Release rights to access PHY 567176667Sjfv * @hw: pointer to the HW structure 568176667Sjfv * 569185353Sjfv * A wrapper to release access rights to the correct PHY. 570176667Sjfv **/ 571176667Sjfvstatic void e1000_release_phy_82575(struct e1000_hw *hw) 572176667Sjfv{ 573194865Sjfv u16 mask = E1000_SWFW_PHY0_SM; 574176667Sjfv 575176667Sjfv DEBUGFUNC("e1000_release_phy_82575"); 576176667Sjfv 577194865Sjfv if (hw->bus.func == E1000_FUNC_1) 578194865Sjfv mask = E1000_SWFW_PHY1_SM; 579200243Sjfv else if (hw->bus.func == E1000_FUNC_2) 580200243Sjfv mask = E1000_SWFW_PHY2_SM; 581200243Sjfv else if (hw->bus.func == E1000_FUNC_3) 582200243Sjfv mask = E1000_SWFW_PHY3_SM; 583194865Sjfv 584238148Sjfv hw->mac.ops.release_swfw_sync(hw, mask); 585176667Sjfv} 586176667Sjfv 587176667Sjfv/** 588176667Sjfv * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 589176667Sjfv * @hw: pointer to the HW structure 590176667Sjfv * @offset: register offset to be read 591176667Sjfv * @data: pointer to the read data 592176667Sjfv * 593176667Sjfv * Reads the PHY register at offset using the serial gigabit media independent 594176667Sjfv * interface and stores the retrieved information in data. 595176667Sjfv **/ 596176667Sjfvstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 597228386Sjfv u16 *data) 598176667Sjfv{ 599200243Sjfv s32 ret_val = -E1000_ERR_PARAM; 600176667Sjfv 601176667Sjfv DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 602176667Sjfv 603176667Sjfv if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 604176667Sjfv DEBUGOUT1("PHY Address %u is out of range\n", offset); 605200243Sjfv goto out; 606176667Sjfv } 607176667Sjfv 608200243Sjfv ret_val = hw->phy.ops.acquire(hw); 609200243Sjfv if (ret_val) 610200243Sjfv goto out; 611176667Sjfv 612200243Sjfv ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 613176667Sjfv 614200243Sjfv hw->phy.ops.release(hw); 615176667Sjfv 616200243Sjfvout: 617200243Sjfv return ret_val; 618176667Sjfv} 619176667Sjfv 620176667Sjfv/** 621176667Sjfv * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 622176667Sjfv * @hw: pointer to the HW structure 623176667Sjfv * @offset: register offset to write to 624176667Sjfv * @data: data to write at register offset 625176667Sjfv * 626176667Sjfv * Writes the data to PHY register at the offset using the serial gigabit 627176667Sjfv * media independent interface. 628176667Sjfv **/ 629176667Sjfvstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 630228386Sjfv u16 data) 631176667Sjfv{ 632200243Sjfv s32 ret_val = -E1000_ERR_PARAM; 633176667Sjfv 634176667Sjfv DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 635176667Sjfv 636176667Sjfv if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 637176667Sjfv DEBUGOUT1("PHY Address %d is out of range\n", offset); 638200243Sjfv goto out; 639176667Sjfv } 640176667Sjfv 641200243Sjfv ret_val = hw->phy.ops.acquire(hw); 642200243Sjfv if (ret_val) 643200243Sjfv goto out; 644176667Sjfv 645200243Sjfv ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 646176667Sjfv 647200243Sjfv hw->phy.ops.release(hw); 648176667Sjfv 649200243Sjfvout: 650200243Sjfv return ret_val; 651176667Sjfv} 652176667Sjfv 653176667Sjfv/** 654176667Sjfv * e1000_get_phy_id_82575 - Retrieve PHY addr and id 655176667Sjfv * @hw: pointer to the HW structure 656176667Sjfv * 657176667Sjfv * Retrieves the PHY address and ID for both PHY's which do and do not use 658176667Sjfv * sgmi interface. 659176667Sjfv **/ 660176667Sjfvstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 661176667Sjfv{ 662176667Sjfv struct e1000_phy_info *phy = &hw->phy; 663176667Sjfv s32 ret_val = E1000_SUCCESS; 664176667Sjfv u16 phy_id; 665200243Sjfv u32 ctrl_ext; 666213234Sjfv u32 mdic; 667176667Sjfv 668176667Sjfv DEBUGFUNC("e1000_get_phy_id_82575"); 669176667Sjfv 670256200Sjfv /* some i354 devices need an extra read for phy id */ 671256200Sjfv if (hw->mac.type == e1000_i354) 672256200Sjfv e1000_get_phy_id(hw); 673256200Sjfv 674176667Sjfv /* 675176667Sjfv * For SGMII PHYs, we try the list of possible addresses until 676176667Sjfv * we find one that works. For non-SGMII PHYs 677176667Sjfv * (e.g. integrated copper PHYs), an address of 1 should 678176667Sjfv * work. The result of this function should mean phy->phy_addr 679176667Sjfv * and phy->id are set correctly. 680176667Sjfv */ 681200243Sjfv if (!e1000_sgmii_active_82575(hw)) { 682176667Sjfv phy->addr = 1; 683176667Sjfv ret_val = e1000_get_phy_id(hw); 684176667Sjfv goto out; 685176667Sjfv } 686176667Sjfv 687213234Sjfv if (e1000_sgmii_uses_mdio_82575(hw)) { 688213234Sjfv switch (hw->mac.type) { 689213234Sjfv case e1000_82575: 690213234Sjfv case e1000_82576: 691213234Sjfv mdic = E1000_READ_REG(hw, E1000_MDIC); 692213234Sjfv mdic &= E1000_MDIC_PHY_MASK; 693213234Sjfv phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 694213234Sjfv break; 695213234Sjfv case e1000_82580: 696218530Sjfv case e1000_i350: 697256200Sjfv case e1000_i354: 698247064Sjfv case e1000_i210: 699247064Sjfv case e1000_i211: 700213234Sjfv mdic = E1000_READ_REG(hw, E1000_MDICNFG); 701213234Sjfv mdic &= E1000_MDICNFG_PHY_MASK; 702213234Sjfv phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 703213234Sjfv break; 704213234Sjfv default: 705213234Sjfv ret_val = -E1000_ERR_PHY; 706213234Sjfv goto out; 707213234Sjfv break; 708213234Sjfv } 709213234Sjfv ret_val = e1000_get_phy_id(hw); 710213234Sjfv goto out; 711213234Sjfv } 712213234Sjfv 713200243Sjfv /* Power on sgmii phy if it is disabled */ 714200243Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 715200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, 716228386Sjfv ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 717200243Sjfv E1000_WRITE_FLUSH(hw); 718200243Sjfv msec_delay(300); 719200243Sjfv 720176667Sjfv /* 721176667Sjfv * The address field in the I2CCMD register is 3 bits and 0 is invalid. 722176667Sjfv * Therefore, we need to test 1-7 723176667Sjfv */ 724176667Sjfv for (phy->addr = 1; phy->addr < 8; phy->addr++) { 725176667Sjfv ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 726176667Sjfv if (ret_val == E1000_SUCCESS) { 727176667Sjfv DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 728228386Sjfv phy_id, phy->addr); 729176667Sjfv /* 730176667Sjfv * At the time of this writing, The M88 part is 731176667Sjfv * the only supported SGMII PHY product. 732176667Sjfv */ 733176667Sjfv if (phy_id == M88_VENDOR) 734176667Sjfv break; 735176667Sjfv } else { 736176667Sjfv DEBUGOUT1("PHY address %u was unreadable\n", 737228386Sjfv phy->addr); 738176667Sjfv } 739176667Sjfv } 740176667Sjfv 741176667Sjfv /* A valid PHY type couldn't be found. */ 742176667Sjfv if (phy->addr == 8) { 743176667Sjfv phy->addr = 0; 744176667Sjfv ret_val = -E1000_ERR_PHY; 745200243Sjfv } else { 746200243Sjfv ret_val = e1000_get_phy_id(hw); 747176667Sjfv } 748176667Sjfv 749200243Sjfv /* restore previous sfp cage power state */ 750200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 751176667Sjfv 752176667Sjfvout: 753176667Sjfv return ret_val; 754176667Sjfv} 755176667Sjfv 756176667Sjfv/** 757176667Sjfv * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 758176667Sjfv * @hw: pointer to the HW structure 759176667Sjfv * 760176667Sjfv * Resets the PHY using the serial gigabit media independent interface. 761176667Sjfv **/ 762176667Sjfvstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 763176667Sjfv{ 764176667Sjfv s32 ret_val = E1000_SUCCESS; 765267935Sjfv struct e1000_phy_info *phy = &hw->phy; 766176667Sjfv 767176667Sjfv DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 768176667Sjfv 769176667Sjfv /* 770178523Sjfv * This isn't a TRUE "hard" reset, but is the only reset 771176667Sjfv * available to us at this time. 772176667Sjfv */ 773176667Sjfv 774176667Sjfv DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 775176667Sjfv 776176667Sjfv if (!(hw->phy.ops.write_reg)) 777176667Sjfv goto out; 778176667Sjfv 779176667Sjfv /* 780176667Sjfv * SFP documentation requires the following to configure the SPF module 781176667Sjfv * to work on SGMII. No further documentation is given. 782176667Sjfv */ 783176667Sjfv ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 784176667Sjfv if (ret_val) 785176667Sjfv goto out; 786176667Sjfv 787176667Sjfv ret_val = hw->phy.ops.commit(hw); 788267935Sjfv if (ret_val) 789267935Sjfv goto out; 790176667Sjfv 791267935Sjfv if (phy->id == M88E1512_E_PHY_ID) 792267935Sjfv ret_val = e1000_initialize_M88E1512_phy(hw); 793176667Sjfvout: 794176667Sjfv return ret_val; 795176667Sjfv} 796176667Sjfv 797176667Sjfv/** 798176667Sjfv * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 799176667Sjfv * @hw: pointer to the HW structure 800176667Sjfv * @active: TRUE to enable LPLU, FALSE to disable 801176667Sjfv * 802176667Sjfv * Sets the LPLU D0 state according to the active flag. When 803176667Sjfv * activating LPLU this function also disables smart speed 804176667Sjfv * and vice versa. LPLU will not be activated unless the 805176667Sjfv * device autonegotiation advertisement meets standards of 806176667Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 807176667Sjfv * This is a function pointer entry point only called by 808176667Sjfv * PHY setup routines. 809176667Sjfv **/ 810176667Sjfvstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 811176667Sjfv{ 812176667Sjfv struct e1000_phy_info *phy = &hw->phy; 813176667Sjfv s32 ret_val = E1000_SUCCESS; 814176667Sjfv u16 data; 815176667Sjfv 816176667Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 817176667Sjfv 818176667Sjfv if (!(hw->phy.ops.read_reg)) 819176667Sjfv goto out; 820176667Sjfv 821176667Sjfv ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 822176667Sjfv if (ret_val) 823176667Sjfv goto out; 824176667Sjfv 825176667Sjfv if (active) { 826176667Sjfv data |= IGP02E1000_PM_D0_LPLU; 827176667Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 828228386Sjfv data); 829176667Sjfv if (ret_val) 830176667Sjfv goto out; 831176667Sjfv 832176667Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 833176667Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 834228386Sjfv &data); 835176667Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 836176667Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 837228386Sjfv data); 838176667Sjfv if (ret_val) 839176667Sjfv goto out; 840176667Sjfv } else { 841176667Sjfv data &= ~IGP02E1000_PM_D0_LPLU; 842176667Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 843228386Sjfv data); 844176667Sjfv /* 845176667Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 846176667Sjfv * during Dx states where the power conservation is most 847176667Sjfv * important. During driver activity we should enable 848176667Sjfv * SmartSpeed, so performance is maintained. 849176667Sjfv */ 850176667Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 851176667Sjfv ret_val = phy->ops.read_reg(hw, 852228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 853228386Sjfv &data); 854176667Sjfv if (ret_val) 855176667Sjfv goto out; 856176667Sjfv 857176667Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 858176667Sjfv ret_val = phy->ops.write_reg(hw, 859228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 860228386Sjfv data); 861176667Sjfv if (ret_val) 862176667Sjfv goto out; 863176667Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 864176667Sjfv ret_val = phy->ops.read_reg(hw, 865228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 866228386Sjfv &data); 867176667Sjfv if (ret_val) 868176667Sjfv goto out; 869176667Sjfv 870176667Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 871176667Sjfv ret_val = phy->ops.write_reg(hw, 872228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 873228386Sjfv data); 874176667Sjfv if (ret_val) 875176667Sjfv goto out; 876176667Sjfv } 877176667Sjfv } 878176667Sjfv 879176667Sjfvout: 880176667Sjfv return ret_val; 881176667Sjfv} 882176667Sjfv 883176667Sjfv/** 884218530Sjfv * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 885218530Sjfv * @hw: pointer to the HW structure 886218530Sjfv * @active: TRUE to enable LPLU, FALSE to disable 887218530Sjfv * 888218530Sjfv * Sets the LPLU D0 state according to the active flag. When 889218530Sjfv * activating LPLU this function also disables smart speed 890218530Sjfv * and vice versa. LPLU will not be activated unless the 891218530Sjfv * device autonegotiation advertisement meets standards of 892218530Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 893218530Sjfv * This is a function pointer entry point only called by 894218530Sjfv * PHY setup routines. 895218530Sjfv **/ 896218530Sjfvstatic s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 897218530Sjfv{ 898218530Sjfv struct e1000_phy_info *phy = &hw->phy; 899238148Sjfv u32 data; 900218530Sjfv 901218530Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82580"); 902218530Sjfv 903218530Sjfv data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 904218530Sjfv 905218530Sjfv if (active) { 906218530Sjfv data |= E1000_82580_PM_D0_LPLU; 907218530Sjfv 908218530Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 909218530Sjfv data &= ~E1000_82580_PM_SPD; 910218530Sjfv } else { 911218530Sjfv data &= ~E1000_82580_PM_D0_LPLU; 912218530Sjfv 913218530Sjfv /* 914218530Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 915218530Sjfv * during Dx states where the power conservation is most 916218530Sjfv * important. During driver activity we should enable 917218530Sjfv * SmartSpeed, so performance is maintained. 918218530Sjfv */ 919228386Sjfv if (phy->smart_speed == e1000_smart_speed_on) 920218530Sjfv data |= E1000_82580_PM_SPD; 921228386Sjfv else if (phy->smart_speed == e1000_smart_speed_off) 922218530Sjfv data &= ~E1000_82580_PM_SPD; 923218530Sjfv } 924218530Sjfv 925218530Sjfv E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 926267935Sjfv return E1000_SUCCESS; 927218530Sjfv} 928218530Sjfv 929218530Sjfv/** 930218530Sjfv * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3 931218530Sjfv * @hw: pointer to the HW structure 932218530Sjfv * @active: boolean used to enable/disable lplu 933218530Sjfv * 934218530Sjfv * Success returns 0, Failure returns 1 935218530Sjfv * 936218530Sjfv * The low power link up (lplu) state is set to the power management level D3 937218530Sjfv * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 938218530Sjfv * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 939218530Sjfv * is used during Dx states where the power conservation is most important. 940218530Sjfv * During driver activity, SmartSpeed should be enabled so performance is 941218530Sjfv * maintained. 942218530Sjfv **/ 943218530Sjfvs32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 944218530Sjfv{ 945218530Sjfv struct e1000_phy_info *phy = &hw->phy; 946238148Sjfv u32 data; 947218530Sjfv 948218530Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_82580"); 949218530Sjfv 950218530Sjfv data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 951218530Sjfv 952218530Sjfv if (!active) { 953218530Sjfv data &= ~E1000_82580_PM_D3_LPLU; 954218530Sjfv /* 955218530Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 956218530Sjfv * during Dx states where the power conservation is most 957218530Sjfv * important. During driver activity we should enable 958218530Sjfv * SmartSpeed, so performance is maintained. 959218530Sjfv */ 960228386Sjfv if (phy->smart_speed == e1000_smart_speed_on) 961218530Sjfv data |= E1000_82580_PM_SPD; 962228386Sjfv else if (phy->smart_speed == e1000_smart_speed_off) 963218530Sjfv data &= ~E1000_82580_PM_SPD; 964218530Sjfv } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 965228386Sjfv (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 966228386Sjfv (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 967218530Sjfv data |= E1000_82580_PM_D3_LPLU; 968218530Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 969218530Sjfv data &= ~E1000_82580_PM_SPD; 970218530Sjfv } 971218530Sjfv 972218530Sjfv E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 973267935Sjfv return E1000_SUCCESS; 974218530Sjfv} 975218530Sjfv 976218530Sjfv/** 977176667Sjfv * e1000_acquire_nvm_82575 - Request for access to EEPROM 978176667Sjfv * @hw: pointer to the HW structure 979176667Sjfv * 980176667Sjfv * Acquire the necessary semaphores for exclusive access to the EEPROM. 981176667Sjfv * Set the EEPROM access request bit and wait for EEPROM access grant bit. 982176667Sjfv * Return successful if access grant bit set, else clear the request for 983176667Sjfv * EEPROM access and return -E1000_ERR_NVM (-1). 984176667Sjfv **/ 985176667Sjfvstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 986176667Sjfv{ 987267935Sjfv s32 ret_val = E1000_SUCCESS; 988176667Sjfv 989176667Sjfv DEBUGFUNC("e1000_acquire_nvm_82575"); 990176667Sjfv 991176667Sjfv ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 992176667Sjfv if (ret_val) 993176667Sjfv goto out; 994228386Sjfv 995228386Sjfv /* 996228386Sjfv * Check if there is some access 997228386Sjfv * error this access may hook on 998228386Sjfv */ 999228386Sjfv if (hw->mac.type == e1000_i350) { 1000228386Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 1001228386Sjfv if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT | 1002228386Sjfv E1000_EECD_TIMEOUT)) { 1003228386Sjfv /* Clear all access error flags */ 1004228386Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd | 1005228386Sjfv E1000_EECD_ERROR_CLR); 1006228386Sjfv DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 1007228386Sjfv } 1008228386Sjfv } 1009267935Sjfv 1010228386Sjfv if (hw->mac.type == e1000_82580) { 1011228386Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 1012228386Sjfv if (eecd & E1000_EECD_BLOCKED) { 1013228386Sjfv /* Clear access error flag */ 1014228386Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd | 1015228386Sjfv E1000_EECD_BLOCKED); 1016228386Sjfv DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 1017228386Sjfv } 1018228386Sjfv } 1019228386Sjfv 1020238148Sjfv ret_val = e1000_acquire_nvm_generic(hw); 1021176667Sjfv if (ret_val) 1022176667Sjfv e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 1023176667Sjfv 1024176667Sjfvout: 1025176667Sjfv return ret_val; 1026176667Sjfv} 1027176667Sjfv 1028176667Sjfv/** 1029176667Sjfv * e1000_release_nvm_82575 - Release exclusive access to EEPROM 1030176667Sjfv * @hw: pointer to the HW structure 1031176667Sjfv * 1032176667Sjfv * Stop any current commands to the EEPROM and clear the EEPROM request bit, 1033176667Sjfv * then release the semaphores acquired. 1034176667Sjfv **/ 1035176667Sjfvstatic void e1000_release_nvm_82575(struct e1000_hw *hw) 1036176667Sjfv{ 1037176667Sjfv DEBUGFUNC("e1000_release_nvm_82575"); 1038176667Sjfv 1039238148Sjfv e1000_release_nvm_generic(hw); 1040238148Sjfv 1041176667Sjfv e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 1042176667Sjfv} 1043176667Sjfv 1044176667Sjfv/** 1045176667Sjfv * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 1046176667Sjfv * @hw: pointer to the HW structure 1047176667Sjfv * @mask: specifies which semaphore to acquire 1048176667Sjfv * 1049176667Sjfv * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 1050176667Sjfv * will also specify which port we're acquiring the lock for. 1051176667Sjfv **/ 1052176667Sjfvstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1053176667Sjfv{ 1054176667Sjfv u32 swfw_sync; 1055176667Sjfv u32 swmask = mask; 1056176667Sjfv u32 fwmask = mask << 16; 1057176667Sjfv s32 ret_val = E1000_SUCCESS; 1058287112Ssbruno s32 i = 0, timeout = 200; 1059176667Sjfv 1060176667Sjfv DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 1061176667Sjfv 1062176667Sjfv while (i < timeout) { 1063176667Sjfv if (e1000_get_hw_semaphore_generic(hw)) { 1064176667Sjfv ret_val = -E1000_ERR_SWFW_SYNC; 1065176667Sjfv goto out; 1066176667Sjfv } 1067176667Sjfv 1068176667Sjfv swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1069176667Sjfv if (!(swfw_sync & (fwmask | swmask))) 1070176667Sjfv break; 1071176667Sjfv 1072176667Sjfv /* 1073176667Sjfv * Firmware currently using resource (fwmask) 1074176667Sjfv * or other software thread using resource (swmask) 1075176667Sjfv */ 1076176667Sjfv e1000_put_hw_semaphore_generic(hw); 1077176667Sjfv msec_delay_irq(5); 1078176667Sjfv i++; 1079176667Sjfv } 1080176667Sjfv 1081176667Sjfv if (i == timeout) { 1082176667Sjfv DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1083176667Sjfv ret_val = -E1000_ERR_SWFW_SYNC; 1084176667Sjfv goto out; 1085176667Sjfv } 1086176667Sjfv 1087176667Sjfv swfw_sync |= swmask; 1088176667Sjfv E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1089176667Sjfv 1090176667Sjfv e1000_put_hw_semaphore_generic(hw); 1091176667Sjfv 1092176667Sjfvout: 1093176667Sjfv return ret_val; 1094176667Sjfv} 1095176667Sjfv 1096176667Sjfv/** 1097176667Sjfv * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 1098176667Sjfv * @hw: pointer to the HW structure 1099176667Sjfv * @mask: specifies which semaphore to acquire 1100176667Sjfv * 1101176667Sjfv * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1102176667Sjfv * will also specify which port we're releasing the lock for. 1103176667Sjfv **/ 1104176667Sjfvstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1105176667Sjfv{ 1106176667Sjfv u32 swfw_sync; 1107176667Sjfv 1108176667Sjfv DEBUGFUNC("e1000_release_swfw_sync_82575"); 1109176667Sjfv 1110228386Sjfv while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 1111228386Sjfv ; /* Empty */ 1112176667Sjfv 1113176667Sjfv swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1114176667Sjfv swfw_sync &= ~mask; 1115176667Sjfv E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1116176667Sjfv 1117176667Sjfv e1000_put_hw_semaphore_generic(hw); 1118176667Sjfv} 1119176667Sjfv 1120176667Sjfv/** 1121176667Sjfv * e1000_get_cfg_done_82575 - Read config done bit 1122176667Sjfv * @hw: pointer to the HW structure 1123176667Sjfv * 1124176667Sjfv * Read the management control register for the config done bit for 1125176667Sjfv * completion status. NOTE: silicon which is EEPROM-less will fail trying 1126176667Sjfv * to read the config done bit, so an error is *ONLY* logged and returns 1127176667Sjfv * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 1128176667Sjfv * would not be able to be reset or change link. 1129176667Sjfv **/ 1130176667Sjfvstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 1131176667Sjfv{ 1132176667Sjfv s32 timeout = PHY_CFG_TIMEOUT; 1133176667Sjfv u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1134176667Sjfv 1135176667Sjfv DEBUGFUNC("e1000_get_cfg_done_82575"); 1136176667Sjfv 1137194865Sjfv if (hw->bus.func == E1000_FUNC_1) 1138176667Sjfv mask = E1000_NVM_CFG_DONE_PORT_1; 1139200243Sjfv else if (hw->bus.func == E1000_FUNC_2) 1140200243Sjfv mask = E1000_NVM_CFG_DONE_PORT_2; 1141200243Sjfv else if (hw->bus.func == E1000_FUNC_3) 1142200243Sjfv mask = E1000_NVM_CFG_DONE_PORT_3; 1143176667Sjfv while (timeout) { 1144176667Sjfv if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 1145176667Sjfv break; 1146176667Sjfv msec_delay(1); 1147176667Sjfv timeout--; 1148176667Sjfv } 1149200243Sjfv if (!timeout) 1150176667Sjfv DEBUGOUT("MNG configuration cycle has not completed.\n"); 1151176667Sjfv 1152176667Sjfv /* If EEPROM is not marked present, init the PHY manually */ 1153238148Sjfv if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 1154200243Sjfv (hw->phy.type == e1000_phy_igp_3)) 1155176667Sjfv e1000_phy_init_script_igp3(hw); 1156176667Sjfv 1157267935Sjfv return E1000_SUCCESS; 1158176667Sjfv} 1159176667Sjfv 1160176667Sjfv/** 1161176667Sjfv * e1000_get_link_up_info_82575 - Get link speed/duplex info 1162176667Sjfv * @hw: pointer to the HW structure 1163176667Sjfv * @speed: stores the current speed 1164176667Sjfv * @duplex: stores the current duplex 1165176667Sjfv * 1166176667Sjfv * This is a wrapper function, if using the serial gigabit media independent 1167176667Sjfv * interface, use PCS to retrieve the link speed and duplex information. 1168176667Sjfv * Otherwise, use the generic function to get the link speed and duplex info. 1169176667Sjfv **/ 1170176667Sjfvstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1171228386Sjfv u16 *duplex) 1172176667Sjfv{ 1173176667Sjfv s32 ret_val; 1174176667Sjfv 1175176667Sjfv DEBUGFUNC("e1000_get_link_up_info_82575"); 1176176667Sjfv 1177200243Sjfv if (hw->phy.media_type != e1000_media_type_copper) 1178176667Sjfv ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 1179228386Sjfv duplex); 1180200243Sjfv else 1181176667Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 1182228386Sjfv duplex); 1183176667Sjfv 1184176667Sjfv return ret_val; 1185176667Sjfv} 1186176667Sjfv 1187176667Sjfv/** 1188176667Sjfv * e1000_check_for_link_82575 - Check for link 1189176667Sjfv * @hw: pointer to the HW structure 1190176667Sjfv * 1191176667Sjfv * If sgmii is enabled, then use the pcs register to determine link, otherwise 1192176667Sjfv * use the generic interface for determining link. 1193176667Sjfv **/ 1194176667Sjfvstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw) 1195176667Sjfv{ 1196176667Sjfv s32 ret_val; 1197176667Sjfv u16 speed, duplex; 1198176667Sjfv 1199176667Sjfv DEBUGFUNC("e1000_check_for_link_82575"); 1200176667Sjfv 1201200243Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 1202176667Sjfv ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 1203228386Sjfv &duplex); 1204190872Sjfv /* 1205190872Sjfv * Use this flag to determine if link needs to be checked or 1206190872Sjfv * not. If we have link clear the flag so that we do not 1207190872Sjfv * continue to check for link. 1208190872Sjfv */ 1209190872Sjfv hw->mac.get_link_status = !hw->mac.serdes_has_link; 1210238148Sjfv 1211247064Sjfv /* 1212247064Sjfv * Configure Flow Control now that Auto-Neg has completed. 1213247064Sjfv * First, we need to restore the desired flow control 1214247064Sjfv * settings because we may have had to re-autoneg with a 1215247064Sjfv * different link partner. 1216247064Sjfv */ 1217247064Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1218247064Sjfv if (ret_val) 1219247064Sjfv DEBUGOUT("Error configuring flow control\n"); 1220190872Sjfv } else { 1221176667Sjfv ret_val = e1000_check_for_copper_link_generic(hw); 1222190872Sjfv } 1223176667Sjfv 1224176667Sjfv return ret_val; 1225176667Sjfv} 1226176667Sjfv 1227176667Sjfv/** 1228256200Sjfv * e1000_check_for_link_media_swap - Check which M88E1112 interface linked 1229256200Sjfv * @hw: pointer to the HW structure 1230256200Sjfv * 1231256200Sjfv * Poll the M88E1112 interfaces to see which interface achieved link. 1232256200Sjfv */ 1233256200Sjfvstatic s32 e1000_check_for_link_media_swap(struct e1000_hw *hw) 1234256200Sjfv{ 1235256200Sjfv struct e1000_phy_info *phy = &hw->phy; 1236256200Sjfv s32 ret_val; 1237256200Sjfv u16 data; 1238256200Sjfv u8 port = 0; 1239256200Sjfv 1240256200Sjfv DEBUGFUNC("e1000_check_for_link_media_swap"); 1241256200Sjfv 1242295323Serj /* Check for copper. */ 1243256200Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 1244256200Sjfv if (ret_val) 1245256200Sjfv return ret_val; 1246256200Sjfv 1247256200Sjfv ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 1248256200Sjfv if (ret_val) 1249256200Sjfv return ret_val; 1250256200Sjfv 1251256200Sjfv if (data & E1000_M88E1112_STATUS_LINK) 1252256200Sjfv port = E1000_MEDIA_PORT_COPPER; 1253256200Sjfv 1254295323Serj /* Check for other. */ 1255256200Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); 1256256200Sjfv if (ret_val) 1257256200Sjfv return ret_val; 1258256200Sjfv 1259256200Sjfv ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 1260256200Sjfv if (ret_val) 1261256200Sjfv return ret_val; 1262256200Sjfv 1263256200Sjfv if (data & E1000_M88E1112_STATUS_LINK) 1264256200Sjfv port = E1000_MEDIA_PORT_OTHER; 1265256200Sjfv 1266256200Sjfv /* Determine if a swap needs to happen. */ 1267256200Sjfv if (port && (hw->dev_spec._82575.media_port != port)) { 1268256200Sjfv hw->dev_spec._82575.media_port = port; 1269256200Sjfv hw->dev_spec._82575.media_changed = TRUE; 1270295323Serj } 1271295323Serj 1272295323Serj if (port == E1000_MEDIA_PORT_COPPER) { 1273295323Serj /* reset page to 0 */ 1274295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 1275295323Serj if (ret_val) 1276295323Serj return ret_val; 1277295323Serj e1000_check_for_link_82575(hw); 1278256200Sjfv } else { 1279295323Serj e1000_check_for_link_82575(hw); 1280295323Serj /* reset page to 0 */ 1281295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 1282295323Serj if (ret_val) 1283295323Serj return ret_val; 1284256200Sjfv } 1285256200Sjfv 1286256200Sjfv return E1000_SUCCESS; 1287256200Sjfv} 1288256200Sjfv 1289256200Sjfv/** 1290203049Sjfv * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1291203049Sjfv * @hw: pointer to the HW structure 1292203049Sjfv **/ 1293203049Sjfvstatic void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 1294203049Sjfv{ 1295203049Sjfv u32 reg; 1296203049Sjfv 1297203049Sjfv DEBUGFUNC("e1000_power_up_serdes_link_82575"); 1298203049Sjfv 1299203049Sjfv if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1300203049Sjfv !e1000_sgmii_active_82575(hw)) 1301203049Sjfv return; 1302203049Sjfv 1303203049Sjfv /* Enable PCS to turn on link */ 1304203049Sjfv reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1305203049Sjfv reg |= E1000_PCS_CFG_PCS_EN; 1306203049Sjfv E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1307203049Sjfv 1308203049Sjfv /* Power up the laser */ 1309203049Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1310203049Sjfv reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1311203049Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1312203049Sjfv 1313203049Sjfv /* flush the write to verify completion */ 1314203049Sjfv E1000_WRITE_FLUSH(hw); 1315203049Sjfv msec_delay(1); 1316203049Sjfv} 1317203049Sjfv 1318203049Sjfv/** 1319176667Sjfv * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1320176667Sjfv * @hw: pointer to the HW structure 1321176667Sjfv * @speed: stores the current speed 1322176667Sjfv * @duplex: stores the current duplex 1323176667Sjfv * 1324176667Sjfv * Using the physical coding sub-layer (PCS), retrieve the current speed and 1325176667Sjfv * duplex, then store the values in the pointers provided. 1326176667Sjfv **/ 1327176667Sjfvstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 1328228386Sjfv u16 *speed, u16 *duplex) 1329176667Sjfv{ 1330176667Sjfv struct e1000_mac_info *mac = &hw->mac; 1331176667Sjfv u32 pcs; 1332256200Sjfv u32 status; 1333176667Sjfv 1334176667Sjfv DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 1335176667Sjfv 1336176667Sjfv /* 1337176667Sjfv * Read the PCS Status register for link state. For non-copper mode, 1338176667Sjfv * the status register is not accurate. The PCS status register is 1339176667Sjfv * used instead. 1340176667Sjfv */ 1341176667Sjfv pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1342176667Sjfv 1343176667Sjfv /* 1344238148Sjfv * The link up bit determines when link is up on autoneg. 1345176667Sjfv */ 1346238148Sjfv if (pcs & E1000_PCS_LSTS_LINK_OK) { 1347176667Sjfv mac->serdes_has_link = TRUE; 1348176667Sjfv 1349176667Sjfv /* Detect and store PCS speed */ 1350228386Sjfv if (pcs & E1000_PCS_LSTS_SPEED_1000) 1351176667Sjfv *speed = SPEED_1000; 1352228386Sjfv else if (pcs & E1000_PCS_LSTS_SPEED_100) 1353176667Sjfv *speed = SPEED_100; 1354228386Sjfv else 1355176667Sjfv *speed = SPEED_10; 1356176667Sjfv 1357176667Sjfv /* Detect and store PCS duplex */ 1358228386Sjfv if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1359176667Sjfv *duplex = FULL_DUPLEX; 1360228386Sjfv else 1361176667Sjfv *duplex = HALF_DUPLEX; 1362247064Sjfv 1363256200Sjfv /* Check if it is an I354 2.5Gb backplane connection. */ 1364256200Sjfv if (mac->type == e1000_i354) { 1365256200Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1366256200Sjfv if ((status & E1000_STATUS_2P5_SKU) && 1367256200Sjfv !(status & E1000_STATUS_2P5_SKU_OVER)) { 1368256200Sjfv *speed = SPEED_2500; 1369256200Sjfv *duplex = FULL_DUPLEX; 1370256200Sjfv DEBUGOUT("2500 Mbs, "); 1371256200Sjfv DEBUGOUT("Full Duplex\n"); 1372256200Sjfv } 1373256200Sjfv } 1374256200Sjfv 1375238148Sjfv } else { 1376238148Sjfv mac->serdes_has_link = FALSE; 1377238148Sjfv *speed = 0; 1378238148Sjfv *duplex = 0; 1379176667Sjfv } 1380176667Sjfv 1381176667Sjfv return E1000_SUCCESS; 1382176667Sjfv} 1383176667Sjfv 1384176667Sjfv/** 1385200243Sjfv * e1000_shutdown_serdes_link_82575 - Remove link during power down 1386181027Sjfv * @hw: pointer to the HW structure 1387181027Sjfv * 1388200243Sjfv * In the case of serdes shut down sfp and PCS on driver unload 1389181027Sjfv * when management pass thru is not enabled. 1390181027Sjfv **/ 1391200243Sjfvvoid e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 1392181027Sjfv{ 1393181027Sjfv u32 reg; 1394181027Sjfv 1395203049Sjfv DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 1396203049Sjfv 1397200243Sjfv if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1398200243Sjfv !e1000_sgmii_active_82575(hw)) 1399181027Sjfv return; 1400181027Sjfv 1401203049Sjfv if (!e1000_enable_mng_pass_thru(hw)) { 1402181027Sjfv /* Disable PCS to turn off link */ 1403181027Sjfv reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1404181027Sjfv reg &= ~E1000_PCS_CFG_PCS_EN; 1405181027Sjfv E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1406181027Sjfv 1407181027Sjfv /* shutdown the laser */ 1408181027Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1409200243Sjfv reg |= E1000_CTRL_EXT_SDP3_DATA; 1410181027Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1411181027Sjfv 1412200243Sjfv /* flush the write to verify completion */ 1413181027Sjfv E1000_WRITE_FLUSH(hw); 1414181027Sjfv msec_delay(1); 1415181027Sjfv } 1416181027Sjfv 1417181027Sjfv return; 1418181027Sjfv} 1419181027Sjfv 1420181027Sjfv/** 1421176667Sjfv * e1000_reset_hw_82575 - Reset hardware 1422176667Sjfv * @hw: pointer to the HW structure 1423176667Sjfv * 1424185353Sjfv * This resets the hardware into a known state. 1425176667Sjfv **/ 1426176667Sjfvstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1427176667Sjfv{ 1428218530Sjfv u32 ctrl; 1429176667Sjfv s32 ret_val; 1430176667Sjfv 1431176667Sjfv DEBUGFUNC("e1000_reset_hw_82575"); 1432176667Sjfv 1433176667Sjfv /* 1434176667Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 1435176667Sjfv * on the last TLP read/write transaction when MAC is reset. 1436176667Sjfv */ 1437176667Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 1438228386Sjfv if (ret_val) 1439176667Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1440176667Sjfv 1441194865Sjfv /* set the completion timeout for interface */ 1442194865Sjfv ret_val = e1000_set_pcie_completion_timeout(hw); 1443228386Sjfv if (ret_val) 1444194865Sjfv DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1445194865Sjfv 1446176667Sjfv DEBUGOUT("Masking off all interrupts\n"); 1447176667Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1448176667Sjfv 1449176667Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 1450176667Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1451176667Sjfv E1000_WRITE_FLUSH(hw); 1452176667Sjfv 1453176667Sjfv msec_delay(10); 1454176667Sjfv 1455176667Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1456176667Sjfv 1457176667Sjfv DEBUGOUT("Issuing a global reset to MAC\n"); 1458176667Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1459176667Sjfv 1460176667Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 1461176667Sjfv if (ret_val) { 1462176667Sjfv /* 1463176667Sjfv * When auto config read does not complete, do not 1464176667Sjfv * return with an error. This can happen in situations 1465176667Sjfv * where there is no eeprom and prevents getting link. 1466176667Sjfv */ 1467176667Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 1468176667Sjfv } 1469176667Sjfv 1470176667Sjfv /* If EEPROM is not present, run manual init scripts */ 1471238148Sjfv if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 1472176667Sjfv e1000_reset_init_script_82575(hw); 1473176667Sjfv 1474176667Sjfv /* Clear any pending interrupt events. */ 1475176667Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1476218530Sjfv E1000_READ_REG(hw, E1000_ICR); 1477176667Sjfv 1478190872Sjfv /* Install any alternate MAC address into RAR0 */ 1479190872Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 1480176667Sjfv 1481176667Sjfv return ret_val; 1482176667Sjfv} 1483176667Sjfv 1484176667Sjfv/** 1485176667Sjfv * e1000_init_hw_82575 - Initialize hardware 1486176667Sjfv * @hw: pointer to the HW structure 1487176667Sjfv * 1488176667Sjfv * This inits the hardware readying it for operation. 1489176667Sjfv **/ 1490267935Sjfvs32 e1000_init_hw_82575(struct e1000_hw *hw) 1491176667Sjfv{ 1492176667Sjfv struct e1000_mac_info *mac = &hw->mac; 1493176667Sjfv s32 ret_val; 1494176667Sjfv u16 i, rar_count = mac->rar_entry_count; 1495176667Sjfv 1496176667Sjfv DEBUGFUNC("e1000_init_hw_82575"); 1497176667Sjfv 1498176667Sjfv /* Initialize identification LED */ 1499190872Sjfv ret_val = mac->ops.id_led_init(hw); 1500176667Sjfv if (ret_val) { 1501176667Sjfv DEBUGOUT("Error initializing identification LED\n"); 1502176667Sjfv /* This is not fatal and we should not stop init due to this */ 1503176667Sjfv } 1504176667Sjfv 1505176667Sjfv /* Disabling VLAN filtering */ 1506176667Sjfv DEBUGOUT("Initializing the IEEE VLAN\n"); 1507176667Sjfv mac->ops.clear_vfta(hw); 1508176667Sjfv 1509176667Sjfv /* Setup the receive address */ 1510190872Sjfv e1000_init_rx_addrs_generic(hw, rar_count); 1511190872Sjfv 1512176667Sjfv /* Zero out the Multicast HASH table */ 1513176667Sjfv DEBUGOUT("Zeroing the MTA\n"); 1514176667Sjfv for (i = 0; i < mac->mta_reg_count; i++) 1515176667Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1516176667Sjfv 1517200243Sjfv /* Zero out the Unicast HASH table */ 1518200243Sjfv DEBUGOUT("Zeroing the UTA\n"); 1519200243Sjfv for (i = 0; i < mac->uta_reg_count; i++) 1520200243Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1521200243Sjfv 1522176667Sjfv /* Setup link and flow control */ 1523176667Sjfv ret_val = mac->ops.setup_link(hw); 1524176667Sjfv 1525228386Sjfv /* Set the default MTU size */ 1526228386Sjfv hw->dev_spec._82575.mtu = 1500; 1527228386Sjfv 1528176667Sjfv /* 1529176667Sjfv * Clear all of the statistics registers (clear on read). It is 1530176667Sjfv * important that we do this after we have tried to establish link 1531176667Sjfv * because the symbol error count will increment wildly if there 1532176667Sjfv * is no link. 1533176667Sjfv */ 1534176667Sjfv e1000_clear_hw_cntrs_82575(hw); 1535176667Sjfv 1536176667Sjfv return ret_val; 1537176667Sjfv} 1538176667Sjfv 1539176667Sjfv/** 1540176667Sjfv * e1000_setup_copper_link_82575 - Configure copper link settings 1541176667Sjfv * @hw: pointer to the HW structure 1542176667Sjfv * 1543176667Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1544176667Sjfv * for link, once link is established calls to configure collision distance 1545176667Sjfv * and flow control are called. 1546176667Sjfv **/ 1547176667Sjfvstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1548176667Sjfv{ 1549194865Sjfv u32 ctrl; 1550247064Sjfv s32 ret_val; 1551247064Sjfv u32 phpm_reg; 1552176667Sjfv 1553176667Sjfv DEBUGFUNC("e1000_setup_copper_link_82575"); 1554176667Sjfv 1555176667Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1556176667Sjfv ctrl |= E1000_CTRL_SLU; 1557176667Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1558176667Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1559176667Sjfv 1560256200Sjfv /* Clear Go Link Disconnect bit on supported devices */ 1561256200Sjfv switch (hw->mac.type) { 1562256200Sjfv case e1000_82580: 1563256200Sjfv case e1000_i350: 1564256200Sjfv case e1000_i210: 1565256200Sjfv case e1000_i211: 1566247064Sjfv phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 1567247064Sjfv phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1568247064Sjfv E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); 1569256200Sjfv break; 1570256200Sjfv default: 1571256200Sjfv break; 1572247064Sjfv } 1573247064Sjfv 1574200243Sjfv ret_val = e1000_setup_serdes_link_82575(hw); 1575200243Sjfv if (ret_val) 1576200243Sjfv goto out; 1577200243Sjfv 1578228386Sjfv if (e1000_sgmii_active_82575(hw)) { 1579200243Sjfv /* allow time for SFP cage time to power up phy */ 1580200243Sjfv msec_delay(300); 1581200243Sjfv 1582200243Sjfv ret_val = hw->phy.ops.reset(hw); 1583200243Sjfv if (ret_val) { 1584200243Sjfv DEBUGOUT("Error resetting the PHY.\n"); 1585200243Sjfv goto out; 1586200243Sjfv } 1587200243Sjfv } 1588176667Sjfv switch (hw->phy.type) { 1589238148Sjfv case e1000_phy_i210: 1590176667Sjfv case e1000_phy_m88: 1591247064Sjfv switch (hw->phy.id) { 1592247064Sjfv case I347AT4_E_PHY_ID: 1593247064Sjfv case M88E1112_E_PHY_ID: 1594247064Sjfv case M88E1340M_E_PHY_ID: 1595256200Sjfv case M88E1543_E_PHY_ID: 1596256200Sjfv case M88E1512_E_PHY_ID: 1597247064Sjfv case I210_I_PHY_ID: 1598218530Sjfv ret_val = e1000_copper_link_setup_m88_gen2(hw); 1599247064Sjfv break; 1600247064Sjfv default: 1601218530Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1602247064Sjfv break; 1603247064Sjfv } 1604176667Sjfv break; 1605176667Sjfv case e1000_phy_igp_3: 1606176667Sjfv ret_val = e1000_copper_link_setup_igp(hw); 1607176667Sjfv break; 1608200243Sjfv case e1000_phy_82580: 1609200243Sjfv ret_val = e1000_copper_link_setup_82577(hw); 1610200243Sjfv break; 1611176667Sjfv default: 1612176667Sjfv ret_val = -E1000_ERR_PHY; 1613176667Sjfv break; 1614176667Sjfv } 1615176667Sjfv 1616176667Sjfv if (ret_val) 1617176667Sjfv goto out; 1618176667Sjfv 1619200243Sjfv ret_val = e1000_setup_copper_link_generic(hw); 1620176667Sjfvout: 1621176667Sjfv return ret_val; 1622176667Sjfv} 1623176667Sjfv 1624176667Sjfv/** 1625200243Sjfv * e1000_setup_serdes_link_82575 - Setup link for serdes 1626176667Sjfv * @hw: pointer to the HW structure 1627176667Sjfv * 1628200243Sjfv * Configure the physical coding sub-layer (PCS) link. The PCS link is 1629200243Sjfv * used on copper connections where the serialized gigabit media independent 1630200243Sjfv * interface (sgmii), or serdes fiber is being used. Configures the link 1631200243Sjfv * for auto-negotiation or forces speed/duplex. 1632176667Sjfv **/ 1633200243Sjfvstatic s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1634176667Sjfv{ 1635247064Sjfv u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1636200243Sjfv bool pcs_autoneg; 1637228386Sjfv s32 ret_val = E1000_SUCCESS; 1638228386Sjfv u16 data; 1639176667Sjfv 1640200243Sjfv DEBUGFUNC("e1000_setup_serdes_link_82575"); 1641176667Sjfv 1642200243Sjfv if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1643200243Sjfv !e1000_sgmii_active_82575(hw)) 1644228386Sjfv return ret_val; 1645200243Sjfv 1646176667Sjfv /* 1647176667Sjfv * On the 82575, SerDes loopback mode persists until it is 1648176667Sjfv * explicitly turned off or a power cycle is performed. A read to 1649176667Sjfv * the register does not indicate its status. Therefore, we ensure 1650176667Sjfv * loopback mode is disabled during initialization. 1651176667Sjfv */ 1652176667Sjfv E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1653176667Sjfv 1654200243Sjfv /* power on the sfp cage if present */ 1655200243Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1656200243Sjfv ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1657200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1658200243Sjfv 1659200243Sjfv ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1660200243Sjfv ctrl_reg |= E1000_CTRL_SLU; 1661200243Sjfv 1662203049Sjfv /* set both sw defined pins on 82575/82576*/ 1663203049Sjfv if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1664200243Sjfv ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1665200243Sjfv 1666200243Sjfv reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1667200243Sjfv 1668200243Sjfv /* default pcs_autoneg to the same setting as mac autoneg */ 1669200243Sjfv pcs_autoneg = hw->mac.autoneg; 1670200243Sjfv 1671200243Sjfv switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1672200243Sjfv case E1000_CTRL_EXT_LINK_MODE_SGMII: 1673200243Sjfv /* sgmii mode lets the phy handle forcing speed/duplex */ 1674200243Sjfv pcs_autoneg = TRUE; 1675200243Sjfv /* autoneg time out should be disabled for SGMII mode */ 1676200243Sjfv reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1677200243Sjfv break; 1678200243Sjfv case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1679200243Sjfv /* disable PCS autoneg and support parallel detect only */ 1680200243Sjfv pcs_autoneg = FALSE; 1681333215Smarius /* FALLTHROUGH */ 1682200243Sjfv default: 1683228386Sjfv if (hw->mac.type == e1000_82575 || 1684228386Sjfv hw->mac.type == e1000_82576) { 1685228386Sjfv ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1686228386Sjfv if (ret_val) { 1687228386Sjfv DEBUGOUT("NVM Read Error\n"); 1688228386Sjfv return ret_val; 1689228386Sjfv } 1690228386Sjfv 1691228386Sjfv if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1692228386Sjfv pcs_autoneg = FALSE; 1693228386Sjfv } 1694228386Sjfv 1695200243Sjfv /* 1696200243Sjfv * non-SGMII modes only supports a speed of 1000/Full for the 1697200243Sjfv * link so it is best to just force the MAC and let the pcs 1698200243Sjfv * link either autoneg or be forced to 1000/Full 1699200243Sjfv */ 1700200243Sjfv ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1701228386Sjfv E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1702200243Sjfv 1703200243Sjfv /* set speed of 1000/Full if speed/duplex is forced */ 1704200243Sjfv reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1705200243Sjfv break; 1706181027Sjfv } 1707181027Sjfv 1708200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1709176667Sjfv 1710176667Sjfv /* 1711176667Sjfv * New SerDes mode allows for forcing speed or autonegotiating speed 1712176667Sjfv * at 1gb. Autoneg should be default set by most drivers. This is the 1713176667Sjfv * mode that will be compatible with older link partners and switches. 1714176667Sjfv * However, both are supported by the hardware and some drivers/tools. 1715176667Sjfv */ 1716176667Sjfv reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1717228386Sjfv E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1718176667Sjfv 1719200243Sjfv if (pcs_autoneg) { 1720176667Sjfv /* Set PCS register for autoneg */ 1721200243Sjfv reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1722200243Sjfv E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1723247064Sjfv 1724247064Sjfv /* Disable force flow control for autoneg */ 1725247064Sjfv reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1726247064Sjfv 1727247064Sjfv /* Configure flow control advertisement for autoneg */ 1728247064Sjfv anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1729247064Sjfv anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1730247064Sjfv 1731247064Sjfv switch (hw->fc.requested_mode) { 1732247064Sjfv case e1000_fc_full: 1733247064Sjfv case e1000_fc_rx_pause: 1734247064Sjfv anadv_reg |= E1000_TXCW_ASM_DIR; 1735247064Sjfv anadv_reg |= E1000_TXCW_PAUSE; 1736247064Sjfv break; 1737247064Sjfv case e1000_fc_tx_pause: 1738247064Sjfv anadv_reg |= E1000_TXCW_ASM_DIR; 1739247064Sjfv break; 1740247064Sjfv default: 1741247064Sjfv break; 1742247064Sjfv } 1743247064Sjfv 1744247064Sjfv E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg); 1745247064Sjfv 1746200243Sjfv DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1747176667Sjfv } else { 1748200243Sjfv /* Set PCS register for forced link */ 1749228386Sjfv reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1750247064Sjfv 1751247064Sjfv /* Force flow control for forced link */ 1752247064Sjfv reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1753247064Sjfv 1754200243Sjfv DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1755181027Sjfv } 1756181027Sjfv 1757176667Sjfv E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1758176667Sjfv 1759247064Sjfv if (!pcs_autoneg && !e1000_sgmii_active_82575(hw)) 1760200243Sjfv e1000_force_mac_fc_generic(hw); 1761200243Sjfv 1762228386Sjfv return ret_val; 1763176667Sjfv} 1764176667Sjfv 1765176667Sjfv/** 1766228386Sjfv * e1000_get_media_type_82575 - derives current media type. 1767228386Sjfv * @hw: pointer to the HW structure 1768228386Sjfv * 1769228386Sjfv * The media type is chosen reflecting few settings. 1770228386Sjfv * The following are taken into account: 1771228386Sjfv * - link mode set in the current port Init Control Word #3 1772228386Sjfv * - current link mode settings in CSR register 1773228386Sjfv * - MDIO vs. I2C PHY control interface chosen 1774228386Sjfv * - SFP module media type 1775228386Sjfv **/ 1776228386Sjfvstatic s32 e1000_get_media_type_82575(struct e1000_hw *hw) 1777228386Sjfv{ 1778228386Sjfv struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1779247064Sjfv s32 ret_val = E1000_SUCCESS; 1780228386Sjfv u32 ctrl_ext = 0; 1781247064Sjfv u32 link_mode = 0; 1782228386Sjfv 1783228386Sjfv /* Set internal phy as default */ 1784228386Sjfv dev_spec->sgmii_active = FALSE; 1785228386Sjfv dev_spec->module_plugged = FALSE; 1786228386Sjfv 1787228386Sjfv /* Get CSR setting */ 1788228386Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1789228386Sjfv 1790247064Sjfv /* extract link mode setting */ 1791247064Sjfv link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 1792228386Sjfv 1793247064Sjfv switch (link_mode) { 1794228386Sjfv case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1795228386Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 1796228386Sjfv break; 1797228386Sjfv case E1000_CTRL_EXT_LINK_MODE_GMII: 1798228386Sjfv hw->phy.media_type = e1000_media_type_copper; 1799228386Sjfv break; 1800228386Sjfv case E1000_CTRL_EXT_LINK_MODE_SGMII: 1801228386Sjfv /* Get phy control interface type set (MDIO vs. I2C)*/ 1802228386Sjfv if (e1000_sgmii_uses_mdio_82575(hw)) { 1803228386Sjfv hw->phy.media_type = e1000_media_type_copper; 1804228386Sjfv dev_spec->sgmii_active = TRUE; 1805247064Sjfv break; 1806247064Sjfv } 1807247064Sjfv /* fall through for I2C based SGMII */ 1808333215Smarius /* FALLTHROUGH */ 1809247064Sjfv case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1810247064Sjfv /* read media type from SFP EEPROM */ 1811247064Sjfv ret_val = e1000_set_sfp_media_type_82575(hw); 1812247064Sjfv if ((ret_val != E1000_SUCCESS) || 1813247064Sjfv (hw->phy.media_type == e1000_media_type_unknown)) { 1814247064Sjfv /* 1815247064Sjfv * If media type was not identified then return media 1816247064Sjfv * type defined by the CTRL_EXT settings. 1817247064Sjfv */ 1818247064Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 1819247064Sjfv 1820247064Sjfv if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 1821247064Sjfv hw->phy.media_type = e1000_media_type_copper; 1822247064Sjfv dev_spec->sgmii_active = TRUE; 1823228386Sjfv } 1824247064Sjfv 1825247064Sjfv break; 1826228386Sjfv } 1827247064Sjfv 1828247064Sjfv /* do not change link mode for 100BaseFX */ 1829247064Sjfv if (dev_spec->eth_flags.e100_base_fx) 1830247064Sjfv break; 1831247064Sjfv 1832247064Sjfv /* change current link mode setting */ 1833228386Sjfv ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1834228386Sjfv 1835247064Sjfv if (hw->phy.media_type == e1000_media_type_copper) 1836247064Sjfv ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 1837228386Sjfv else 1838247064Sjfv ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1839247064Sjfv 1840247064Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1841247064Sjfv 1842247064Sjfv break; 1843228386Sjfv } 1844228386Sjfv 1845228386Sjfv return ret_val; 1846228386Sjfv} 1847228386Sjfv 1848228386Sjfv/** 1849228386Sjfv * e1000_set_sfp_media_type_82575 - derives SFP module media type. 1850228386Sjfv * @hw: pointer to the HW structure 1851228386Sjfv * 1852228386Sjfv * The media type is chosen based on SFP module. 1853228386Sjfv * compatibility flags retrieved from SFP ID EEPROM. 1854228386Sjfv **/ 1855228386Sjfvstatic s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw) 1856228386Sjfv{ 1857228386Sjfv s32 ret_val = E1000_ERR_CONFIG; 1858228386Sjfv u32 ctrl_ext = 0; 1859228386Sjfv struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1860247064Sjfv struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags; 1861228386Sjfv u8 tranceiver_type = 0; 1862247064Sjfv s32 timeout = 3; 1863228386Sjfv 1864247064Sjfv /* Turn I2C interface ON and power on sfp cage */ 1865228386Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1866247064Sjfv ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1867228386Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 1868228386Sjfv 1869247064Sjfv E1000_WRITE_FLUSH(hw); 1870247064Sjfv 1871228386Sjfv /* Read SFP module data */ 1872247064Sjfv while (timeout) { 1873247064Sjfv ret_val = e1000_read_sfp_data_byte(hw, 1874228386Sjfv E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 1875228386Sjfv &tranceiver_type); 1876247064Sjfv if (ret_val == E1000_SUCCESS) 1877247064Sjfv break; 1878247064Sjfv msec_delay(100); 1879247064Sjfv timeout--; 1880247064Sjfv } 1881228386Sjfv if (ret_val != E1000_SUCCESS) 1882228386Sjfv goto out; 1883247064Sjfv 1884228386Sjfv ret_val = e1000_read_sfp_data_byte(hw, 1885228386Sjfv E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 1886247064Sjfv (u8 *)eth_flags); 1887228386Sjfv if (ret_val != E1000_SUCCESS) 1888228386Sjfv goto out; 1889247064Sjfv 1890247064Sjfv /* Check if there is some SFP module plugged and powered */ 1891228386Sjfv if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 1892228386Sjfv (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 1893228386Sjfv dev_spec->module_plugged = TRUE; 1894247064Sjfv if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 1895228386Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 1896247064Sjfv } else if (eth_flags->e100_base_fx) { 1897228386Sjfv dev_spec->sgmii_active = TRUE; 1898247064Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 1899247064Sjfv } else if (eth_flags->e1000_base_t) { 1900247064Sjfv dev_spec->sgmii_active = TRUE; 1901228386Sjfv hw->phy.media_type = e1000_media_type_copper; 1902228386Sjfv } else { 1903247064Sjfv hw->phy.media_type = e1000_media_type_unknown; 1904247064Sjfv DEBUGOUT("PHY module has not been recognized\n"); 1905247064Sjfv goto out; 1906228386Sjfv } 1907228386Sjfv } else { 1908228386Sjfv hw->phy.media_type = e1000_media_type_unknown; 1909228386Sjfv } 1910228386Sjfv ret_val = E1000_SUCCESS; 1911228386Sjfvout: 1912228386Sjfv /* Restore I2C interface setting */ 1913228386Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1914228386Sjfv return ret_val; 1915228386Sjfv} 1916228386Sjfv 1917228386Sjfv/** 1918181027Sjfv * e1000_valid_led_default_82575 - Verify a valid default LED config 1919181027Sjfv * @hw: pointer to the HW structure 1920181027Sjfv * @data: pointer to the NVM (EEPROM) 1921181027Sjfv * 1922181027Sjfv * Read the EEPROM for the current default LED configuration. If the 1923181027Sjfv * LED configuration is not valid, set to a valid LED configuration. 1924181027Sjfv **/ 1925181027Sjfvstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1926181027Sjfv{ 1927181027Sjfv s32 ret_val; 1928181027Sjfv 1929181027Sjfv DEBUGFUNC("e1000_valid_led_default_82575"); 1930181027Sjfv 1931181027Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1932181027Sjfv if (ret_val) { 1933181027Sjfv DEBUGOUT("NVM Read Error\n"); 1934181027Sjfv goto out; 1935181027Sjfv } 1936181027Sjfv 1937181027Sjfv if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1938228386Sjfv switch (hw->phy.media_type) { 1939181027Sjfv case e1000_media_type_internal_serdes: 1940181027Sjfv *data = ID_LED_DEFAULT_82575_SERDES; 1941181027Sjfv break; 1942181027Sjfv case e1000_media_type_copper: 1943181027Sjfv default: 1944181027Sjfv *data = ID_LED_DEFAULT; 1945181027Sjfv break; 1946181027Sjfv } 1947181027Sjfv } 1948181027Sjfvout: 1949181027Sjfv return ret_val; 1950181027Sjfv} 1951181027Sjfv 1952181027Sjfv/** 1953176667Sjfv * e1000_sgmii_active_82575 - Return sgmii state 1954176667Sjfv * @hw: pointer to the HW structure 1955176667Sjfv * 1956176667Sjfv * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1957176667Sjfv * which can be enabled for use in the embedded applications. Simply 1958176667Sjfv * return the current state of the sgmii interface. 1959176667Sjfv **/ 1960176667Sjfvstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1961176667Sjfv{ 1962185353Sjfv struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1963185353Sjfv return dev_spec->sgmii_active; 1964176667Sjfv} 1965176667Sjfv 1966176667Sjfv/** 1967176667Sjfv * e1000_reset_init_script_82575 - Inits HW defaults after reset 1968176667Sjfv * @hw: pointer to the HW structure 1969176667Sjfv * 1970176667Sjfv * Inits recommended HW defaults after a reset when there is no EEPROM 1971176667Sjfv * detected. This is only for the 82575. 1972176667Sjfv **/ 1973228386Sjfvstatic s32 e1000_reset_init_script_82575(struct e1000_hw *hw) 1974176667Sjfv{ 1975176667Sjfv DEBUGFUNC("e1000_reset_init_script_82575"); 1976176667Sjfv 1977176667Sjfv if (hw->mac.type == e1000_82575) { 1978176667Sjfv DEBUGOUT("Running reset init script for 82575\n"); 1979176667Sjfv /* SerDes configuration via SERDESCTRL */ 1980178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1981178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1982178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1983178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1984176667Sjfv 1985176667Sjfv /* CCM configuration via CCMCTL register */ 1986178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1987178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1988176667Sjfv 1989176667Sjfv /* PCIe lanes configuration */ 1990178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1991178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1992178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1993178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1994176667Sjfv 1995176667Sjfv /* PCIe PLL Configuration */ 1996178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1997178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1998178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1999176667Sjfv } 2000176667Sjfv 2001176667Sjfv return E1000_SUCCESS; 2002176667Sjfv} 2003176667Sjfv 2004176667Sjfv/** 2005176667Sjfv * e1000_read_mac_addr_82575 - Read device MAC address 2006176667Sjfv * @hw: pointer to the HW structure 2007176667Sjfv **/ 2008176667Sjfvstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 2009176667Sjfv{ 2010267935Sjfv s32 ret_val; 2011176667Sjfv 2012176667Sjfv DEBUGFUNC("e1000_read_mac_addr_82575"); 2013176667Sjfv 2014190872Sjfv /* 2015190872Sjfv * If there's an alternate MAC address place it in RAR0 2016190872Sjfv * so that it will override the Si installed default perm 2017190872Sjfv * address. 2018190872Sjfv */ 2019190872Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 2020190872Sjfv if (ret_val) 2021190872Sjfv goto out; 2022190872Sjfv 2023190872Sjfv ret_val = e1000_read_mac_addr_generic(hw); 2024190872Sjfv 2025190872Sjfvout: 2026176667Sjfv return ret_val; 2027176667Sjfv} 2028176667Sjfv 2029176667Sjfv/** 2030203049Sjfv * e1000_config_collision_dist_82575 - Configure collision distance 2031203049Sjfv * @hw: pointer to the HW structure 2032203049Sjfv * 2033203049Sjfv * Configures the collision distance to the default value and is used 2034203049Sjfv * during link setup. 2035203049Sjfv **/ 2036203049Sjfvstatic void e1000_config_collision_dist_82575(struct e1000_hw *hw) 2037203049Sjfv{ 2038203049Sjfv u32 tctl_ext; 2039203049Sjfv 2040203049Sjfv DEBUGFUNC("e1000_config_collision_dist_82575"); 2041203049Sjfv 2042203049Sjfv tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 2043203049Sjfv 2044203049Sjfv tctl_ext &= ~E1000_TCTL_EXT_COLD; 2045203049Sjfv tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 2046203049Sjfv 2047203049Sjfv E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 2048203049Sjfv E1000_WRITE_FLUSH(hw); 2049203049Sjfv} 2050203049Sjfv 2051203049Sjfv/** 2052176667Sjfv * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 2053176667Sjfv * @hw: pointer to the HW structure 2054176667Sjfv * 2055176667Sjfv * In the case of a PHY power down to save power, or to turn off link during a 2056176667Sjfv * driver unload, or wake on lan is not enabled, remove the link. 2057176667Sjfv **/ 2058176667Sjfvstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 2059176667Sjfv{ 2060176667Sjfv struct e1000_phy_info *phy = &hw->phy; 2061176667Sjfv 2062176667Sjfv if (!(phy->ops.check_reset_block)) 2063176667Sjfv return; 2064176667Sjfv 2065176667Sjfv /* If the management interface is not enabled, then power down */ 2066205869Sjfv if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) 2067176667Sjfv e1000_power_down_phy_copper(hw); 2068176667Sjfv 2069176667Sjfv return; 2070176667Sjfv} 2071176667Sjfv 2072176667Sjfv/** 2073176667Sjfv * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 2074176667Sjfv * @hw: pointer to the HW structure 2075176667Sjfv * 2076176667Sjfv * Clears the hardware counters by reading the counter registers. 2077176667Sjfv **/ 2078176667Sjfvstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 2079176667Sjfv{ 2080176667Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 2081176667Sjfv 2082176667Sjfv e1000_clear_hw_cntrs_base_generic(hw); 2083176667Sjfv 2084185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 2085185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 2086185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 2087185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 2088185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 2089185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 2090185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 2091185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 2092185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 2093185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 2094185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 2095185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 2096176667Sjfv 2097185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 2098185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 2099185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 2100185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 2101185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 2102185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 2103176667Sjfv 2104185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 2105185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 2106185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 2107176667Sjfv 2108185353Sjfv E1000_READ_REG(hw, E1000_IAC); 2109185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 2110176667Sjfv 2111185353Sjfv E1000_READ_REG(hw, E1000_ICRXPTC); 2112185353Sjfv E1000_READ_REG(hw, E1000_ICRXATC); 2113185353Sjfv E1000_READ_REG(hw, E1000_ICTXPTC); 2114185353Sjfv E1000_READ_REG(hw, E1000_ICTXATC); 2115185353Sjfv E1000_READ_REG(hw, E1000_ICTXQEC); 2116185353Sjfv E1000_READ_REG(hw, E1000_ICTXQMTC); 2117185353Sjfv E1000_READ_REG(hw, E1000_ICRXDMTC); 2118176667Sjfv 2119185353Sjfv E1000_READ_REG(hw, E1000_CBTMPC); 2120185353Sjfv E1000_READ_REG(hw, E1000_HTDPMC); 2121185353Sjfv E1000_READ_REG(hw, E1000_CBRMPC); 2122185353Sjfv E1000_READ_REG(hw, E1000_RPTHC); 2123185353Sjfv E1000_READ_REG(hw, E1000_HGPTC); 2124185353Sjfv E1000_READ_REG(hw, E1000_HTCBDPC); 2125185353Sjfv E1000_READ_REG(hw, E1000_HGORCL); 2126185353Sjfv E1000_READ_REG(hw, E1000_HGORCH); 2127185353Sjfv E1000_READ_REG(hw, E1000_HGOTCL); 2128185353Sjfv E1000_READ_REG(hw, E1000_HGOTCH); 2129185353Sjfv E1000_READ_REG(hw, E1000_LENERRS); 2130176667Sjfv 2131176667Sjfv /* This register should not be read in copper configurations */ 2132200243Sjfv if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 2133200243Sjfv e1000_sgmii_active_82575(hw)) 2134185353Sjfv E1000_READ_REG(hw, E1000_SCVPC); 2135176667Sjfv} 2136194865Sjfv 2137181027Sjfv/** 2138218530Sjfv * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable 2139181027Sjfv * @hw: pointer to the HW structure 2140181027Sjfv * 2141287112Ssbruno * After Rx enable, if manageability is enabled then there is likely some 2142181027Sjfv * bad data at the start of the fifo and possibly in the DMA fifo. This 2143181027Sjfv * function clears the fifos and flushes any packets that came in as rx was 2144181027Sjfv * being enabled. 2145181027Sjfv **/ 2146181027Sjfvvoid e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 2147181027Sjfv{ 2148181027Sjfv u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 2149181027Sjfv int i, ms_wait; 2150181027Sjfv 2151295323Serj DEBUGFUNC("e1000_rx_fifo_flush_82575"); 2152295323Serj 2153295323Serj /* disable IPv6 options as per hardware errata */ 2154295323Serj rfctl = E1000_READ_REG(hw, E1000_RFCTL); 2155295323Serj rfctl |= E1000_RFCTL_IPV6_EX_DIS; 2156295323Serj E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2157295323Serj 2158181027Sjfv if (hw->mac.type != e1000_82575 || 2159181027Sjfv !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 2160181027Sjfv return; 2161181027Sjfv 2162218530Sjfv /* Disable all Rx queues */ 2163181027Sjfv for (i = 0; i < 4; i++) { 2164181027Sjfv rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 2165181027Sjfv E1000_WRITE_REG(hw, E1000_RXDCTL(i), 2166228386Sjfv rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 2167181027Sjfv } 2168181027Sjfv /* Poll all queues to verify they have shut down */ 2169181027Sjfv for (ms_wait = 0; ms_wait < 10; ms_wait++) { 2170181027Sjfv msec_delay(1); 2171181027Sjfv rx_enabled = 0; 2172181027Sjfv for (i = 0; i < 4; i++) 2173181027Sjfv rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 2174181027Sjfv if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 2175181027Sjfv break; 2176181027Sjfv } 2177181027Sjfv 2178181027Sjfv if (ms_wait == 10) 2179181027Sjfv DEBUGOUT("Queue disable timed out after 10ms\n"); 2180181027Sjfv 2181181027Sjfv /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 2182181027Sjfv * incoming packets are rejected. Set enable and wait 2ms so that 2183181027Sjfv * any packet that was coming in as RCTL.EN was set is flushed 2184181027Sjfv */ 2185181027Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 2186181027Sjfv 2187181027Sjfv rlpml = E1000_READ_REG(hw, E1000_RLPML); 2188181027Sjfv E1000_WRITE_REG(hw, E1000_RLPML, 0); 2189181027Sjfv 2190181027Sjfv rctl = E1000_READ_REG(hw, E1000_RCTL); 2191181027Sjfv temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 2192181027Sjfv temp_rctl |= E1000_RCTL_LPE; 2193181027Sjfv 2194181027Sjfv E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 2195181027Sjfv E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 2196181027Sjfv E1000_WRITE_FLUSH(hw); 2197181027Sjfv msec_delay(2); 2198181027Sjfv 2199218530Sjfv /* Enable Rx queues that were previously enabled and restore our 2200181027Sjfv * previous state 2201181027Sjfv */ 2202181027Sjfv for (i = 0; i < 4; i++) 2203181027Sjfv E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 2204181027Sjfv E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2205181027Sjfv E1000_WRITE_FLUSH(hw); 2206181027Sjfv 2207181027Sjfv E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 2208181027Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2209181027Sjfv 2210181027Sjfv /* Flush receive errors generated by workaround */ 2211181027Sjfv E1000_READ_REG(hw, E1000_ROC); 2212181027Sjfv E1000_READ_REG(hw, E1000_RNBC); 2213181027Sjfv E1000_READ_REG(hw, E1000_MPC); 2214181027Sjfv} 2215185353Sjfv 2216194865Sjfv/** 2217194865Sjfv * e1000_set_pcie_completion_timeout - set pci-e completion timeout 2218194865Sjfv * @hw: pointer to the HW structure 2219194865Sjfv * 2220194865Sjfv * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 2221194865Sjfv * however the hardware default for these parts is 500us to 1ms which is less 2222194865Sjfv * than the 10ms recommended by the pci-e spec. To address this we need to 2223194865Sjfv * increase the value to either 10ms to 200ms for capability version 1 config, 2224194865Sjfv * or 16ms to 55ms for version 2. 2225194865Sjfv **/ 2226194865Sjfvstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 2227194865Sjfv{ 2228194865Sjfv u32 gcr = E1000_READ_REG(hw, E1000_GCR); 2229194865Sjfv s32 ret_val = E1000_SUCCESS; 2230194865Sjfv u16 pcie_devctl2; 2231194865Sjfv 2232194865Sjfv /* only take action if timeout value is defaulted to 0 */ 2233194865Sjfv if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2234194865Sjfv goto out; 2235194865Sjfv 2236194865Sjfv /* 2237194865Sjfv * if capababilities version is type 1 we can write the 2238194865Sjfv * timeout of 10ms to 200ms through the GCR register 2239194865Sjfv */ 2240194865Sjfv if (!(gcr & E1000_GCR_CAP_VER2)) { 2241194865Sjfv gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2242194865Sjfv goto out; 2243194865Sjfv } 2244194865Sjfv 2245194865Sjfv /* 2246194865Sjfv * for version 2 capabilities we need to write the config space 2247194865Sjfv * directly in order to set the completion timeout value for 2248194865Sjfv * 16ms to 55ms 2249194865Sjfv */ 2250194865Sjfv ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2251228386Sjfv &pcie_devctl2); 2252194865Sjfv if (ret_val) 2253194865Sjfv goto out; 2254194865Sjfv 2255194865Sjfv pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2256194865Sjfv 2257194865Sjfv ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2258228386Sjfv &pcie_devctl2); 2259194865Sjfvout: 2260194865Sjfv /* disable completion timeout resend */ 2261194865Sjfv gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2262194865Sjfv 2263194865Sjfv E1000_WRITE_REG(hw, E1000_GCR, gcr); 2264194865Sjfv return ret_val; 2265194865Sjfv} 2266194865Sjfv 2267200243Sjfv/** 2268213234Sjfv * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2269213234Sjfv * @hw: pointer to the hardware struct 2270213234Sjfv * @enable: state to enter, either enabled or disabled 2271213234Sjfv * @pf: Physical Function pool - do not set anti-spoofing for the PF 2272213234Sjfv * 2273213234Sjfv * enables/disables L2 switch anti-spoofing functionality. 2274213234Sjfv **/ 2275213234Sjfvvoid e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2276213234Sjfv{ 2277256200Sjfv u32 reg_val, reg_offset; 2278213234Sjfv 2279213234Sjfv switch (hw->mac.type) { 2280213234Sjfv case e1000_82576: 2281256200Sjfv reg_offset = E1000_DTXSWC; 2282213234Sjfv break; 2283228386Sjfv case e1000_i350: 2284256200Sjfv case e1000_i354: 2285256200Sjfv reg_offset = E1000_TXSWC; 2286256200Sjfv break; 2287213234Sjfv default: 2288256200Sjfv return; 2289213234Sjfv } 2290256200Sjfv 2291256200Sjfv reg_val = E1000_READ_REG(hw, reg_offset); 2292256200Sjfv if (enable) { 2293256200Sjfv reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2294256200Sjfv E1000_DTXSWC_VLAN_SPOOF_MASK); 2295256200Sjfv /* The PF can spoof - it has to in order to 2296256200Sjfv * support emulation mode NICs 2297256200Sjfv */ 2298256200Sjfv reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 2299256200Sjfv } else { 2300256200Sjfv reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2301256200Sjfv E1000_DTXSWC_VLAN_SPOOF_MASK); 2302256200Sjfv } 2303256200Sjfv E1000_WRITE_REG(hw, reg_offset, reg_val); 2304213234Sjfv} 2305213234Sjfv 2306213234Sjfv/** 2307200243Sjfv * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 2308200243Sjfv * @hw: pointer to the hardware struct 2309200243Sjfv * @enable: state to enter, either enabled or disabled 2310200243Sjfv * 2311200243Sjfv * enables/disables L2 switch loopback functionality. 2312200243Sjfv **/ 2313200243Sjfvvoid e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2314200243Sjfv{ 2315205869Sjfv u32 dtxswc; 2316200243Sjfv 2317205869Sjfv switch (hw->mac.type) { 2318205869Sjfv case e1000_82576: 2319205869Sjfv dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 2320205869Sjfv if (enable) 2321205869Sjfv dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2322205869Sjfv else 2323205869Sjfv dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2324205869Sjfv E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 2325205869Sjfv break; 2326218530Sjfv case e1000_i350: 2327256200Sjfv case e1000_i354: 2328218530Sjfv dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 2329218530Sjfv if (enable) 2330218530Sjfv dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2331218530Sjfv else 2332218530Sjfv dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2333218530Sjfv E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 2334218530Sjfv break; 2335205869Sjfv default: 2336205869Sjfv /* Currently no other hardware supports loopback */ 2337205869Sjfv break; 2338205869Sjfv } 2339200243Sjfv 2340205869Sjfv 2341200243Sjfv} 2342200243Sjfv 2343200243Sjfv/** 2344200243Sjfv * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 2345200243Sjfv * @hw: pointer to the hardware struct 2346200243Sjfv * @enable: state to enter, either enabled or disabled 2347200243Sjfv * 2348200243Sjfv * enables/disables replication of packets across multiple pools. 2349200243Sjfv **/ 2350200243Sjfvvoid e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2351200243Sjfv{ 2352200243Sjfv u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 2353200243Sjfv 2354200243Sjfv if (enable) 2355200243Sjfv vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2356200243Sjfv else 2357200243Sjfv vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2358200243Sjfv 2359200243Sjfv E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 2360200243Sjfv} 2361200243Sjfv 2362200243Sjfv/** 2363200243Sjfv * e1000_read_phy_reg_82580 - Read 82580 MDI control register 2364200243Sjfv * @hw: pointer to the HW structure 2365200243Sjfv * @offset: register offset to be read 2366200243Sjfv * @data: pointer to the read data 2367200243Sjfv * 2368200243Sjfv * Reads the MDI control register in the PHY at offset and stores the 2369200243Sjfv * information read to data. 2370200243Sjfv **/ 2371200243Sjfvstatic s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2372200243Sjfv{ 2373200243Sjfv s32 ret_val; 2374200243Sjfv 2375200243Sjfv DEBUGFUNC("e1000_read_phy_reg_82580"); 2376200243Sjfv 2377200243Sjfv ret_val = hw->phy.ops.acquire(hw); 2378200243Sjfv if (ret_val) 2379200243Sjfv goto out; 2380200243Sjfv 2381200243Sjfv ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 2382200243Sjfv 2383200243Sjfv hw->phy.ops.release(hw); 2384200243Sjfv 2385200243Sjfvout: 2386200243Sjfv return ret_val; 2387200243Sjfv} 2388200243Sjfv 2389200243Sjfv/** 2390200243Sjfv * e1000_write_phy_reg_82580 - Write 82580 MDI control register 2391200243Sjfv * @hw: pointer to the HW structure 2392200243Sjfv * @offset: register offset to write to 2393200243Sjfv * @data: data to write to register at offset 2394200243Sjfv * 2395200243Sjfv * Writes data to MDI control register in the PHY at offset. 2396200243Sjfv **/ 2397200243Sjfvstatic s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2398200243Sjfv{ 2399200243Sjfv s32 ret_val; 2400200243Sjfv 2401200243Sjfv DEBUGFUNC("e1000_write_phy_reg_82580"); 2402200243Sjfv 2403200243Sjfv ret_val = hw->phy.ops.acquire(hw); 2404200243Sjfv if (ret_val) 2405200243Sjfv goto out; 2406200243Sjfv 2407200243Sjfv ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 2408200243Sjfv 2409200243Sjfv hw->phy.ops.release(hw); 2410200243Sjfv 2411200243Sjfvout: 2412200243Sjfv return ret_val; 2413200243Sjfv} 2414203049Sjfv 2415200243Sjfv/** 2416213234Sjfv * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2417213234Sjfv * @hw: pointer to the HW structure 2418213234Sjfv * 2419300050Seadler * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2420213234Sjfv * the values found in the EEPROM. This addresses an issue in which these 2421213234Sjfv * bits are not restored from EEPROM after reset. 2422213234Sjfv **/ 2423213234Sjfvstatic s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) 2424213234Sjfv{ 2425213234Sjfv s32 ret_val = E1000_SUCCESS; 2426213234Sjfv u32 mdicnfg; 2427218530Sjfv u16 nvm_data = 0; 2428213234Sjfv 2429213234Sjfv DEBUGFUNC("e1000_reset_mdicnfg_82580"); 2430213234Sjfv 2431213234Sjfv if (hw->mac.type != e1000_82580) 2432213234Sjfv goto out; 2433213234Sjfv if (!e1000_sgmii_active_82575(hw)) 2434213234Sjfv goto out; 2435213234Sjfv 2436213234Sjfv ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2437228386Sjfv NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2438228386Sjfv &nvm_data); 2439213234Sjfv if (ret_val) { 2440213234Sjfv DEBUGOUT("NVM Read Error\n"); 2441213234Sjfv goto out; 2442213234Sjfv } 2443213234Sjfv 2444213234Sjfv mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); 2445213234Sjfv if (nvm_data & NVM_WORD24_EXT_MDIO) 2446213234Sjfv mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2447213234Sjfv if (nvm_data & NVM_WORD24_COM_MDIO) 2448213234Sjfv mdicnfg |= E1000_MDICNFG_COM_MDIO; 2449213234Sjfv E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 2450213234Sjfvout: 2451213234Sjfv return ret_val; 2452213234Sjfv} 2453213234Sjfv 2454213234Sjfv/** 2455200243Sjfv * e1000_reset_hw_82580 - Reset hardware 2456200243Sjfv * @hw: pointer to the HW structure 2457200243Sjfv * 2458200243Sjfv * This resets function or entire device (all ports, etc.) 2459200243Sjfv * to a known state. 2460200243Sjfv **/ 2461200243Sjfvstatic s32 e1000_reset_hw_82580(struct e1000_hw *hw) 2462200243Sjfv{ 2463200243Sjfv s32 ret_val = E1000_SUCCESS; 2464200243Sjfv /* BH SW mailbox bit in SW_FW_SYNC */ 2465200243Sjfv u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2466218530Sjfv u32 ctrl; 2467200243Sjfv bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2468200243Sjfv 2469200243Sjfv DEBUGFUNC("e1000_reset_hw_82580"); 2470200243Sjfv 2471200243Sjfv hw->dev_spec._82575.global_device_reset = FALSE; 2472200243Sjfv 2473247064Sjfv /* 82580 does not reliably do global_device_reset due to hw errata */ 2474247064Sjfv if (hw->mac.type == e1000_82580) 2475247064Sjfv global_device_reset = FALSE; 2476247064Sjfv 2477200243Sjfv /* Get current control state. */ 2478200243Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2479200243Sjfv 2480200243Sjfv /* 2481200243Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 2482200243Sjfv * on the last TLP read/write transaction when MAC is reset. 2483200243Sjfv */ 2484200243Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 2485200243Sjfv if (ret_val) 2486200243Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2487200243Sjfv 2488200243Sjfv DEBUGOUT("Masking off all interrupts\n"); 2489200243Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2490200243Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 2491200243Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2492200243Sjfv E1000_WRITE_FLUSH(hw); 2493200243Sjfv 2494200243Sjfv msec_delay(10); 2495200243Sjfv 2496200243Sjfv /* Determine whether or not a global dev reset is requested */ 2497238148Sjfv if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw, 2498228386Sjfv swmbsw_mask)) 2499200243Sjfv global_device_reset = FALSE; 2500200243Sjfv 2501228386Sjfv if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) & 2502228386Sjfv E1000_STAT_DEV_RST_SET)) 2503200243Sjfv ctrl |= E1000_CTRL_DEV_RST; 2504200243Sjfv else 2505200243Sjfv ctrl |= E1000_CTRL_RST; 2506200243Sjfv 2507200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2508200243Sjfv 2509267935Sjfv switch (hw->device_id) { 2510267935Sjfv case E1000_DEV_ID_DH89XXCC_SGMII: 2511267935Sjfv break; 2512267935Sjfv default: 2513267935Sjfv E1000_WRITE_FLUSH(hw); 2514267935Sjfv break; 2515267935Sjfv } 2516200243Sjfv 2517267935Sjfv /* Add delay to insure DEV_RST or RST has time to complete */ 2518267935Sjfv msec_delay(5); 2519267935Sjfv 2520200243Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 2521200243Sjfv if (ret_val) { 2522200243Sjfv /* 2523200243Sjfv * When auto config read does not complete, do not 2524200243Sjfv * return with an error. This can happen in situations 2525200243Sjfv * where there is no eeprom and prevents getting link. 2526200243Sjfv */ 2527200243Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 2528200243Sjfv } 2529200243Sjfv 2530200243Sjfv /* clear global device reset status bit */ 2531200243Sjfv E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 2532200243Sjfv 2533200243Sjfv /* Clear any pending interrupt events. */ 2534200243Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2535218530Sjfv E1000_READ_REG(hw, E1000_ICR); 2536200243Sjfv 2537213234Sjfv ret_val = e1000_reset_mdicnfg_82580(hw); 2538213234Sjfv if (ret_val) 2539213234Sjfv DEBUGOUT("Could not reset MDICNFG based on EEPROM\n"); 2540213234Sjfv 2541200243Sjfv /* Install any alternate MAC address into RAR0 */ 2542200243Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 2543200243Sjfv 2544200243Sjfv /* Release semaphore */ 2545200243Sjfv if (global_device_reset) 2546238148Sjfv hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2547200243Sjfv 2548200243Sjfv return ret_val; 2549200243Sjfv} 2550200243Sjfv 2551200243Sjfv/** 2552218530Sjfv * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size 2553200243Sjfv * @data: data received by reading RXPBS register 2554200243Sjfv * 2555200243Sjfv * The 82580 uses a table based approach for packet buffer allocation sizes. 2556200243Sjfv * This function converts the retrieved value into the correct table value 2557200243Sjfv * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2558200243Sjfv * 0x0 36 72 144 1 2 4 8 16 2559200243Sjfv * 0x8 35 70 140 rsv rsv rsv rsv rsv 2560200243Sjfv */ 2561200243Sjfvu16 e1000_rxpbs_adjust_82580(u32 data) 2562200243Sjfv{ 2563200243Sjfv u16 ret_val = 0; 2564200243Sjfv 2565200243Sjfv if (data < E1000_82580_RXPBS_TABLE_SIZE) 2566200243Sjfv ret_val = e1000_82580_rxpbs_table[data]; 2567200243Sjfv 2568200243Sjfv return ret_val; 2569200243Sjfv} 2570218530Sjfv 2571218530Sjfv/** 2572218530Sjfv * e1000_validate_nvm_checksum_with_offset - Validate EEPROM 2573218530Sjfv * checksum 2574218530Sjfv * @hw: pointer to the HW structure 2575218530Sjfv * @offset: offset in words of the checksum protected region 2576218530Sjfv * 2577218530Sjfv * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2578218530Sjfv * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2579218530Sjfv **/ 2580218530Sjfvs32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2581218530Sjfv{ 2582218530Sjfv s32 ret_val = E1000_SUCCESS; 2583218530Sjfv u16 checksum = 0; 2584218530Sjfv u16 i, nvm_data; 2585218530Sjfv 2586218530Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_with_offset"); 2587218530Sjfv 2588218530Sjfv for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2589218530Sjfv ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2590218530Sjfv if (ret_val) { 2591218530Sjfv DEBUGOUT("NVM Read Error\n"); 2592218530Sjfv goto out; 2593218530Sjfv } 2594218530Sjfv checksum += nvm_data; 2595218530Sjfv } 2596218530Sjfv 2597218530Sjfv if (checksum != (u16) NVM_SUM) { 2598218530Sjfv DEBUGOUT("NVM Checksum Invalid\n"); 2599218530Sjfv ret_val = -E1000_ERR_NVM; 2600218530Sjfv goto out; 2601218530Sjfv } 2602218530Sjfv 2603218530Sjfvout: 2604218530Sjfv return ret_val; 2605218530Sjfv} 2606218530Sjfv 2607218530Sjfv/** 2608218530Sjfv * e1000_update_nvm_checksum_with_offset - Update EEPROM 2609218530Sjfv * checksum 2610218530Sjfv * @hw: pointer to the HW structure 2611218530Sjfv * @offset: offset in words of the checksum protected region 2612218530Sjfv * 2613218530Sjfv * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2614218530Sjfv * up to the checksum. Then calculates the EEPROM checksum and writes the 2615218530Sjfv * value to the EEPROM. 2616218530Sjfv **/ 2617218530Sjfvs32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2618218530Sjfv{ 2619218530Sjfv s32 ret_val; 2620218530Sjfv u16 checksum = 0; 2621218530Sjfv u16 i, nvm_data; 2622218530Sjfv 2623218530Sjfv DEBUGFUNC("e1000_update_nvm_checksum_with_offset"); 2624218530Sjfv 2625218530Sjfv for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2626218530Sjfv ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2627218530Sjfv if (ret_val) { 2628218530Sjfv DEBUGOUT("NVM Read Error while updating checksum.\n"); 2629218530Sjfv goto out; 2630218530Sjfv } 2631218530Sjfv checksum += nvm_data; 2632218530Sjfv } 2633218530Sjfv checksum = (u16) NVM_SUM - checksum; 2634218530Sjfv ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2635228386Sjfv &checksum); 2636218530Sjfv if (ret_val) 2637218530Sjfv DEBUGOUT("NVM Write Error while updating checksum.\n"); 2638218530Sjfv 2639218530Sjfvout: 2640218530Sjfv return ret_val; 2641218530Sjfv} 2642218530Sjfv 2643218530Sjfv/** 2644218530Sjfv * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum 2645218530Sjfv * @hw: pointer to the HW structure 2646218530Sjfv * 2647218530Sjfv * Calculates the EEPROM section checksum by reading/adding each word of 2648218530Sjfv * the EEPROM and then verifies that the sum of the EEPROM is 2649218530Sjfv * equal to 0xBABA. 2650218530Sjfv **/ 2651218530Sjfvstatic s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) 2652218530Sjfv{ 2653267935Sjfv s32 ret_val; 2654218530Sjfv u16 eeprom_regions_count = 1; 2655218530Sjfv u16 j, nvm_data; 2656218530Sjfv u16 nvm_offset; 2657218530Sjfv 2658218530Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_82580"); 2659218530Sjfv 2660218530Sjfv ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2661218530Sjfv if (ret_val) { 2662218530Sjfv DEBUGOUT("NVM Read Error\n"); 2663218530Sjfv goto out; 2664218530Sjfv } 2665218530Sjfv 2666218530Sjfv if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2667218530Sjfv /* if chekcsums compatibility bit is set validate checksums 2668218530Sjfv * for all 4 ports. */ 2669218530Sjfv eeprom_regions_count = 4; 2670218530Sjfv } 2671218530Sjfv 2672218530Sjfv for (j = 0; j < eeprom_regions_count; j++) { 2673218530Sjfv nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2674218530Sjfv ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2675228386Sjfv nvm_offset); 2676218530Sjfv if (ret_val != E1000_SUCCESS) 2677218530Sjfv goto out; 2678218530Sjfv } 2679218530Sjfv 2680218530Sjfvout: 2681218530Sjfv return ret_val; 2682218530Sjfv} 2683218530Sjfv 2684218530Sjfv/** 2685218530Sjfv * e1000_update_nvm_checksum_82580 - Update EEPROM checksum 2686218530Sjfv * @hw: pointer to the HW structure 2687218530Sjfv * 2688218530Sjfv * Updates the EEPROM section checksums for all 4 ports by reading/adding 2689218530Sjfv * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2690218530Sjfv * checksum and writes the value to the EEPROM. 2691218530Sjfv **/ 2692218530Sjfvstatic s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) 2693218530Sjfv{ 2694218530Sjfv s32 ret_val; 2695218530Sjfv u16 j, nvm_data; 2696218530Sjfv u16 nvm_offset; 2697218530Sjfv 2698218530Sjfv DEBUGFUNC("e1000_update_nvm_checksum_82580"); 2699218530Sjfv 2700218530Sjfv ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2701218530Sjfv if (ret_val) { 2702228386Sjfv DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n"); 2703218530Sjfv goto out; 2704218530Sjfv } 2705218530Sjfv 2706238148Sjfv if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) { 2707218530Sjfv /* set compatibility bit to validate checksums appropriately */ 2708218530Sjfv nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2709218530Sjfv ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2710228386Sjfv &nvm_data); 2711218530Sjfv if (ret_val) { 2712228386Sjfv DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n"); 2713218530Sjfv goto out; 2714218530Sjfv } 2715218530Sjfv } 2716218530Sjfv 2717218530Sjfv for (j = 0; j < 4; j++) { 2718218530Sjfv nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2719218530Sjfv ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2720228386Sjfv if (ret_val) 2721218530Sjfv goto out; 2722218530Sjfv } 2723218530Sjfv 2724218530Sjfvout: 2725218530Sjfv return ret_val; 2726218530Sjfv} 2727218530Sjfv 2728218530Sjfv/** 2729218530Sjfv * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum 2730218530Sjfv * @hw: pointer to the HW structure 2731218530Sjfv * 2732218530Sjfv * Calculates the EEPROM section checksum by reading/adding each word of 2733218530Sjfv * the EEPROM and then verifies that the sum of the EEPROM is 2734218530Sjfv * equal to 0xBABA. 2735218530Sjfv **/ 2736218530Sjfvstatic s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) 2737218530Sjfv{ 2738218530Sjfv s32 ret_val = E1000_SUCCESS; 2739218530Sjfv u16 j; 2740218530Sjfv u16 nvm_offset; 2741218530Sjfv 2742218530Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_i350"); 2743218530Sjfv 2744218530Sjfv for (j = 0; j < 4; j++) { 2745218530Sjfv nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2746218530Sjfv ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2747228386Sjfv nvm_offset); 2748218530Sjfv if (ret_val != E1000_SUCCESS) 2749218530Sjfv goto out; 2750218530Sjfv } 2751218530Sjfv 2752218530Sjfvout: 2753218530Sjfv return ret_val; 2754218530Sjfv} 2755218530Sjfv 2756218530Sjfv/** 2757218530Sjfv * e1000_update_nvm_checksum_i350 - Update EEPROM checksum 2758218530Sjfv * @hw: pointer to the HW structure 2759218530Sjfv * 2760218530Sjfv * Updates the EEPROM section checksums for all 4 ports by reading/adding 2761218530Sjfv * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2762218530Sjfv * checksum and writes the value to the EEPROM. 2763218530Sjfv **/ 2764218530Sjfvstatic s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) 2765218530Sjfv{ 2766218530Sjfv s32 ret_val = E1000_SUCCESS; 2767218530Sjfv u16 j; 2768218530Sjfv u16 nvm_offset; 2769218530Sjfv 2770218530Sjfv DEBUGFUNC("e1000_update_nvm_checksum_i350"); 2771218530Sjfv 2772218530Sjfv for (j = 0; j < 4; j++) { 2773218530Sjfv nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2774218530Sjfv ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2775218530Sjfv if (ret_val != E1000_SUCCESS) 2776218530Sjfv goto out; 2777218530Sjfv } 2778218530Sjfv 2779218530Sjfvout: 2780218530Sjfv return ret_val; 2781218530Sjfv} 2782218530Sjfv 2783218530Sjfv/** 2784256200Sjfv * __e1000_access_emi_reg - Read/write EMI register 2785256200Sjfv * @hw: pointer to the HW structure 2786256200Sjfv * @addr: EMI address to program 2787256200Sjfv * @data: pointer to value to read/write from/to the EMI address 2788256200Sjfv * @read: boolean flag to indicate read or write 2789256200Sjfv **/ 2790256200Sjfvstatic s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address, 2791256200Sjfv u16 *data, bool read) 2792256200Sjfv{ 2793267935Sjfv s32 ret_val; 2794256200Sjfv 2795256200Sjfv DEBUGFUNC("__e1000_access_emi_reg"); 2796256200Sjfv 2797256200Sjfv ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); 2798256200Sjfv if (ret_val) 2799256200Sjfv return ret_val; 2800256200Sjfv 2801256200Sjfv if (read) 2802256200Sjfv ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); 2803256200Sjfv else 2804256200Sjfv ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); 2805256200Sjfv 2806256200Sjfv return ret_val; 2807256200Sjfv} 2808256200Sjfv 2809256200Sjfv/** 2810256200Sjfv * e1000_read_emi_reg - Read Extended Management Interface register 2811256200Sjfv * @hw: pointer to the HW structure 2812256200Sjfv * @addr: EMI address to program 2813256200Sjfv * @data: value to be read from the EMI address 2814256200Sjfv **/ 2815256200Sjfvs32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) 2816256200Sjfv{ 2817256200Sjfv DEBUGFUNC("e1000_read_emi_reg"); 2818256200Sjfv 2819256200Sjfv return __e1000_access_emi_reg(hw, addr, data, TRUE); 2820256200Sjfv} 2821256200Sjfv 2822256200Sjfv/** 2823267935Sjfv * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY 2824267935Sjfv * @hw: pointer to the HW structure 2825267935Sjfv * 2826295323Serj * Initialize Marvell 1512 to work correctly with Avoton. 2827267935Sjfv **/ 2828267935Sjfvs32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw) 2829267935Sjfv{ 2830267935Sjfv struct e1000_phy_info *phy = &hw->phy; 2831267935Sjfv s32 ret_val = E1000_SUCCESS; 2832267935Sjfv 2833267935Sjfv DEBUGFUNC("e1000_initialize_M88E1512_phy"); 2834267935Sjfv 2835267935Sjfv /* Check if this is correct PHY. */ 2836267935Sjfv if (phy->id != M88E1512_E_PHY_ID) 2837267935Sjfv goto out; 2838267935Sjfv 2839267935Sjfv /* Switch to PHY page 0xFF. */ 2840267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); 2841267935Sjfv if (ret_val) 2842267935Sjfv goto out; 2843267935Sjfv 2844267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); 2845267935Sjfv if (ret_val) 2846267935Sjfv goto out; 2847267935Sjfv 2848267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); 2849267935Sjfv if (ret_val) 2850267935Sjfv goto out; 2851267935Sjfv 2852267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); 2853267935Sjfv if (ret_val) 2854267935Sjfv goto out; 2855267935Sjfv 2856267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); 2857267935Sjfv if (ret_val) 2858267935Sjfv goto out; 2859267935Sjfv 2860267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); 2861267935Sjfv if (ret_val) 2862267935Sjfv goto out; 2863267935Sjfv 2864267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); 2865267935Sjfv if (ret_val) 2866267935Sjfv goto out; 2867267935Sjfv 2868267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C); 2869267935Sjfv if (ret_val) 2870267935Sjfv goto out; 2871267935Sjfv 2872267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); 2873267935Sjfv if (ret_val) 2874267935Sjfv goto out; 2875267935Sjfv 2876267935Sjfv /* Switch to PHY page 0xFB. */ 2877267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); 2878267935Sjfv if (ret_val) 2879267935Sjfv goto out; 2880267935Sjfv 2881267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D); 2882267935Sjfv if (ret_val) 2883267935Sjfv goto out; 2884267935Sjfv 2885267935Sjfv /* Switch to PHY page 0x12. */ 2886267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); 2887267935Sjfv if (ret_val) 2888267935Sjfv goto out; 2889267935Sjfv 2890267935Sjfv /* Change mode to SGMII-to-Copper */ 2891267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); 2892267935Sjfv if (ret_val) 2893267935Sjfv goto out; 2894267935Sjfv 2895267935Sjfv /* Return the PHY to page 0. */ 2896267935Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2897267935Sjfv if (ret_val) 2898267935Sjfv goto out; 2899267935Sjfv 2900267935Sjfv ret_val = phy->ops.commit(hw); 2901267935Sjfv if (ret_val) { 2902267935Sjfv DEBUGOUT("Error committing the PHY changes\n"); 2903267935Sjfv return ret_val; 2904267935Sjfv } 2905267935Sjfv 2906267935Sjfv msec_delay(1000); 2907267935Sjfvout: 2908267935Sjfv return ret_val; 2909267935Sjfv} 2910267935Sjfv 2911267935Sjfv/** 2912295323Serj * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY 2913295323Serj * @hw: pointer to the HW structure 2914295323Serj * 2915295323Serj * Initialize Marvell 1543 to work correctly with Avoton. 2916295323Serj **/ 2917295323Serjs32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw) 2918295323Serj{ 2919295323Serj struct e1000_phy_info *phy = &hw->phy; 2920295323Serj s32 ret_val = E1000_SUCCESS; 2921295323Serj 2922295323Serj DEBUGFUNC("e1000_initialize_M88E1543_phy"); 2923295323Serj 2924295323Serj /* Check if this is correct PHY. */ 2925295323Serj if (phy->id != M88E1543_E_PHY_ID) 2926295323Serj goto out; 2927295323Serj 2928295323Serj /* Switch to PHY page 0xFF. */ 2929295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); 2930295323Serj if (ret_val) 2931295323Serj goto out; 2932295323Serj 2933295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); 2934295323Serj if (ret_val) 2935295323Serj goto out; 2936295323Serj 2937295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); 2938295323Serj if (ret_val) 2939295323Serj goto out; 2940295323Serj 2941295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); 2942295323Serj if (ret_val) 2943295323Serj goto out; 2944295323Serj 2945295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); 2946295323Serj if (ret_val) 2947295323Serj goto out; 2948295323Serj 2949295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); 2950295323Serj if (ret_val) 2951295323Serj goto out; 2952295323Serj 2953295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); 2954295323Serj if (ret_val) 2955295323Serj goto out; 2956295323Serj 2957295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C); 2958295323Serj if (ret_val) 2959295323Serj goto out; 2960295323Serj 2961295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); 2962295323Serj if (ret_val) 2963295323Serj goto out; 2964295323Serj 2965295323Serj /* Switch to PHY page 0xFB. */ 2966295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); 2967295323Serj if (ret_val) 2968295323Serj goto out; 2969295323Serj 2970295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D); 2971295323Serj if (ret_val) 2972295323Serj goto out; 2973295323Serj 2974295323Serj /* Switch to PHY page 0x12. */ 2975295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); 2976295323Serj if (ret_val) 2977295323Serj goto out; 2978295323Serj 2979295323Serj /* Change mode to SGMII-to-Copper */ 2980295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); 2981295323Serj if (ret_val) 2982295323Serj goto out; 2983295323Serj 2984295323Serj /* Switch to PHY page 1. */ 2985295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1); 2986295323Serj if (ret_val) 2987295323Serj goto out; 2988295323Serj 2989295323Serj /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */ 2990295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140); 2991295323Serj if (ret_val) 2992295323Serj goto out; 2993295323Serj 2994295323Serj /* Return the PHY to page 0. */ 2995295323Serj ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2996295323Serj if (ret_val) 2997295323Serj goto out; 2998295323Serj 2999295323Serj ret_val = phy->ops.commit(hw); 3000295323Serj if (ret_val) { 3001295323Serj DEBUGOUT("Error committing the PHY changes\n"); 3002295323Serj return ret_val; 3003295323Serj } 3004295323Serj 3005295323Serj msec_delay(1000); 3006295323Serjout: 3007295323Serj return ret_val; 3008295323Serj} 3009295323Serj 3010295323Serj/** 3011218530Sjfv * e1000_set_eee_i350 - Enable/disable EEE support 3012218530Sjfv * @hw: pointer to the HW structure 3013295323Serj * @adv1g: boolean flag enabling 1G EEE advertisement 3014295323Serj * @adv100m: boolean flag enabling 100M EEE advertisement 3015218530Sjfv * 3016218530Sjfv * Enable/disable EEE based on setting in dev_spec structure. 3017218530Sjfv * 3018218530Sjfv **/ 3019295323Serjs32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) 3020218530Sjfv{ 3021228386Sjfv u32 ipcnfg, eeer; 3022218530Sjfv 3023218530Sjfv DEBUGFUNC("e1000_set_eee_i350"); 3024218530Sjfv 3025228386Sjfv if ((hw->mac.type < e1000_i350) || 3026228386Sjfv (hw->phy.media_type != e1000_media_type_copper)) 3027218530Sjfv goto out; 3028218530Sjfv ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); 3029218530Sjfv eeer = E1000_READ_REG(hw, E1000_EEER); 3030218530Sjfv 3031218530Sjfv /* enable or disable per user setting */ 3032218530Sjfv if (!(hw->dev_spec._82575.eee_disable)) { 3033247064Sjfv u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU); 3034247064Sjfv 3035295323Serj if (adv100M) 3036295323Serj ipcnfg |= E1000_IPCNFG_EEE_100M_AN; 3037295323Serj else 3038295323Serj ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN; 3039295323Serj 3040295323Serj if (adv1G) 3041295323Serj ipcnfg |= E1000_IPCNFG_EEE_1G_AN; 3042295323Serj else 3043295323Serj ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN; 3044295323Serj 3045228386Sjfv eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 3046228386Sjfv E1000_EEER_LPI_FC); 3047218530Sjfv 3048247064Sjfv /* This bit should not be set in normal operation. */ 3049247064Sjfv if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 3050247064Sjfv DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); 3051218530Sjfv } else { 3052228386Sjfv ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 3053228386Sjfv eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 3054228386Sjfv E1000_EEER_LPI_FC); 3055218530Sjfv } 3056218530Sjfv E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 3057218530Sjfv E1000_WRITE_REG(hw, E1000_EEER, eeer); 3058228386Sjfv E1000_READ_REG(hw, E1000_IPCNFG); 3059228386Sjfv E1000_READ_REG(hw, E1000_EEER); 3060218530Sjfvout: 3061218530Sjfv 3062267935Sjfv return E1000_SUCCESS; 3063218530Sjfv} 3064228386Sjfv 3065256200Sjfv/** 3066256200Sjfv * e1000_set_eee_i354 - Enable/disable EEE support 3067256200Sjfv * @hw: pointer to the HW structure 3068295323Serj * @adv1g: boolean flag enabling 1G EEE advertisement 3069295323Serj * @adv100m: boolean flag enabling 100M EEE advertisement 3070256200Sjfv * 3071256200Sjfv * Enable/disable EEE legacy mode based on setting in dev_spec structure. 3072256200Sjfv * 3073256200Sjfv **/ 3074295323Serjs32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) 3075256200Sjfv{ 3076256200Sjfv struct e1000_phy_info *phy = &hw->phy; 3077256200Sjfv s32 ret_val = E1000_SUCCESS; 3078256200Sjfv u16 phy_data; 3079256200Sjfv 3080256200Sjfv DEBUGFUNC("e1000_set_eee_i354"); 3081256200Sjfv 3082256200Sjfv if ((hw->phy.media_type != e1000_media_type_copper) || 3083256200Sjfv ((phy->id != M88E1543_E_PHY_ID) && 3084256200Sjfv (phy->id != M88E1512_E_PHY_ID))) 3085256200Sjfv goto out; 3086256200Sjfv 3087256200Sjfv if (!hw->dev_spec._82575.eee_disable) { 3088256200Sjfv /* Switch to PHY page 18. */ 3089256200Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); 3090256200Sjfv if (ret_val) 3091256200Sjfv goto out; 3092256200Sjfv 3093256200Sjfv ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, 3094256200Sjfv &phy_data); 3095256200Sjfv if (ret_val) 3096256200Sjfv goto out; 3097256200Sjfv 3098256200Sjfv phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 3099256200Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, 3100256200Sjfv phy_data); 3101256200Sjfv if (ret_val) 3102256200Sjfv goto out; 3103256200Sjfv 3104256200Sjfv /* Return the PHY to page 0. */ 3105256200Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 3106256200Sjfv if (ret_val) 3107256200Sjfv goto out; 3108256200Sjfv 3109256200Sjfv /* Turn on EEE advertisement. */ 3110256200Sjfv ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 3111256200Sjfv E1000_EEE_ADV_DEV_I354, 3112256200Sjfv &phy_data); 3113256200Sjfv if (ret_val) 3114256200Sjfv goto out; 3115256200Sjfv 3116295323Serj if (adv100M) 3117295323Serj phy_data |= E1000_EEE_ADV_100_SUPPORTED; 3118295323Serj else 3119295323Serj phy_data &= ~E1000_EEE_ADV_100_SUPPORTED; 3120295323Serj 3121295323Serj if (adv1G) 3122295323Serj phy_data |= E1000_EEE_ADV_1000_SUPPORTED; 3123295323Serj else 3124295323Serj phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED; 3125295323Serj 3126256200Sjfv ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 3127256200Sjfv E1000_EEE_ADV_DEV_I354, 3128256200Sjfv phy_data); 3129256200Sjfv } else { 3130256200Sjfv /* Turn off EEE advertisement. */ 3131256200Sjfv ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 3132256200Sjfv E1000_EEE_ADV_DEV_I354, 3133256200Sjfv &phy_data); 3134256200Sjfv if (ret_val) 3135256200Sjfv goto out; 3136256200Sjfv 3137256200Sjfv phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | 3138256200Sjfv E1000_EEE_ADV_1000_SUPPORTED); 3139256200Sjfv ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 3140256200Sjfv E1000_EEE_ADV_DEV_I354, 3141256200Sjfv phy_data); 3142256200Sjfv } 3143256200Sjfv 3144256200Sjfvout: 3145256200Sjfv return ret_val; 3146256200Sjfv} 3147256200Sjfv 3148256200Sjfv/** 3149256200Sjfv * e1000_get_eee_status_i354 - Get EEE status 3150256200Sjfv * @hw: pointer to the HW structure 3151256200Sjfv * @status: EEE status 3152256200Sjfv * 3153256200Sjfv * Get EEE status by guessing based on whether Tx or Rx LPI indications have 3154256200Sjfv * been received. 3155256200Sjfv **/ 3156256200Sjfvs32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status) 3157256200Sjfv{ 3158256200Sjfv struct e1000_phy_info *phy = &hw->phy; 3159256200Sjfv s32 ret_val = E1000_SUCCESS; 3160256200Sjfv u16 phy_data; 3161256200Sjfv 3162256200Sjfv DEBUGFUNC("e1000_get_eee_status_i354"); 3163256200Sjfv 3164256200Sjfv /* Check if EEE is supported on this device. */ 3165256200Sjfv if ((hw->phy.media_type != e1000_media_type_copper) || 3166256200Sjfv ((phy->id != M88E1543_E_PHY_ID) && 3167256200Sjfv (phy->id != M88E1512_E_PHY_ID))) 3168256200Sjfv goto out; 3169256200Sjfv 3170256200Sjfv ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, 3171256200Sjfv E1000_PCS_STATUS_DEV_I354, 3172256200Sjfv &phy_data); 3173256200Sjfv if (ret_val) 3174256200Sjfv goto out; 3175256200Sjfv 3176256200Sjfv *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | 3177256200Sjfv E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE; 3178256200Sjfv 3179256200Sjfvout: 3180256200Sjfv return ret_val; 3181256200Sjfv} 3182256200Sjfv 3183228386Sjfv/* Due to a hw errata, if the host tries to configure the VFTA register 3184228386Sjfv * while performing queries from the BMC or DMA, then the VFTA in some 3185228386Sjfv * cases won't be written. 3186228386Sjfv */ 3187228386Sjfv 3188228386Sjfv/** 3189228386Sjfv * e1000_clear_vfta_i350 - Clear VLAN filter table 3190228386Sjfv * @hw: pointer to the HW structure 3191228386Sjfv * 3192228386Sjfv * Clears the register array which contains the VLAN filter table by 3193228386Sjfv * setting all the values to 0. 3194228386Sjfv **/ 3195228386Sjfvvoid e1000_clear_vfta_i350(struct e1000_hw *hw) 3196228386Sjfv{ 3197228386Sjfv u32 offset; 3198228386Sjfv int i; 3199228386Sjfv 3200228386Sjfv DEBUGFUNC("e1000_clear_vfta_350"); 3201228386Sjfv 3202228386Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 3203228386Sjfv for (i = 0; i < 10; i++) 3204228386Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 3205228386Sjfv 3206228386Sjfv E1000_WRITE_FLUSH(hw); 3207228386Sjfv } 3208228386Sjfv} 3209228386Sjfv 3210228386Sjfv/** 3211228386Sjfv * e1000_write_vfta_i350 - Write value to VLAN filter table 3212228386Sjfv * @hw: pointer to the HW structure 3213228386Sjfv * @offset: register offset in VLAN filter table 3214228386Sjfv * @value: register value written to VLAN filter table 3215228386Sjfv * 3216228386Sjfv * Writes value at the given offset in the register array which stores 3217228386Sjfv * the VLAN filter table. 3218228386Sjfv **/ 3219228386Sjfvvoid e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 3220228386Sjfv{ 3221228386Sjfv int i; 3222228386Sjfv 3223228386Sjfv DEBUGFUNC("e1000_write_vfta_350"); 3224228386Sjfv 3225228386Sjfv for (i = 0; i < 10; i++) 3226228386Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 3227228386Sjfv 3228228386Sjfv E1000_WRITE_FLUSH(hw); 3229228386Sjfv} 3230228386Sjfv 3231228386Sjfv 3232228386Sjfv/** 3233228386Sjfv * e1000_set_i2c_bb - Enable I2C bit-bang 3234228386Sjfv * @hw: pointer to the HW structure 3235228386Sjfv * 3236228386Sjfv * Enable I2C bit-bang interface 3237228386Sjfv * 3238228386Sjfv **/ 3239228386Sjfvs32 e1000_set_i2c_bb(struct e1000_hw *hw) 3240228386Sjfv{ 3241228386Sjfv s32 ret_val = E1000_SUCCESS; 3242228386Sjfv u32 ctrl_ext, i2cparams; 3243228386Sjfv 3244228386Sjfv DEBUGFUNC("e1000_set_i2c_bb"); 3245228386Sjfv 3246228386Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3247228386Sjfv ctrl_ext |= E1000_CTRL_I2C_ENA; 3248228386Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3249228386Sjfv E1000_WRITE_FLUSH(hw); 3250228386Sjfv 3251228386Sjfv i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS); 3252228386Sjfv i2cparams |= E1000_I2CBB_EN; 3253228386Sjfv i2cparams |= E1000_I2C_DATA_OE_N; 3254228386Sjfv i2cparams |= E1000_I2C_CLK_OE_N; 3255228386Sjfv E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams); 3256228386Sjfv E1000_WRITE_FLUSH(hw); 3257228386Sjfv 3258228386Sjfv return ret_val; 3259228386Sjfv} 3260228386Sjfv 3261228386Sjfv/** 3262228386Sjfv * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C 3263228386Sjfv * @hw: pointer to hardware structure 3264228386Sjfv * @byte_offset: byte offset to read 3265238148Sjfv * @dev_addr: device address 3266228386Sjfv * @data: value read 3267228386Sjfv * 3268228386Sjfv * Performs byte read operation over I2C interface at 3269228386Sjfv * a specified device address. 3270228386Sjfv **/ 3271228386Sjfvs32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 3272228386Sjfv u8 dev_addr, u8 *data) 3273228386Sjfv{ 3274228386Sjfv s32 status = E1000_SUCCESS; 3275228386Sjfv u32 max_retry = 10; 3276228386Sjfv u32 retry = 1; 3277228386Sjfv u16 swfw_mask = 0; 3278228386Sjfv 3279238148Sjfv bool nack = TRUE; 3280228386Sjfv 3281228386Sjfv DEBUGFUNC("e1000_read_i2c_byte_generic"); 3282228386Sjfv 3283228386Sjfv swfw_mask = E1000_SWFW_PHY0_SM; 3284228386Sjfv 3285228386Sjfv do { 3286238148Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 3287228386Sjfv != E1000_SUCCESS) { 3288228386Sjfv status = E1000_ERR_SWFW_SYNC; 3289228386Sjfv goto read_byte_out; 3290228386Sjfv } 3291228386Sjfv 3292228386Sjfv e1000_i2c_start(hw); 3293228386Sjfv 3294228386Sjfv /* Device Address and write indication */ 3295228386Sjfv status = e1000_clock_out_i2c_byte(hw, dev_addr); 3296228386Sjfv if (status != E1000_SUCCESS) 3297228386Sjfv goto fail; 3298228386Sjfv 3299228386Sjfv status = e1000_get_i2c_ack(hw); 3300228386Sjfv if (status != E1000_SUCCESS) 3301228386Sjfv goto fail; 3302228386Sjfv 3303228386Sjfv status = e1000_clock_out_i2c_byte(hw, byte_offset); 3304228386Sjfv if (status != E1000_SUCCESS) 3305228386Sjfv goto fail; 3306228386Sjfv 3307228386Sjfv status = e1000_get_i2c_ack(hw); 3308228386Sjfv if (status != E1000_SUCCESS) 3309228386Sjfv goto fail; 3310228386Sjfv 3311228386Sjfv e1000_i2c_start(hw); 3312228386Sjfv 3313228386Sjfv /* Device Address and read indication */ 3314228386Sjfv status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 3315228386Sjfv if (status != E1000_SUCCESS) 3316228386Sjfv goto fail; 3317228386Sjfv 3318228386Sjfv status = e1000_get_i2c_ack(hw); 3319228386Sjfv if (status != E1000_SUCCESS) 3320228386Sjfv goto fail; 3321228386Sjfv 3322228386Sjfv status = e1000_clock_in_i2c_byte(hw, data); 3323228386Sjfv if (status != E1000_SUCCESS) 3324228386Sjfv goto fail; 3325228386Sjfv 3326228386Sjfv status = e1000_clock_out_i2c_bit(hw, nack); 3327228386Sjfv if (status != E1000_SUCCESS) 3328228386Sjfv goto fail; 3329228386Sjfv 3330228386Sjfv e1000_i2c_stop(hw); 3331228386Sjfv break; 3332228386Sjfv 3333228386Sjfvfail: 3334238148Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3335228386Sjfv msec_delay(100); 3336228386Sjfv e1000_i2c_bus_clear(hw); 3337228386Sjfv retry++; 3338228386Sjfv if (retry < max_retry) 3339228386Sjfv DEBUGOUT("I2C byte read error - Retrying.\n"); 3340228386Sjfv else 3341228386Sjfv DEBUGOUT("I2C byte read error.\n"); 3342228386Sjfv 3343228386Sjfv } while (retry < max_retry); 3344228386Sjfv 3345238148Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3346228386Sjfv 3347228386Sjfvread_byte_out: 3348228386Sjfv 3349228386Sjfv return status; 3350228386Sjfv} 3351228386Sjfv 3352228386Sjfv/** 3353228386Sjfv * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C 3354228386Sjfv * @hw: pointer to hardware structure 3355228386Sjfv * @byte_offset: byte offset to write 3356238148Sjfv * @dev_addr: device address 3357228386Sjfv * @data: value to write 3358228386Sjfv * 3359228386Sjfv * Performs byte write operation over I2C interface at 3360228386Sjfv * a specified device address. 3361228386Sjfv **/ 3362228386Sjfvs32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 3363228386Sjfv u8 dev_addr, u8 data) 3364228386Sjfv{ 3365228386Sjfv s32 status = E1000_SUCCESS; 3366228386Sjfv u32 max_retry = 1; 3367228386Sjfv u32 retry = 0; 3368228386Sjfv u16 swfw_mask = 0; 3369228386Sjfv 3370228386Sjfv DEBUGFUNC("e1000_write_i2c_byte_generic"); 3371228386Sjfv 3372228386Sjfv swfw_mask = E1000_SWFW_PHY0_SM; 3373228386Sjfv 3374238148Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) { 3375228386Sjfv status = E1000_ERR_SWFW_SYNC; 3376228386Sjfv goto write_byte_out; 3377228386Sjfv } 3378228386Sjfv 3379228386Sjfv do { 3380228386Sjfv e1000_i2c_start(hw); 3381228386Sjfv 3382228386Sjfv status = e1000_clock_out_i2c_byte(hw, dev_addr); 3383228386Sjfv if (status != E1000_SUCCESS) 3384228386Sjfv goto fail; 3385228386Sjfv 3386228386Sjfv status = e1000_get_i2c_ack(hw); 3387228386Sjfv if (status != E1000_SUCCESS) 3388228386Sjfv goto fail; 3389228386Sjfv 3390228386Sjfv status = e1000_clock_out_i2c_byte(hw, byte_offset); 3391228386Sjfv if (status != E1000_SUCCESS) 3392228386Sjfv goto fail; 3393228386Sjfv 3394228386Sjfv status = e1000_get_i2c_ack(hw); 3395228386Sjfv if (status != E1000_SUCCESS) 3396228386Sjfv goto fail; 3397228386Sjfv 3398228386Sjfv status = e1000_clock_out_i2c_byte(hw, data); 3399228386Sjfv if (status != E1000_SUCCESS) 3400228386Sjfv goto fail; 3401228386Sjfv 3402228386Sjfv status = e1000_get_i2c_ack(hw); 3403228386Sjfv if (status != E1000_SUCCESS) 3404228386Sjfv goto fail; 3405228386Sjfv 3406228386Sjfv e1000_i2c_stop(hw); 3407228386Sjfv break; 3408228386Sjfv 3409228386Sjfvfail: 3410228386Sjfv e1000_i2c_bus_clear(hw); 3411228386Sjfv retry++; 3412228386Sjfv if (retry < max_retry) 3413228386Sjfv DEBUGOUT("I2C byte write error - Retrying.\n"); 3414228386Sjfv else 3415228386Sjfv DEBUGOUT("I2C byte write error.\n"); 3416228386Sjfv } while (retry < max_retry); 3417228386Sjfv 3418238148Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3419228386Sjfv 3420228386Sjfvwrite_byte_out: 3421228386Sjfv 3422228386Sjfv return status; 3423228386Sjfv} 3424228386Sjfv 3425228386Sjfv/** 3426228386Sjfv * e1000_i2c_start - Sets I2C start condition 3427228386Sjfv * @hw: pointer to hardware structure 3428228386Sjfv * 3429228386Sjfv * Sets I2C start condition (High -> Low on SDA while SCL is High) 3430228386Sjfv **/ 3431228386Sjfvstatic void e1000_i2c_start(struct e1000_hw *hw) 3432228386Sjfv{ 3433228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3434228386Sjfv 3435228386Sjfv DEBUGFUNC("e1000_i2c_start"); 3436228386Sjfv 3437228386Sjfv /* Start condition must begin with data and clock high */ 3438228386Sjfv e1000_set_i2c_data(hw, &i2cctl, 1); 3439228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3440228386Sjfv 3441228386Sjfv /* Setup time for start condition (4.7us) */ 3442228386Sjfv usec_delay(E1000_I2C_T_SU_STA); 3443228386Sjfv 3444228386Sjfv e1000_set_i2c_data(hw, &i2cctl, 0); 3445228386Sjfv 3446228386Sjfv /* Hold time for start condition (4us) */ 3447228386Sjfv usec_delay(E1000_I2C_T_HD_STA); 3448228386Sjfv 3449228386Sjfv e1000_lower_i2c_clk(hw, &i2cctl); 3450228386Sjfv 3451228386Sjfv /* Minimum low period of clock is 4.7 us */ 3452228386Sjfv usec_delay(E1000_I2C_T_LOW); 3453228386Sjfv 3454228386Sjfv} 3455228386Sjfv 3456228386Sjfv/** 3457228386Sjfv * e1000_i2c_stop - Sets I2C stop condition 3458228386Sjfv * @hw: pointer to hardware structure 3459228386Sjfv * 3460228386Sjfv * Sets I2C stop condition (Low -> High on SDA while SCL is High) 3461228386Sjfv **/ 3462228386Sjfvstatic void e1000_i2c_stop(struct e1000_hw *hw) 3463228386Sjfv{ 3464228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3465228386Sjfv 3466228386Sjfv DEBUGFUNC("e1000_i2c_stop"); 3467228386Sjfv 3468228386Sjfv /* Stop condition must begin with data low and clock high */ 3469228386Sjfv e1000_set_i2c_data(hw, &i2cctl, 0); 3470228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3471228386Sjfv 3472228386Sjfv /* Setup time for stop condition (4us) */ 3473228386Sjfv usec_delay(E1000_I2C_T_SU_STO); 3474228386Sjfv 3475228386Sjfv e1000_set_i2c_data(hw, &i2cctl, 1); 3476228386Sjfv 3477228386Sjfv /* bus free time between stop and start (4.7us)*/ 3478228386Sjfv usec_delay(E1000_I2C_T_BUF); 3479228386Sjfv} 3480228386Sjfv 3481228386Sjfv/** 3482228386Sjfv * e1000_clock_in_i2c_byte - Clocks in one byte via I2C 3483228386Sjfv * @hw: pointer to hardware structure 3484228386Sjfv * @data: data byte to clock in 3485228386Sjfv * 3486228386Sjfv * Clocks in one byte data via I2C data/clock 3487228386Sjfv **/ 3488228386Sjfvstatic s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data) 3489228386Sjfv{ 3490228386Sjfv s32 i; 3491228386Sjfv bool bit = 0; 3492228386Sjfv 3493228386Sjfv DEBUGFUNC("e1000_clock_in_i2c_byte"); 3494228386Sjfv 3495228386Sjfv *data = 0; 3496228386Sjfv for (i = 7; i >= 0; i--) { 3497228386Sjfv e1000_clock_in_i2c_bit(hw, &bit); 3498228386Sjfv *data |= bit << i; 3499228386Sjfv } 3500228386Sjfv 3501228386Sjfv return E1000_SUCCESS; 3502228386Sjfv} 3503228386Sjfv 3504228386Sjfv/** 3505228386Sjfv * e1000_clock_out_i2c_byte - Clocks out one byte via I2C 3506228386Sjfv * @hw: pointer to hardware structure 3507228386Sjfv * @data: data byte clocked out 3508228386Sjfv * 3509228386Sjfv * Clocks out one byte data via I2C data/clock 3510228386Sjfv **/ 3511228386Sjfvstatic s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data) 3512228386Sjfv{ 3513228386Sjfv s32 status = E1000_SUCCESS; 3514228386Sjfv s32 i; 3515228386Sjfv u32 i2cctl; 3516228386Sjfv bool bit = 0; 3517228386Sjfv 3518228386Sjfv DEBUGFUNC("e1000_clock_out_i2c_byte"); 3519228386Sjfv 3520228386Sjfv for (i = 7; i >= 0; i--) { 3521228386Sjfv bit = (data >> i) & 0x1; 3522228386Sjfv status = e1000_clock_out_i2c_bit(hw, bit); 3523228386Sjfv 3524228386Sjfv if (status != E1000_SUCCESS) 3525228386Sjfv break; 3526228386Sjfv } 3527228386Sjfv 3528228386Sjfv /* Release SDA line (set high) */ 3529228386Sjfv i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3530228386Sjfv 3531228386Sjfv i2cctl |= E1000_I2C_DATA_OE_N; 3532228386Sjfv E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl); 3533228386Sjfv E1000_WRITE_FLUSH(hw); 3534228386Sjfv 3535228386Sjfv return status; 3536228386Sjfv} 3537228386Sjfv 3538228386Sjfv/** 3539228386Sjfv * e1000_get_i2c_ack - Polls for I2C ACK 3540228386Sjfv * @hw: pointer to hardware structure 3541228386Sjfv * 3542228386Sjfv * Clocks in/out one bit via I2C data/clock 3543228386Sjfv **/ 3544228386Sjfvstatic s32 e1000_get_i2c_ack(struct e1000_hw *hw) 3545228386Sjfv{ 3546228386Sjfv s32 status = E1000_SUCCESS; 3547228386Sjfv u32 i = 0; 3548228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3549228386Sjfv u32 timeout = 10; 3550238148Sjfv bool ack = TRUE; 3551228386Sjfv 3552228386Sjfv DEBUGFUNC("e1000_get_i2c_ack"); 3553228386Sjfv 3554228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3555228386Sjfv 3556228386Sjfv /* Minimum high period of clock is 4us */ 3557228386Sjfv usec_delay(E1000_I2C_T_HIGH); 3558228386Sjfv 3559228386Sjfv /* Wait until SCL returns high */ 3560228386Sjfv for (i = 0; i < timeout; i++) { 3561228386Sjfv usec_delay(1); 3562228386Sjfv i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3563228386Sjfv if (i2cctl & E1000_I2C_CLK_IN) 3564228386Sjfv break; 3565228386Sjfv } 3566228386Sjfv if (!(i2cctl & E1000_I2C_CLK_IN)) 3567228386Sjfv return E1000_ERR_I2C; 3568228386Sjfv 3569228386Sjfv ack = e1000_get_i2c_data(&i2cctl); 3570238148Sjfv if (ack) { 3571228386Sjfv DEBUGOUT("I2C ack was not received.\n"); 3572228386Sjfv status = E1000_ERR_I2C; 3573228386Sjfv } 3574228386Sjfv 3575228386Sjfv e1000_lower_i2c_clk(hw, &i2cctl); 3576228386Sjfv 3577228386Sjfv /* Minimum low period of clock is 4.7 us */ 3578228386Sjfv usec_delay(E1000_I2C_T_LOW); 3579228386Sjfv 3580228386Sjfv return status; 3581228386Sjfv} 3582228386Sjfv 3583228386Sjfv/** 3584228386Sjfv * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 3585228386Sjfv * @hw: pointer to hardware structure 3586228386Sjfv * @data: read data value 3587228386Sjfv * 3588228386Sjfv * Clocks in one bit via I2C data/clock 3589228386Sjfv **/ 3590228386Sjfvstatic s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data) 3591228386Sjfv{ 3592228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3593228386Sjfv 3594228386Sjfv DEBUGFUNC("e1000_clock_in_i2c_bit"); 3595228386Sjfv 3596228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3597228386Sjfv 3598228386Sjfv /* Minimum high period of clock is 4us */ 3599228386Sjfv usec_delay(E1000_I2C_T_HIGH); 3600228386Sjfv 3601228386Sjfv i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3602228386Sjfv *data = e1000_get_i2c_data(&i2cctl); 3603228386Sjfv 3604228386Sjfv e1000_lower_i2c_clk(hw, &i2cctl); 3605228386Sjfv 3606228386Sjfv /* Minimum low period of clock is 4.7 us */ 3607228386Sjfv usec_delay(E1000_I2C_T_LOW); 3608228386Sjfv 3609228386Sjfv return E1000_SUCCESS; 3610228386Sjfv} 3611228386Sjfv 3612228386Sjfv/** 3613228386Sjfv * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 3614228386Sjfv * @hw: pointer to hardware structure 3615228386Sjfv * @data: data value to write 3616228386Sjfv * 3617228386Sjfv * Clocks out one bit via I2C data/clock 3618228386Sjfv **/ 3619228386Sjfvstatic s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data) 3620228386Sjfv{ 3621228386Sjfv s32 status; 3622228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3623228386Sjfv 3624228386Sjfv DEBUGFUNC("e1000_clock_out_i2c_bit"); 3625228386Sjfv 3626228386Sjfv status = e1000_set_i2c_data(hw, &i2cctl, data); 3627228386Sjfv if (status == E1000_SUCCESS) { 3628228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3629228386Sjfv 3630228386Sjfv /* Minimum high period of clock is 4us */ 3631228386Sjfv usec_delay(E1000_I2C_T_HIGH); 3632228386Sjfv 3633228386Sjfv e1000_lower_i2c_clk(hw, &i2cctl); 3634228386Sjfv 3635228386Sjfv /* Minimum low period of clock is 4.7 us. 3636228386Sjfv * This also takes care of the data hold time. 3637228386Sjfv */ 3638228386Sjfv usec_delay(E1000_I2C_T_LOW); 3639228386Sjfv } else { 3640228386Sjfv status = E1000_ERR_I2C; 3641228386Sjfv DEBUGOUT1("I2C data was not set to %X\n", data); 3642228386Sjfv } 3643228386Sjfv 3644228386Sjfv return status; 3645228386Sjfv} 3646228386Sjfv/** 3647228386Sjfv * e1000_raise_i2c_clk - Raises the I2C SCL clock 3648228386Sjfv * @hw: pointer to hardware structure 3649228386Sjfv * @i2cctl: Current value of I2CCTL register 3650228386Sjfv * 3651228386Sjfv * Raises the I2C clock line '0'->'1' 3652228386Sjfv **/ 3653228386Sjfvstatic void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3654228386Sjfv{ 3655228386Sjfv DEBUGFUNC("e1000_raise_i2c_clk"); 3656228386Sjfv 3657228386Sjfv *i2cctl |= E1000_I2C_CLK_OUT; 3658228386Sjfv *i2cctl &= ~E1000_I2C_CLK_OE_N; 3659228386Sjfv E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3660228386Sjfv E1000_WRITE_FLUSH(hw); 3661228386Sjfv 3662228386Sjfv /* SCL rise time (1000ns) */ 3663228386Sjfv usec_delay(E1000_I2C_T_RISE); 3664228386Sjfv} 3665228386Sjfv 3666228386Sjfv/** 3667228386Sjfv * e1000_lower_i2c_clk - Lowers the I2C SCL clock 3668228386Sjfv * @hw: pointer to hardware structure 3669228386Sjfv * @i2cctl: Current value of I2CCTL register 3670228386Sjfv * 3671228386Sjfv * Lowers the I2C clock line '1'->'0' 3672228386Sjfv **/ 3673228386Sjfvstatic void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3674228386Sjfv{ 3675228386Sjfv 3676228386Sjfv DEBUGFUNC("e1000_lower_i2c_clk"); 3677228386Sjfv 3678228386Sjfv *i2cctl &= ~E1000_I2C_CLK_OUT; 3679228386Sjfv *i2cctl &= ~E1000_I2C_CLK_OE_N; 3680228386Sjfv E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3681228386Sjfv E1000_WRITE_FLUSH(hw); 3682228386Sjfv 3683228386Sjfv /* SCL fall time (300ns) */ 3684228386Sjfv usec_delay(E1000_I2C_T_FALL); 3685228386Sjfv} 3686228386Sjfv 3687228386Sjfv/** 3688228386Sjfv * e1000_set_i2c_data - Sets the I2C data bit 3689228386Sjfv * @hw: pointer to hardware structure 3690228386Sjfv * @i2cctl: Current value of I2CCTL register 3691228386Sjfv * @data: I2C data value (0 or 1) to set 3692228386Sjfv * 3693228386Sjfv * Sets the I2C data bit 3694228386Sjfv **/ 3695228386Sjfvstatic s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data) 3696228386Sjfv{ 3697228386Sjfv s32 status = E1000_SUCCESS; 3698228386Sjfv 3699228386Sjfv DEBUGFUNC("e1000_set_i2c_data"); 3700228386Sjfv 3701228386Sjfv if (data) 3702228386Sjfv *i2cctl |= E1000_I2C_DATA_OUT; 3703228386Sjfv else 3704228386Sjfv *i2cctl &= ~E1000_I2C_DATA_OUT; 3705228386Sjfv 3706228386Sjfv *i2cctl &= ~E1000_I2C_DATA_OE_N; 3707228386Sjfv *i2cctl |= E1000_I2C_CLK_OE_N; 3708228386Sjfv E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3709228386Sjfv E1000_WRITE_FLUSH(hw); 3710228386Sjfv 3711228386Sjfv /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 3712228386Sjfv usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA); 3713228386Sjfv 3714228386Sjfv *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3715228386Sjfv if (data != e1000_get_i2c_data(i2cctl)) { 3716228386Sjfv status = E1000_ERR_I2C; 3717228386Sjfv DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 3718228386Sjfv } 3719228386Sjfv 3720228386Sjfv return status; 3721228386Sjfv} 3722228386Sjfv 3723228386Sjfv/** 3724228386Sjfv * e1000_get_i2c_data - Reads the I2C SDA data bit 3725228386Sjfv * @hw: pointer to hardware structure 3726228386Sjfv * @i2cctl: Current value of I2CCTL register 3727228386Sjfv * 3728228386Sjfv * Returns the I2C data bit value 3729228386Sjfv **/ 3730228386Sjfvstatic bool e1000_get_i2c_data(u32 *i2cctl) 3731228386Sjfv{ 3732228386Sjfv bool data; 3733228386Sjfv 3734228386Sjfv DEBUGFUNC("e1000_get_i2c_data"); 3735228386Sjfv 3736228386Sjfv if (*i2cctl & E1000_I2C_DATA_IN) 3737228386Sjfv data = 1; 3738228386Sjfv else 3739228386Sjfv data = 0; 3740228386Sjfv 3741228386Sjfv return data; 3742228386Sjfv} 3743228386Sjfv 3744228386Sjfv/** 3745228386Sjfv * e1000_i2c_bus_clear - Clears the I2C bus 3746228386Sjfv * @hw: pointer to hardware structure 3747228386Sjfv * 3748228386Sjfv * Clears the I2C bus by sending nine clock pulses. 3749228386Sjfv * Used when data line is stuck low. 3750228386Sjfv **/ 3751228386Sjfvvoid e1000_i2c_bus_clear(struct e1000_hw *hw) 3752228386Sjfv{ 3753228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3754228386Sjfv u32 i; 3755228386Sjfv 3756228386Sjfv DEBUGFUNC("e1000_i2c_bus_clear"); 3757228386Sjfv 3758228386Sjfv e1000_i2c_start(hw); 3759228386Sjfv 3760228386Sjfv e1000_set_i2c_data(hw, &i2cctl, 1); 3761228386Sjfv 3762228386Sjfv for (i = 0; i < 9; i++) { 3763228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3764228386Sjfv 3765228386Sjfv /* Min high period of clock is 4us */ 3766228386Sjfv usec_delay(E1000_I2C_T_HIGH); 3767228386Sjfv 3768228386Sjfv e1000_lower_i2c_clk(hw, &i2cctl); 3769228386Sjfv 3770228386Sjfv /* Min low period of clock is 4.7us*/ 3771228386Sjfv usec_delay(E1000_I2C_T_LOW); 3772228386Sjfv } 3773228386Sjfv 3774228386Sjfv e1000_i2c_start(hw); 3775228386Sjfv 3776228386Sjfv /* Put the i2c bus back to default state */ 3777228386Sjfv e1000_i2c_stop(hw); 3778228386Sjfv} 3779228386Sjfv 3780