Searched refs:base (Results 26 - 50 of 6511) sorted by relevance

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/linux-master/arch/sparc/kernel/
H A Dkstack.h13 unsigned long base = (unsigned long) tp; local
19 if (sp >= (base + sizeof(struct thread_info)) &&
20 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf)))
24 base = (unsigned long) hardirq_stack[tp->cpu];
25 if (sp >= base &&
26 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf)))
28 base = (unsigned long) softirq_stack[tp->cpu];
29 if (sp >= base &&
30 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf)))
39 unsigned long base local
[all...]
/linux-master/sound/soc/sunxi/
H A Dsun8i-adda-pr-regmap.h7 void __iomem *base);
H A Dsun8i-adda-pr-regmap.c18 #define ADDA_PR 0x0 /* PRCM base + 0x1c0 */
31 void __iomem *base = (void __iomem *)context; local
35 writel(readl(base) | ADDA_PR_RESET, base);
38 writel(readl(base) & ~ADDA_PR_WRITE, base); local
41 tmp = readl(base);
44 writel(tmp, base);
47 *val = readl(base) & ADDA_PR_DATA_OUT_MASK;
54 void __iomem *base local
76 writel(readl(base) & ~ADDA_PR_WRITE, base); local
92 sun8i_adda_pr_regmap_init(struct device *dev, void __iomem *base) argument
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/linux-master/arch/alpha/kernel/
H A Dpc873xx.c13 static unsigned int base, model; variable
18 return base;
26 static unsigned char __init pc873xx_read(unsigned int base, int reg) argument
28 outb(reg, base);
29 return inb(base + 1);
32 static void __init pc873xx_write(unsigned int base, int reg, unsigned char data) argument
37 outb(reg, base);
38 outb(data, base + 1);
39 outb(data, base + 1); /* Must be written twice */
47 while ((base
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/linux-master/tools/testing/selftests/rcutorture/bin/
H A Dconfig_override.sh4 # config_override.sh base override
6 # Combines base and override, removing any Kconfig options from base
14 base=$1
15 if test -r $base
19 echo Base file $base unreadable!!!
46 sh $T/script < $base
/linux-master/drivers/gpu/drm/xe/regs/
H A Dxe_gsc_regs.h19 #define HECI_H_CSR(base) XE_REG((base) + 0x4)
30 #define HECI_FWSTS1(base) XE_REG((base) + 0xc40)
35 #define HECI_FWSTS5(base) XE_REG((base) + 0xc68)
38 #define HECI_H_GS1(base) XE_REG((base) + 0xc4c)
/linux-master/arch/csky/include/asm/
H A Dvdso.h16 #define VDSO_SYMBOL(base, name) \
19 (void __user *)((unsigned long)(base) + __vdso_##name); \
/linux-master/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_20nm.c13 void __iomem *base = phy->base; local
15 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0,
17 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1,
19 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2,
22 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3,
24 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4,
26 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5,
28 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6,
30 dsi_phy_write(base
45 void __iomem *base = phy->reg_base; local
72 void __iomem *base = phy->base; local
[all...]
/linux-master/drivers/clk/imx/
H A Dclk-imx6sll.c82 void __iomem *base; local
102 base = of_iomap(np, 0);
104 WARN_ON(!base);
107 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0));
108 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10));
109 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20));
110 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30));
111 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70));
112 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0));
113 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base
[all...]
H A Dclk-imx6sx.c123 void __iomem *base; local
148 base = of_iomap(np, 0);
149 WARN_ON(!base);
152 hws[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
153 hws[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
154 hws[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
155 hws[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
156 hws[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
157 hws[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
158 hws[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base
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H A Dclk-imx8ulp.c53 void __iomem *base; member in struct:pcc_reset_dev
91 val = readl(pcc_reset->base + offset);
93 writel(val, pcc_reset->base + offset);
109 val = readl(pcc_reset->base + offset);
111 writel(val, pcc_reset->base + offset);
123 static int imx8ulp_pcc_reset_init(struct platform_device *pdev, void __iomem *base, argument
134 pcc_reset->base = base;
150 void __iomem *base; local
163 base
234 void __iomem *base; local
316 void __iomem *base; local
399 void __iomem *base; local
454 void __iomem *base; local
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H A Dclk-imx6ul.c131 void __iomem *base; local
151 base = of_iomap(np, 0);
153 WARN_ON(!base);
155 hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
156 hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
157 hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
158 hws[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
159 hws[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
160 hws[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
161 hws[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base
[all...]
H A Dclk-imx7d.c383 void __iomem *base; local
398 base = of_iomap(np, 0);
399 WARN_ON(!base);
402 hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
403 hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
404 hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
405 hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
406 hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
407 hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
409 hws[IMX7D_PLL_ARM_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base
[all...]
/linux-master/arch/arm/plat-orion/include/plat/
H A Dpcie.h16 u32 orion_pcie_dev_id(void __iomem *base);
17 u32 orion_pcie_rev(void __iomem *base);
18 int orion_pcie_link_up(void __iomem *base);
19 int orion_pcie_x4_mode(void __iomem *base);
20 int orion_pcie_get_local_bus_nr(void __iomem *base);
21 void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
22 void orion_pcie_reset(void __iomem *base);
23 void orion_pcie_setup(void __iomem *base);
24 int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
26 int orion_pcie_rd_conf_tlp(void __iomem *base, struc
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/linux-master/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-hw-exynos4.c16 void exynos4_jpeg_sw_reset(void __iomem *base) argument
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG);
22 base + EXYNOS4_JPEG_CNTL_REG);
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG);
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG);
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG);
32 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) argument
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG);
41 base + EXYNOS4_JPEG_CNTL_REG);
45 base
52 __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt, unsigned int version) argument
136 __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt, unsigned int version) argument
169 exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version) argument
183 exynos4_jpeg_get_int_status(void __iomem *base) argument
188 exynos4_jpeg_get_fifo_status(void __iomem *base) argument
193 exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value) argument
207 exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value) argument
219 exynos4_jpeg_set_stream_buf_address(void __iomem *base, unsigned int address) argument
225 exynos4_jpeg_set_stream_size(void __iomem *base, unsigned int x_value, unsigned int y_value) argument
233 exynos4_jpeg_set_frame_buf_address(void __iomem *base, struct s5p_jpeg_addr *exynos4_jpeg_addr) argument
241 exynos4_jpeg_set_encode_tbl_select(void __iomem *base, enum exynos4_jpeg_img_quality_level level) argument
255 exynos4_jpeg_set_dec_components(void __iomem *base, int n) argument
265 exynos4_jpeg_select_dec_q_tbl(void __iomem *base, char c, char x) argument
275 exynos4_jpeg_select_dec_h_tbl(void __iomem *base, char c, char x) argument
285 exynos4_jpeg_set_encode_hoff_cnt(void __iomem *base, unsigned int fmt) argument
293 exynos4_jpeg_get_stream_size(void __iomem *base) argument
298 exynos4_jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size) argument
303 exynos4_jpeg_get_frame_size(void __iomem *base, unsigned int *width, unsigned int *height) argument
312 exynos4_jpeg_get_frame_fmt(void __iomem *base) argument
318 exynos4_jpeg_set_timer_count(void __iomem *base, unsigned int size) argument
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/linux-master/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt2701.c53 void __iomem *base = hdmi_phy->regs; local
55 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
56 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
57 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
58 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
60 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);
61 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
62 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
64 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
65 mtk_phy_set_bits(base
75 void __iomem *base = hdmi_phy->regs; local
103 void __iomem *base = hdmi_phy->regs; local
179 void __iomem *base = hdmi_phy->regs; local
199 void __iomem *base = hdmi_phy->regs; local
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/linux-master/include/linux/
H A Dkstrtox.h9 int __must_check _kstrtoul(const char *s, unsigned int base, unsigned long *res);
10 int __must_check _kstrtol(const char *s, unsigned int base, long *res);
12 int __must_check kstrtoull(const char *s, unsigned int base, unsigned long long *res);
13 int __must_check kstrtoll(const char *s, unsigned int base, long long *res);
20 * @base: The number base to use. The maximum supported base is 16. If base is
21 * given as 0, then the base of the string is automatically detected with the
30 static inline int __must_check kstrtoul(const char *s, unsigned int base, unsigne argument
58 kstrtol(const char *s, unsigned int base, long *res) argument
74 kstrtou64(const char *s, unsigned int base, u64 *res) argument
79 kstrtos64(const char *s, unsigned int base, s64 *res) argument
84 kstrtou32(const char *s, unsigned int base, u32 *res) argument
89 kstrtos32(const char *s, unsigned int base, s32 *res) argument
112 kstrtou64_from_user(const char __user *s, size_t count, unsigned int base, u64 *res) argument
117 kstrtos64_from_user(const char __user *s, size_t count, unsigned int base, s64 *res) argument
122 kstrtou32_from_user(const char __user *s, size_t count, unsigned int base, u32 *res) argument
127 kstrtos32_from_user(const char __user *s, size_t count, unsigned int base, s32 *res) argument
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/linux-master/arch/powerpc/boot/
H A Dstdlib.h5 unsigned long long int strtoull(const char *ptr, char **end, int base);
/linux-master/arch/mips/alchemy/common/
H A Dvss.c25 void __iomem *base = (void __iomem *)VSS_ADDR(block); local
27 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */
34 __raw_writel(0x01, base + VSS_FTR);
36 __raw_writel(0x03, base + VSS_FTR);
38 __raw_writel(0x07, base + VSS_FTR);
40 __raw_writel(0x0f, base + VSS_FTR);
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */
49 __raw_writel(0x1f, base
56 void __iomem *base = (void __iomem *)VSS_ADDR(block); local
[all...]
H A Dusb.c6 * area. Au1550 has OHCI on different base address. No need to handle
98 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) argument
102 r = __raw_readl(base + USB_DWC_CTRL2);
103 s = __raw_readl(base + USB_DWC_CTRL3);
112 __raw_writel(r, base + USB_DWC_CTRL2);
118 __raw_writel(r, base + USB_DWC_CTRL2);
123 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) argument
128 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */
131 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */
134 __raw_writel(r, base
163 __au1300_ehci_control(void __iomem *base, int enable) argument
204 __au1300_udc_control(void __iomem *base, int enable) argument
235 __au1300_otg_control(void __iomem *base, int enable) argument
267 void __iomem *base = local
295 void __iomem *base = local
316 __au1200_ohci_control(void __iomem *base, int enable) argument
330 __au1200_ehci_control(void __iomem *base, int enable) argument
346 __au1200_udc_control(void __iomem *base, int enable) argument
362 void __iomem *base = local
385 void __iomem *base = local
394 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); local
427 void __iomem *base = (void __iomem *)KSEG1ADDR(rb); local
514 void __iomem *base = (void __iomem *)KSEG1ADDR(br); local
531 void __iomem *base = local
551 void __iomem *base = local
[all...]
/linux-master/include/clocksource/
H A Dpxa.h11 extern void pxa_timer_nodt_init(int irq, void __iomem *base);
/linux-master/lib/math/
H A Dint_pow.c13 * int_pow - computes the exponentiation of the given base and exponent
14 * @base: base which will be raised to the given power
17 * Computes: pow(base, exp), i.e. @base raised to the @exp power
19 u64 int_pow(u64 base, unsigned int exp) argument
25 result *= base;
27 base *= base;
/linux-master/tools/include/linux/
H A Dring_buffer.h51 static inline u64 ring_buffer_read_head(struct perf_event_mmap_page *base) argument
59 return smp_load_acquire(&base->data_head);
61 u64 head = READ_ONCE(base->data_head);
68 static inline void ring_buffer_write_tail(struct perf_event_mmap_page *base, argument
71 smp_store_release(&base->data_tail, tail);
/linux-master/drivers/clocksource/
H A Dtimer-gx6605s.c28 void __iomem *base = timer_of_base(to_timer_of(ce)); local
30 writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
31 writel_relaxed(0, base + TIMER_INI);
40 void __iomem *base = timer_of_base(to_timer_of(ce)); local
43 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
47 base + TIMER_CONFIG);
55 void __iomem *base = timer_of_base(to_timer_of(ce)); local
58 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
61 writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
62 writel_relaxed(GX6605S_CONTRL_START, base
69 void __iomem *base = timer_of_base(to_timer_of(ce)); local
96 void __iomem *base; local
103 gx6605s_clkevt_init(void __iomem *base) argument
112 gx6605s_clksrc_init(void __iomem *base) argument
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Dbusgf119.c24 #define gf119_i2c_bus(p) container_of((p), struct gf119_i2c_bus, base)
28 struct nvkm_i2c_bus base; member in struct:gf119_i2c_bus
33 gf119_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) argument
35 struct gf119_i2c_bus *bus = gf119_i2c_bus(base);
36 struct nvkm_device *device = bus->base.pad->i2c->subdev.device;
41 gf119_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) argument
43 struct gf119_i2c_bus *bus = gf119_i2c_bus(base);
44 struct nvkm_device *device = bus->base.pad->i2c->subdev.device;
49 gf119_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) argument
51 struct gf119_i2c_bus *bus = gf119_i2c_bus(base);
57 gf119_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) argument
65 gf119_i2c_bus_init(struct nvkm_i2c_bus *base) argument
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1234567891011>>