alchemy/common/usb.c

6  *	    area. Au1550 has OHCI on different base address. No need to handle
98 static inline void __au1300_usb_phyctl(void __iomem *base, int enable)
102 	r = __raw_readl(base + USB_DWC_CTRL2);
103 	s = __raw_readl(base + USB_DWC_CTRL3);
112 		__raw_writel(r, base + USB_DWC_CTRL2);
118 		__raw_writel(r, base + USB_DWC_CTRL2);
123 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
128 		__raw_writel(1, base + USB_DWC_CTRL7);	/* start OHCI clock */
131 		r = __raw_readl(base + USB_DWC_CTRL3);	/* enable OHCI block */
134 		__raw_writel(r, base + USB_DWC_CTRL3);
137 		__au1300_usb_phyctl(base, enable);	/* power up the PHYs */
139 		r = __raw_readl(base + USB_INT_ENABLE);
141 		__raw_writel(r, base + USB_INT_ENABLE);
145 		__raw_writel(0, base + USB_DWC_CTRL7);
148 		r = __raw_readl(base + USB_INT_ENABLE);
150 		__raw_writel(r, base + USB_INT_ENABLE);
153 		r = __raw_readl(base + USB_DWC_CTRL3);
156 		__raw_writel(r, base + USB_DWC_CTRL3);
159 		__au1300_usb_phyctl(base, enable);
163 static inline void __au1300_ehci_control(void __iomem *base, int enable)
168 		r = __raw_readl(base + USB_DWC_CTRL3);
170 		__raw_writel(r, base + USB_DWC_CTRL3);
173 		r = __raw_readl(base + USB_DWC_CTRL1);
175 		__raw_writel(r, base + USB_DWC_CTRL1);
178 		__au1300_usb_phyctl(base, enable);
180 		r = __raw_readl(base + USB_INT_ENABLE);
182 		__raw_writel(r, base + USB_INT_ENABLE);
185 		r = __raw_readl(base + USB_INT_ENABLE);
187 		__raw_writel(r, base + USB_INT_ENABLE);
190 		r = __raw_readl(base + USB_DWC_CTRL1);
192 		__raw_writel(r, base + USB_DWC_CTRL1);
195 		r = __raw_readl(base + USB_DWC_CTRL3);
197 		__raw_writel(r, base + USB_DWC_CTRL3);
200 		__au1300_usb_phyctl(base, enable);
204 static inline void __au1300_udc_control(void __iomem *base, int enable)
209 		r = __raw_readl(base + USB_DWC_CTRL1);
211 		__raw_writel(r, base + USB_DWC_CTRL1);
214 		__au1300_usb_phyctl(base, enable);
216 		r = __raw_readl(base + USB_INT_ENABLE);
218 		__raw_writel(r, base + USB_INT_ENABLE);
221 		r = __raw_readl(base + USB_INT_ENABLE);
223 		__raw_writel(r, base + USB_INT_ENABLE);
226 		r = __raw_readl(base + USB_DWC_CTRL1);
228 		__raw_writel(r, base + USB_DWC_CTRL1);
231 		__au1300_usb_phyctl(base, enable);
235 static inline void __au1300_otg_control(void __iomem *base, int enable)
239 		r = __raw_readl(base + USB_DWC_CTRL3);
241 		__raw_writel(r, base + USB_DWC_CTRL3);
244 		r = __raw_readl(base + USB_DWC_CTRL1);
246 		__raw_writel(r, base + USB_DWC_CTRL1);
249 		__au1300_usb_phyctl(base, enable);
251 		r = __raw_readl(base + USB_DWC_CTRL1);
253 		__raw_writel(r, base + USB_DWC_CTRL1);
256 		r = __raw_readl(base + USB_DWC_CTRL3);
258 		__raw_writel(r, base + USB_DWC_CTRL3);
261 		__au1300_usb_phyctl(base, enable);
267 	void __iomem *base =
273 		__au1300_ohci_control(base, enable, 0);
276 		__au1300_ohci_control(base, enable, 1);
279 		__au1300_ehci_control(base, enable);
282 		__au1300_udc_control(base, enable);
285 		__au1300_otg_control(base, enable);
295 	void __iomem *base =
303 	__raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */
305 	__raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */
307 	__raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */
309 	__raw_writel(~0, base + USB_INT_STATUS); /* clear int status */
312 	__raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL);
316 static inline void __au1200_ohci_control(void __iomem *base, int enable)
318 	unsigned long r = __raw_readl(base + AU1200_USBCFG);
320 		__raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
324 		__raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
330 static inline void __au1200_ehci_control(void __iomem *base, int enable)
332 	unsigned long r = __raw_readl(base + AU1200_USBCFG);
334 		__raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
340 		__raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
346 static inline void __au1200_udc_control(void __iomem *base, int enable)
348 	unsigned long r = __raw_readl(base + AU1200_USBCFG);
350 		__raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
355 		__raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
362 	void __iomem *base =
367 		__au1200_ohci_control(base, enable);
370 		__au1200_udc_control(base, enable);
373 		__au1200_ehci_control(base, enable);
385 	void __iomem *base =
387 	__raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
394 	void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
395 	unsigned long r = __raw_readl(base);
417 	__raw_writel(r, base);
427 	void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
428 	unsigned long r = __raw_readl(base + creg);
438 		__raw_writel(r | USBHEN_CE, base + creg);
441 		__raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
446 		while (__raw_readl(base + creg),
447 			!(__raw_readl(base + creg) & USBHEN_RD))
450 		__raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
514 	void __iomem *base = (void __iomem *)KSEG1ADDR(br);
517 		alchemy_usb_pmdata[0] = __raw_readl(base + creg);
519 		__raw_writel(0, base + 0x04);
521 		__raw_writel(0, base + creg);
524 		__raw_writel(alchemy_usb_pmdata[0], base + creg);
531 	void __iomem *base =
536 		alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
537 		alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
543 		__raw_writel(alchemy_usb_pmdata[0], base + 0x00);
544 		__raw_writel(alchemy_usb_pmdata[1], base + 0x04);
551 	void __iomem *base =
555 		alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4);
558 		__raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4);