Searched refs:num_entries (Results 26 - 50 of 460) sorted by last modified time

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/linux-master/drivers/gpu/drm/xe/
H A Dxe_migrate.c141 u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level; local
157 num_entries * XE_PAGE_SIZE,
167 map_ofs = (num_entries - num_level) * XE_PAGE_SIZE;
170 for (i = 0, level = 0; i < num_entries; level++) {
238 for (i = 0; i < num_entries - num_level; i++) {
H A Dxe_lmtt.c58 unsigned int num_entries = level ? lmtt->ops->lmtt_pte_num(level) : 0; local
63 pt = kzalloc(struct_size(pt, entries, num_entries), GFP_KERNEL);
116 unsigned int num_entries = lmtt->ops->lmtt_pte_num(pd->level); local
120 for (n = 0; n < num_entries; n++)
241 unsigned int num_entries = pd->level ? lmtt->ops->lmtt_pte_num(pd->level) : 0; local
245 for (i = 0; i < num_entries; i++) {
/linux-master/drivers/gpu/drm/nouveau/dispnv50/
H A Dcrc.c137 while (crc->entry_idx < func->num_entries) {
/linux-master/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_capture.c413 struct guc_mmio_reg *ptr, u16 num_entries)
428 for (i = 0; i < num_entries && i < match->num_regs; ++i) {
437 for (i = match->num_regs, j = 0; i < num_entries &&
446 if (i < num_entries)
447 guc_dbg(guc, "Got short capture reglist init: %d out %d.\n", i, num_entries);
412 guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid, struct guc_mmio_reg *ptr, u16 num_entries) argument
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_ggtt.c330 struct sg_table *pages, u32 num_entries,
342 if (!num_entries)
352 while (num_entries) {
359 u32 n_ptes = min_t(u32, 511, num_entries);
417 num_entries -= n_ptes;
554 unsigned int num_entries = length / I915_GTT_PAGE_SIZE; local
561 if (WARN(num_entries > max_entries,
563 first_entry, num_entries, max_entries))
564 num_entries = max_entries;
566 for (i = 0; i < num_entries;
329 gen8_ggtt_bind_ptes(struct i915_ggtt *ggtt, u32 offset, struct sg_table *pages, u32 num_entries, const gen8_pte_t pte) argument
575 unsigned int num_entries = length / I915_GTT_PAGE_SIZE; local
724 unsigned int num_entries = length / I915_GTT_PAGE_SIZE; local
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H A Dintel_execlists_submission.c1821 const u8 num_entries = execlists->csb_size; local
1885 if (++head == num_entries)
2013 drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
H A Dintel_engine_cs.c2138 const u8 num_entries = execlists->csb_size; local
2154 read, write, num_entries);
2156 if (read >= num_entries)
2158 if (write >= num_entries)
2161 write += num_entries;
2163 idx = ++read % num_entries;
/linux-master/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c2511 int num_entries, int ignore_idx)
2515 for (i = 0; i < num_entries; i++) {
2509 skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, const struct skl_ddb_entry *entries, int num_entries, int ignore_idx) argument
H A Dskl_watermark.h40 int num_entries, int ignore_idx);
H A Dintel_dmc.c293 u32 num_entries; member in struct:intel_package_header
660 * Search fw_info table for dmc_offset to find firmware binary: num_entries is
665 unsigned int num_entries,
673 for (i = 0; i < num_entries; i++) {
853 u32 num_entries, max_entries; local
883 num_entries = package_header->num_entries;
884 if (WARN_ON(package_header->num_entries > max_entries))
885 num_entries = max_entries;
889 dmc_set_fw_offset(dmc, fw_info, num_entries, s
663 dmc_set_fw_offset(struct intel_dmc *dmc, const struct intel_fw_info *fw_info, unsigned int num_entries, const struct stepping_info *si, u8 package_ver) argument
[all...]
H A Dintel_ddi_buf_trans.c32 .num_entries = ARRAY_SIZE(_hsw_trans_dp),
49 .num_entries = ARRAY_SIZE(_hsw_trans_fdi),
70 .num_entries = ARRAY_SIZE(_hsw_trans_hdmi),
88 .num_entries = ARRAY_SIZE(_bdw_trans_edp),
105 .num_entries = ARRAY_SIZE(_bdw_trans_dp),
122 .num_entries = ARRAY_SIZE(_bdw_trans_fdi),
141 .num_entries = ARRAY_SIZE(_bdw_trans_hdmi),
160 .num_entries = ARRAY_SIZE(_skl_trans_dp),
178 .num_entries = ARRAY_SIZE(_skl_u_trans_dp),
196 .num_entries
1140 intel_get_buf_trans(const struct intel_ddi_buf_trans *trans, int *num_entries) argument
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/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c5849 for (k = 0; k < table->num_entries; k++)
5860 for (k = 0; k < table->num_entries; k++) {
5874 for (k = 0; k < table->num_entries; k++)
5884 for(k = 0; k < table->num_entries; k++)
5959 for (j = 1; j < table->num_entries; j++) {
5986 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5993 for (i = 0; i < table->num_entries; i++) {
6001 si_table->num_entries = table->num_entries;
6078 u32 num_entries, u3
6076 si_convert_mc_registers(const struct si_mc_reg_entry *entry, SMC_SIslands_MCRegisterSet *data, u32 num_entries, u32 valid_flag) argument
[all...]
H A Dkv_dpm.c86 for (i = 0; i < vid_mapping_table->num_entries; i++) {
90 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
109 for (i = 0; i < vid_mapping_table->num_entries; i++) {
114 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
190 vid_mapping_table->num_entries = i;
/linux-master/drivers/gpu/drm/amd/display/modules/color/
H A Dcolor_gamma.c621 const uint32_t max_number = ramp->num_entries + 3;
728 if (index_left >= ramp->num_entries + 3) {
733 if (index_right >= ramp->num_entries + 3) {
1284 struct pwl_float_data *rgb_last = rgb + ramp->num_entries - 1;
1296 } while (i != ramp->num_entries);
1310 } while (i != ramp->num_entries);
1349 for (i = 0 ; i < ramp->num_entries; i++) {
1374 for (i = 0 ; i < ramp->num_entries; i++) {
1647 max_entries += ramp->num_entries;
2024 rgb_user = kvcalloc(ramp->num_entries
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c2155 num_uclk_states = bw_params->clk_table.num_entries;
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h135 unsigned int num_entries; /* highest populated dpm level for back compatibility */ member in struct:clk_limit_table
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c1730 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c1170 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
/linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c859 for (i = 0; i < gamma->num_entries; i++) {
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_wrapper.c297 static void copy_dummy_pstate_table(struct dummy_pstate_entry *dest, struct dummy_pstate_entry *src, unsigned int num_entries) argument
299 for (int i = 0; i < num_entries; i++) {
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c278 ASSERT(clk_table->num_entries);
281 for (i = 0; i < clk_table->num_entries; ++i) {
288 for (i = 0; i < clk_table->num_entries; i++) {
298 if (clk_table->num_entries == 1) {
307 if (clk_table->num_entries == 1 &&
350 if (clk_table->num_entries)
351 dcn3_51_soc.num_states = clk_table->num_entries;
387 if (clk_table->num_entries > 2) {
389 for (i = 0; i < clk_table->num_entries; i++) {
391 clk_table->num_entries;
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c244 ASSERT(clk_table->num_entries);
247 for (i = 0; i < clk_table->num_entries; ++i) {
254 for (i = 0; i < clk_table->num_entries; i++) {
264 if (clk_table->num_entries == 1) {
273 if (clk_table->num_entries == 1 &&
316 if (clk_table->num_entries)
317 dcn3_5_soc.num_states = clk_table->num_entries;
353 if (clk_table->num_entries > 2) {
355 for (i = 0; i < clk_table->num_entries; i++) {
357 clk_table->num_entries;
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c418 unsigned int *num_entries,
426 if (*num_entries == 0) {
428 (*num_entries)++;
432 if (index >= *num_entries)
436 for (i = *num_entries; i > index; i--)
440 (*num_entries)++;
2635 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, argument
2640 if (*num_entries == 0)
2643 for (i = index; i < *num_entries - 1; i++) {
2646 memset(&table[--(*num_entries)],
417 insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, struct _vcs_dpi_voltage_scaling_st *entry) argument
2699 sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) argument
2734 remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) argument
2781 build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c205 ASSERT(clk_table->num_entries);
208 for (i = 0; i < clk_table->num_entries; ++i) {
215 for (i = 0; i < clk_table->num_entries; i++) {
223 if (clk_table->num_entries == 1) {
232 if (clk_table->num_entries == 1 &&
256 for (i = 0; i < clk_table->num_entries; i++)
258 if (clk_table->num_entries) {
259 dcn3_14_soc.num_states = clk_table->num_entries;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c607 ASSERT(clk_table->num_entries);
610 for (i = 0; i < clk_table->num_entries; ++i) {
617 for (i = 0; i < clk_table->num_entries; i++) {
650 if (clk_table->num_entries) {
651 dcn3_1_soc.num_states = clk_table->num_entries;
683 ASSERT(clk_table->num_entries);
686 for (i = 0; i < clk_table->num_entries; ++i) {
693 for (i = 0; i < clk_table->num_entries; i++) {
712 dcn3_15_soc.num_states = clk_table->num_entries;
746 ASSERT(clk_table->num_entries);
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