/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_hubbub.c | 277 struct dc_surface_dcc_cap *output) 286 memset(output, 0, sizeof(*output)); 343 output->grph.rgb.max_uncompressed_blk_size = 256; 344 output->grph.rgb.max_compressed_blk_size = 256; 345 output->grph.rgb.independent_64b_blks = false; 346 output->grph.rgb.dcc_controls.dcc_256_256_unconstrained = 1; 347 output->grph.rgb.dcc_controls.dcc_256_128_128 = 1; 350 output->grph.rgb.max_uncompressed_blk_size = 128; 351 output 275 hubbub3_get_dcc_compression_cap(struct hubbub *hubbub, const struct dc_dcc_surface_param *input, struct dc_surface_dcc_cap *output) argument [all...] |
H A D | dcn30_hubbub.h | 123 struct dc_surface_dcc_cap *output);
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/ |
H A D | dcn31_hubbub.c | 805 struct dc_surface_dcc_cap *output) 813 memset(output, 0, sizeof(*output)); 870 output->grph.rgb.max_uncompressed_blk_size = 256; 871 output->grph.rgb.max_compressed_blk_size = 256; 872 output->grph.rgb.independent_64b_blks = false; 873 output->grph.rgb.dcc_controls.dcc_256_256_unconstrained = 1; 874 output->grph.rgb.dcc_controls.dcc_256_128_128 = 1; 877 output->grph.rgb.max_uncompressed_blk_size = 128; 878 output 803 hubbub31_get_dcc_compression_cap(struct hubbub *hubbub, const struct dc_dcc_surface_param *input, struct dc_surface_dcc_cap *output) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
H A D | dcn_calc_auto.c | 193 if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) { 196 else if (v->output[k] == dcn_bw_writeback) { 242 if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0 > (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) { 245 else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) >dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) { 263 if (v->output[k] == dcn_bw_dp && v->dsc_capability == dcn_bw_yes) { 277 if (v->output[k] == dcn_bw_hdmi) { 291 else if (v->output[k] == dcn_bw_dp) { 301 if (v->required_phyclk[k] > v->phyclk_per_state[i] || (v->output[k] == dcn_bw_hdmi && v->required_phyclk[k] > 600.0)) { 310 if (v->output[k] == dcn_bw_writeback) { 1329 if (v->output[ [all...] |
H A D | dcn_calcs.c | 502 input->dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp; 924 * source size because here we are only interested in if the output 1032 v->output[input_idx] = pipe->stream->signal == 1035 if (v->output[input_idx] == dcn_bw_hdmi) {
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/linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | display_mode_core.c | 936 // dscc - output cdc fifo 942 // dscc - output serializer 957 // dscc - output cdc fifo 961 // dscc - output serializer 976 // dscc - output cdc fifo 978 // dscc - output serializer 1093 dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", __func__, s->Tdmbf); 1264 dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", __func__, s->Tdmbf); 2694 display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k]; 5446 } else { // output i [all...] |
H A D | display_mode_core_structs.h | 560 /// @brief structure that represents the output stream 568 dml_float_t OutputBpp[__DML_NUM_PLANES__]; //< brief Use by mode_programming to specify a output bpp; user can use the output from mode_support (support.OutputBpp) 599 dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 606 /// Describe how to display a surface in multi-plane setup and output to different output and writeback using the specified timgin 611 struct dml_output_cfg_st output; member in struct:dml_display_cfg_st 644 dml_bool_t UseMinimumRequiredDCFCLK; //<brief When set the mode_check stage will figure the min DCFCLK freq to support the given display configuration. User can tell use the output DCFCLK for mode programming. 734 dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 1837 /// @brief Represent the overall soc/ip enviroment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output [all...] |
H A D | dml2_translation_helper.c | 1099 populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context); 1156 populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_plane_location, context->streams[i], current_pipe_context);
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H A D | dml2_wrapper.c | 179 p->new_display_config->output.OutputDisabled[new_timing_index] = true; 208 p->cur_display_config->output.OutputEncoder[0], p->cur_mode_support_info->DSCEnabled[0]) - 1; 589 /* Call map dc pipes to map the pipes based on the DML output. For correctly determining if recalculation
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
H A D | dcn_calcs.h | 190 enum dcn_bw_defs output[number_of_planes_minus_one + 1]; member in struct:dcn_bw_internal_vars
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | dchubbub.h | 142 struct dc_surface_dcc_cap *output); 187 * the graphics output. One of the main features of this component is
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
H A D | dcn10_resource.c | 1123 struct dc_surface_dcc_cap *output) 1128 output); 1598 "DC: failed to create output pixel processor!\n"); 1121 dcn10_get_dcc_compression_cap(const struct dc *dc, const struct dc_dcc_surface_param *input, struct dc_surface_dcc_cap *output) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
H A D | dcn20_resource.c | 2190 struct dc_surface_dcc_cap *output) 2195 output); 2679 "DC: failed to create output pixel processor!\n"); 2188 dcn20_get_dcc_compression_cap(const struct dc *dc, const struct dc_dcc_surface_param *input, struct dc_surface_dcc_cap *output) argument
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H A D | dcn20_resource.h | 78 struct dc_surface_dcc_cap *output);
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
H A D | dcn201_resource.c | 1026 struct dc_surface_dcc_cap *output) 1031 output); 1227 "DC: failed to create output pixel processor!\n"); 1024 dcn201_get_dcc_compression_cap(const struct dc *dc, const struct dc_dcc_surface_param *input, struct dc_surface_dcc_cap *output) argument
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/linux-master/drivers/gpu/drm/amd/display/dmub/inc/ |
H A D | dmub_cmd.h | 4193 struct dmub_cmd_edid_cea_output { /**< output with results */ 4199 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ member in union:dmub_rb_cmd_edid_cea::dmub_cmd_edid_cea_data 4212 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 4231 struct dmub_cmd_cable_id_output output; /**< Output */ member in union:dmub_rb_cmd_get_usbc_cable_id::dmub_cmd_cable_id_data 4232 uint8_t output_raw; /**< Raw data output */ 4821 * @brief Copies output data from in/out commands into the given command.
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/linux-master/drivers/gpu/drm/amd/display/modules/color/ |
H A D | color_gamma.c | 854 struct fixed31_32 output; local 876 output = pq_table[i]; 879 compute_pq(x, &output); 883 if (dc_fixpt_lt(output, dc_fixpt_zero)) 884 output = dc_fixpt_zero; 886 rgb->r = output; 887 rgb->g = output; 888 rgb->b = output; 900 struct fixed31_32 output; local 911 output 1062 struct fixed31_32 output; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/modules/hdcp/ |
H A D | hdcp.c | 130 struct mod_hdcp_output *output) 140 callback_in_ms(0, output); 141 set_state_id(hdcp, output, D2_A0_DETERMINE_RX_HDCP_CAPABLE); 143 callback_in_ms(0, output); 144 set_state_id(hdcp, output, D1_A0_DETERMINE_RX_HDCP_CAPABLE); 146 callback_in_ms(0, output); 147 set_state_id(hdcp, output, HDCP_CP_NOT_DESIRED); 148 set_auth_complete(hdcp, output); 152 callback_in_ms(0, output); 153 set_state_id(hdcp, output, H2_A0_KNOWN_HDCP2_CAPABLE_R 127 transition(struct mod_hdcp *hdcp, struct mod_hdcp_event_context *event_ctx, union mod_hdcp_transition_input *input, struct mod_hdcp_output *output) argument 188 reset_authentication(struct mod_hdcp *hdcp, struct mod_hdcp_output *output) argument 234 reset_connection(struct mod_hdcp *hdcp, struct mod_hdcp_output *output) argument 292 struct mod_hdcp_output output; local 307 struct mod_hdcp_output output; local 319 mod_hdcp_add_display(struct mod_hdcp *hdcp, struct mod_hdcp_link *link, struct mod_hdcp_display *display, struct mod_hdcp_output *output) argument 378 mod_hdcp_remove_display(struct mod_hdcp *hdcp, uint8_t index, struct mod_hdcp_output *output) argument 421 mod_hdcp_update_display(struct mod_hdcp *hdcp, uint8_t index, struct mod_hdcp_link_adjustment *link_adjust, struct mod_hdcp_display_adjustment *display_adjust, struct mod_hdcp_output *output) argument 522 mod_hdcp_reset_connection(struct mod_hdcp *hdcp, struct mod_hdcp_output *output) argument 535 mod_hdcp_process_event(struct mod_hdcp *hdcp, enum mod_hdcp_event event, struct mod_hdcp_output *output) argument [all...] |
H A D | hdcp.h | 302 struct mod_hdcp_output *output); 306 struct mod_hdcp_output *output); 318 struct mod_hdcp_output *output); 322 struct mod_hdcp_output *output); 414 struct mod_hdcp_output *output, uint8_t id) 419 output->callback_stop = 1; 420 output->watchdog_timer_stop = 1; 421 HDCP_NEXT_STATE_TRACE(hdcp, id, output); 484 struct mod_hdcp_output *output) 486 output 413 set_state_id(struct mod_hdcp *hdcp, struct mod_hdcp_output *output, uint8_t id) argument 482 fail_and_restart_in_ms(uint16_t time, enum mod_hdcp_status *status, struct mod_hdcp_output *output) argument 493 callback_in_ms(uint16_t time, struct mod_hdcp_output *output) argument 499 set_watchdog_in_ms(struct mod_hdcp *hdcp, uint16_t time, struct mod_hdcp_output *output) argument 506 set_auth_complete(struct mod_hdcp *hdcp, struct mod_hdcp_output *output) argument [all...] |
H A D | hdcp1_transition.c | 31 struct mod_hdcp_output *output) 41 callback_in_ms(500, output); 45 callback_in_ms(0, output); 46 set_state_id(hdcp, output, H1_A1_EXCHANGE_KSVS); 52 fail_and_restart_in_ms(0, &status, output); 60 fail_and_restart_in_ms(0, &status, output); 63 callback_in_ms(300, output); 64 set_state_id(hdcp, output, 70 fail_and_restart_in_ms(0, &status, output); 79 fail_and_restart_in_ms(1000, &status, output); 28 mod_hdcp_hdcp1_transition(struct mod_hdcp *hdcp, struct mod_hdcp_event_context *event_ctx, struct mod_hdcp_transition_input_hdcp1 *input, struct mod_hdcp_output *output) argument 151 mod_hdcp_hdcp1_dp_transition(struct mod_hdcp *hdcp, struct mod_hdcp_event_context *event_ctx, struct mod_hdcp_transition_input_hdcp1 *input, struct mod_hdcp_output *output) argument [all...] |
H A D | hdcp2_transition.c | 31 struct mod_hdcp_output *output) 42 callback_in_ms(0, output); 43 set_state_id(hdcp, output, HDCP_INITIALIZED); 45 callback_in_ms(0, output); 46 set_state_id(hdcp, output, H2_A1_SEND_AKE_INIT); 54 fail_and_restart_in_ms(0, &status, output); 57 fail_and_restart_in_ms(0, &status, output); 60 set_watchdog_in_ms(hdcp, 100, output); 61 callback_in_ms(0, output); 62 set_state_id(hdcp, output, H2_A1_VALIDATE_AKE_CER 28 mod_hdcp_hdcp2_transition(struct mod_hdcp *hdcp, struct mod_hdcp_event_context *event_ctx, struct mod_hdcp_transition_input_hdcp2 *input, struct mod_hdcp_output *output) argument 369 mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp, struct mod_hdcp_event_context *event_ctx, struct mod_hdcp_transition_input_hdcp2 *input, struct mod_hdcp_output *output) argument [all...] |
H A D | hdcp_log.h | 73 #define HDCP_NEXT_STATE_TRACE(hdcp, id, output) do { \ 74 if (output->watchdog_timer_needed) \ 78 mod_hdcp_state_id_to_str(id), output->watchdog_timer_delay); \
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/linux-master/drivers/gpu/drm/amd/display/modules/inc/ |
H A D | mod_hdcp.h | 222 /* output flags from module requesting timer operations */ 291 struct mod_hdcp_output *output); 295 uint8_t index, struct mod_hdcp_output *output); 302 struct mod_hdcp_output *output); 310 struct mod_hdcp_output *output); 314 enum mod_hdcp_event event, struct mod_hdcp_output *output);
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/linux-master/drivers/gpu/drm/amd/include/ |
H A D | kgd_pp_interface.h | 399 struct amd_pp_simple_clock_info *output);
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/ |
H A D | amd_powerplay.c | 1049 struct amd_pp_simple_clock_info *output) 1053 if (!hwmgr || !hwmgr->pm_en || !output) 1056 return phm_get_dal_power_level(hwmgr, output); 1048 pp_get_display_power_level(void *handle, struct amd_pp_simple_clock_info *output) argument
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