Searched refs:clock (Results 176 - 200 of 1865) sorted by relevance

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/linux-master/drivers/gpu/drm/loongson/
H A Dlsdc_pixpll.h27 * +---- bypass (bypass above software configurable clock if set) ----+
31 * sel_out: PLL clock output selector(enable).
33 * If sel_out == 1, then enable output clock (turn On);
34 * If sel_out == 0, then disable output clock (turn Off);
55 unsigned int clock,
H A Dlsdc_pixpll.c22 unsigned div_out : 7; /* 6 : 0 Output clock divider */
28 unsigned div_ref : 7; /* 38 : 32 Input clock divider */
45 unsigned int clock; /* kHz */ member in struct:clk_to_pixpll_parms_lookup_t
144 * @clock: the desired output pixel clock, the unit is kHz
150 unsigned int clock,
160 if (clock == pt->clock) {
169 drm_dbg_kms(this->ddev, "pixel clock %u: miss\n", clock);
149 lsdc_pixpll_find(struct lsdc_pixpll * const this, unsigned int clock, struct lsdc_pixpll_parms *pout) argument
192 lsdc_pixel_pll_compute(struct lsdc_pixpll * const this, unsigned int clock, struct lsdc_pixpll_parms *pout) argument
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/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_snps_phy.h33 int intel_snps_phy_check_hdmi_link_rate(int clock);
H A Dintel_snps_phy.c86 * Basic DP link rates with 100 MHz reference clock.
90 .clock = 162000,
117 .clock = 270000,
139 .clock = 540000,
160 .clock = 810000,
180 .clock = 1000000,
215 .clock = 1350000,
259 * eDP link rates with 100 MHz reference clock.
263 .clock = 216000,
294 .clock
1982 intel_snps_phy_check_hdmi_link_rate(int clock) argument
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H A Dintel_cx0_phy.c485 * Basic DP link rates with 38.4 MHz reference clock.
492 .clock = 162000,
518 .clock = 216000,
544 .clock = 243000,
570 .clock = 270000,
596 .clock = 324000,
622 .clock = 432000,
648 .clock = 540000,
674 .clock = 675000,
700 .clock
1780 intel_c10_phy_check_hdmi_link_rate(int clock) argument
2021 intel_c20_phy_check_hdmi_link_rate(int clock) argument
2037 intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock) argument
2229 intel_c20_get_dp_rate(u32 clock) argument
2264 intel_c20_get_hdmi_rate(u32 clock) argument
2284 is_dp2(u32 clock) argument
2293 is_hdmi_frl(u32 clock) argument
2316 intel_get_c20_custom_width(u32 clock, bool dp) argument
2333 u32 clock = crtc_state->port_clock; local
2789 u32 clock; local
2813 intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock) argument
3002 u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val); local
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/linux-master/drivers/gpu/drm/renesas/shmobile/
H A Dshmob_drm_drv.h34 struct clk *clock; member in struct:shmob_drm_device
/linux-master/drivers/gpu/drm/bridge/imx/
H A Dimx8mp-hdmi-tx.c27 if (mode->clock < 13500)
30 if (mode->clock > 297000)
33 if (clk_round_rate(hdmi->pixclk, mode->clock * 1000) !=
34 mode->clock * 1000)
90 "Unable to get pixel clock\n");
/linux-master/kernel/time/
H A Dtimekeeping.c15 #include <linux/sched/clock.h>
99 .clock = &dummy_clock, \
185 * clock reference passed to the read function. This can cause crashes if
193 struct clocksource *clock = READ_ONCE(tkr->clock); local
195 return clock->read(clock);
204 u64 max_cycles = tk->tkr_mono.clock->max_cycles;
205 const char *name = tk->tkr_mono.clock->name;
208 printk_deferred("WARNING: timekeeping: Cycle offset (%lld) is larger than allowed by the '%s' clock'
309 tk_setup_internals(struct timekeeper *tk, struct clocksource *clock) argument
1501 timekeeping_notify(struct clocksource *clock) argument
1637 struct clocksource *clock; local
1781 struct clocksource *clock = tk->tkr_mono.clock; local
2412 struct clocksource *clock = READ_ONCE(tkr->clock); local
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Datombios_crtc.c313 u32 adjusted_clock = mode->clock;
315 u32 dp_clock = mode->clock;
316 u32 clock = mode->clock; local
318 bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock);
347 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
349 adjusted_clock = mode->clock * 2;
363 clock = (clock * 5) / 4;
366 clock
575 amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct amdgpu_atom_ss *ss) argument
824 u32 clock = mode->clock; local
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/linux-master/drivers/mfd/
H A Ddb8500-prcmu.c628 * prcmu_config_clkout - Configure one of the programmable clock outputs.
630 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
633 * Configures one of the programmable clock outputs (CLKOUTs).
877 pr_err("prcmu: Bad clock divider %d in %s\n",
1033 static int request_pll(u8 clock, bool enable) argument
1037 if (clock == PRCMU_PLLSOC0)
1038 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1039 else if (clock == PRCMU_PLLSOC1)
1040 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1050 writeb(clock, (tcdm_bas
1245 request_clock(u8 clock, bool enable) argument
1273 request_sga_clock(u8 clock, bool enable) argument
1373 db8500_prcmu_request_clock(u8 clock, bool enable) argument
1433 clock_rate(u8 clock) argument
1538 prcmu_clock_rate(u8 clock) argument
1593 round_clock_rate(u8 clock, unsigned long rate) argument
1731 prcmu_round_clock_rate(u8 clock, unsigned long rate) argument
1747 set_clock_rate(u8 clock, unsigned long rate) argument
1903 prcmu_set_clock_rate(u8 clock, unsigned long rate) argument
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/linux-master/drivers/media/platform/qcom/camss/
H A Dcamss-vfe.c513 struct camss_clock *clock)
521 return (!strcmp(clock->name, vfe_name) ||
522 !strcmp(clock->name, vfe_lite_name) ||
523 !strcmp(clock->name, "vfe_lite"));
527 * vfe_set_clock_rates - Calculate and set clock rates on VFE module
547 struct camss_clock *clock = &vfe->clock[i]; local
549 if (vfe_match_clock_names(vfe, clock)) {
574 for (j = 0; j < clock->nfreqs; j++)
575 if (min_rate < clock
512 vfe_match_clock_names(struct vfe_device *vfe, struct camss_clock *clock) argument
628 struct camss_clock *clock = &vfe->clock[i]; local
1450 struct camss_clock *clock = &vfe->clock[i]; local
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/linux-master/drivers/gpu/drm/mgag200/
H A Dmgag200_g200se.c85 mb = (mode->clock * bpp) / 1000;
123 long clock = new_crtc_state->mode.clock; local
132 permitteddelta = clock * 5 / 1000;
135 if (clock * testp > vcomax)
137 if (clock * testp < vcomin)
143 if (computed > clock)
144 tmpdelta = computed - clock;
146 tmpdelta = clock - computed;
207 long clock local
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/linux-master/drivers/gpu/drm/radeon/
H A Devergreen_hdmi.h60 struct radeon_crtc *crtc, unsigned int clock);
62 struct radeon_crtc *crtc, unsigned int clock);
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv04.c32 nv04_clk_pll_calc(struct nvkm_clk *clock, struct nvbios_pll *info, argument
36 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P);
H A Dmcp77.c56 u32 clock = 0; local
73 clock = ref * N1 / M1;
74 clock = clock / post_div;
77 return clock;
93 return 100000; /* PCIE reference clock */
157 nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
163 u32 clock, int *N, int *M, int *P)
178 return nv04_pll_calc(subdev, &pll, clock, N, M, NULL, NULL, P);
207 u32 out = 0, clock local
162 calc_pll(struct mcp77_clk *clk, u32 reg, u32 clock, int *N, int *M, int *P) argument
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/linux-master/kernel/sched/
H A Dbuild_policy.c16 #include <linux/sched/clock.h>
/linux-master/arch/powerpc/include/asm/
H A Dudbg.h29 void __init udbg_uart_setup(unsigned int speed, unsigned int clock);
30 unsigned int __init udbg_probe_uart_speed(unsigned int clock);
/linux-master/tools/perf/tests/shell/
H A Dstat_bpf_counters_cgrp.sh51 check_system_wide_counted_output=$(perf stat -a --bpf-counters --for-each-cgroup ${test_cgroups} -e cpu-clock -x, sleep 1 2>&1)
63 check_cpu_list_counted_output=$(perf stat -C 0,1 --bpf-counters --for-each-cgroup ${test_cgroups} -e cpu-clock -x, taskset -c 1 sleep 1 2>&1)
H A Dstat+std_output.sh14 event_name=(cpu-clock task-clock context-switches cpu-migrations page-faults stalled-cycles-frontend stalled-cycles-backend cycles instructions branches branch-misses)
/linux-master/drivers/clk/bcm/
H A Dclk-bcm63xx-gate.c8 #include <dt-bindings/clock/bcm3368-clock.h>
9 #include <dt-bindings/clock/bcm6318-clock.h>
10 #include <dt-bindings/clock/bcm6328-clock.h>
11 #include <dt-bindings/clock/bcm6358-clock.h>
12 #include <dt-bindings/clock/bcm6362-clock
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H A Dclk-bcm2835.c8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
10 * The clock tree on the 2835 has several levels. There's a root
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
38 #include <dt-bindings/clock/bcm2835.h>
321 * Real names of cprman clock parents looked up through
323 * parent_names[] arrays for clock registration.
345 /* Does a cycle of measuring a clock through the TCNT clock, which may
724 /* Unmask the reference clock fro
929 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); local
940 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); local
972 bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, unsigned long parent_rate, u32 div) argument
1023 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); local
1042 bcm2835_clock_wait_busy(struct bcm2835_clock *clock) argument
1060 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); local
1075 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); local
1103 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); local
1146 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); local
1264 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); local
1275 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); local
1297 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); local
1437 struct bcm2835_clock *clock; local
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/linux-master/drivers/scsi/
H A Dzalon.c53 * future. The clock = (int) pdc_result[16] does not look correct to
58 /* poke SCSI clock out of iodc data */
66 int clock, status;
70 clock = (int) pdc_result[16];
73 clock = defaultclock;
76 printk(KERN_DEBUG "%s: SCSI clock %d\n", __func__, clock);
77 return clock;
/linux-master/drivers/ata/
H A Dpata_pdc202xx_old.c168 * In UDMA3 or higher we have to clock switch for the duration of the
183 void __iomem *clock = master + 0x11; local
190 iowrite8(ioread8(clock) | sel66, clock);
192 iowrite8(ioread8(clock) & ~sel66, clock); local
218 * After a DMA completes we need to put the clock back to 33MHz for
232 /* The clock bits are in the same register for both channels */
234 void __iomem *clock = master + 0x11; local
240 iowrite8(ioread8(clock)
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/linux-master/drivers/gpu/drm/etnaviv/
H A Detnaviv_perfmon.c49 static inline void pipe_select(struct etnaviv_gpu *gpu, u32 clock, unsigned pipe) argument
51 clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
52 clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(pipe);
54 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); local
66 pipe_select(gpu, clock, i);
71 pipe_select(gpu, clock, 0);
80 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); local
85 pipe_select(gpu, clock, i);
90 pipe_select(gpu, clock,
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/linux-master/sound/usb/
H A Dclock.c21 #include "clock.h"
165 * Assume the clock is valid if clock source supports only one
167 * (there is no clock selector) and clock type is internal.
169 * reports that clock is invalid.
172 (fmt->clock & 0xff) == cs_desc->v2.bClockID &&
198 "%s(): cannot get clock validity for id %d\n",
230 /* If a clock source can't tell us whether it's valid, we assume it is */
243 "%s(): cannot get clock validit
488 get_sample_rate_v2v3(struct snd_usb_audio *chip, int iface, int altsetting, int clock) argument
518 snd_usb_set_sample_rate_v2v3(struct snd_usb_audio *chip, const struct audioformat *fmt, int clock, int rate) argument
559 int clock; local
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