amd/amdgpu/atombios_crtc.c

313 	u32 adjusted_clock = mode->clock;
315 	u32 dp_clock = mode->clock;
316 	u32 clock = mode->clock;
318 	bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock);
347 	/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
349 		adjusted_clock = mode->clock * 2;
363 			clock = (clock * 5) / 4;
366 			clock = (clock * 3) / 2;
369 			clock = clock * 2;
374 	/* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
390 			args.v1.usPixelClock = cpu_to_le16(clock / 10);
402 			args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
488 			/* if the default dcpll clock is specified,
496 			/* if the default dcpll clock is specified,
580 				      u32 clock,
605 			if (clock == ATOM_DISABLE)
607 			args.v1.usPixelClock = cpu_to_le16(clock / 10);
617 			args.v2.usPixelClock = cpu_to_le16(clock / 10);
627 			args.v3.usPixelClock = cpu_to_le16(clock / 10);
644 			args.v5.usPixelClock = cpu_to_le16(clock / 10);
674 			args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
706 			args.v7.ulPixelClock = cpu_to_le32(clock * 10); /* 100 hz units */
709 			    (clock > 165000))
770 		/* Assign mode clock for hdmi deep color max clock limit check */
771 		amdgpu_connector->pixelclock_for_modeset = mode->clock;
789 								 mode->clock / 10);
796 								 mode->clock / 10);
803 								 mode->clock / 10);
810 	/* adjust pixel clock as needed */
823 	u32 pll_clock = mode->clock;
824 	u32 clock = mode->clock;
829 	/* pass the actual clock to amdgpu_atombios_crtc_program_pll for HDMI */
832 		clock = amdgpu_crtc->adjusted_clock;
836 		pll = &adev->clock.ppll[0];
839 		pll = &adev->clock.ppll[1];
844 		pll = &adev->clock.ppll[2];
860 				  encoder_mode, amdgpu_encoder->encoder_id, clock,