/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_pps_regs.h | 43 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
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/linux-master/drivers/net/wireless/intel/iwlwifi/ |
H A D | iwl-context-info.h | 49 IWL_CTXT_INFO_RB_SIZE_16K = 0xa,
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/linux-master/drivers/staging/rtl8192e/rtl8192e/ |
H A D | rtl_pm.c | 43 rtl92e_writeb(dev, MAC_BLK_CTRL, 0xa);
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/linux-master/drivers/crypto/amlogic/ |
H A D | amlogic-gxl.h | 17 #define MODE_AES_256 0xa
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/linux-master/sound/soc/codecs/ |
H A D | wm8960.h | 24 #define WM8960_LDAC 0xa
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/linux-master/net/dsa/ |
H A D | tag_rtl4_a.c | 31 * 0xa = RTL8366RB DSA protocol 33 #define RTL4_A_PROTOCOL_RTL8366RB 0xa
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/linux-master/include/linux/mfd/ |
H A D | da8xx-cfgchip.h | 38 #define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa) 55 #define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa) 72 #define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa)
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/dpcs/ |
H A D | dpcs_2_0_0_sh_mask.h | 63 #define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa 135 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa 162 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa 304 #define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa 324 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa 444 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa 571 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa 617 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa 694 #define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa 766 #define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa [all...] |
H A D | dpcs_3_0_0_sh_mask.h | 52 #define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa 113 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa 140 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa 255 #define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa 275 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa 395 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa 522 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa 568 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa 647 #define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa 708 #define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa [all...] |
/linux-master/drivers/scsi/ |
H A D | constants.c | 109 {0xa, "Report target port groups"}, 121 {0xa, "Set target port groups"}, 214 {0xa, "Verify(32)"},
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
H A D | nbio_6_1_sh_mask.h | 43 #define PSWUSCFG0_COMMAND__INT_DIS__SHIFT 0xa 230 #define PSWUSCFG0_PMI_CAP__D2_SUPPORT__SHIFT 0xa 300 #define PSWUSCFG0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa 332 #define PSWUSCFG0_LINK_CAP__PM_SUPPORT__SHIFT 0xa 361 #define PSWUSCFG0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa 396 #define PSWUSCFG0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa 425 #define PSWUSCFG0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa 458 #define PSWUSCFG0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa 569 #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa 807 #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
H A D | sdma0_4_1_sh_mask.h | 69 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 102 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 141 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 166 #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 222 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 287 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 359 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 424 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 494 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 551 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/sdma1/ |
H A D | sdma1_4_0_sh_mask.h | 72 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa 105 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa 144 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 169 #define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 225 #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa 290 #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa 360 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 419 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 489 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 546 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/oss/ |
H A D | oss_3_0_1_sh_mask.h | 100 #define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa 138 #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa 150 #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa 188 #define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 228 #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa 334 #define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa 370 #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa 414 #define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa 444 #define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa 554 #define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa [all...] |
H A D | oss_3_0_1_enum.h | 64 IH_PERF_SEL_CLIENT7_IH_STALL = 0xa, 106 SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0xa, 281 SRBM_PERF_SEL_SEM_BUSY = 0xa, 311 GRBM_GFX_INDEX_VP8 = 0xa, 328 SRBM_GFX_CNTL_VP8 = 0xa, 345 SDMA_PERF_SEL_RB_CMD_FULL = 0xa, 434 DBG_BLOCK_ID_IH = 0xa, 691 DBG_BLOCK_ID_VC0_BY2 = 0xa, 813 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 875 DBG_BLOCK_ID_SXS_BY8 = 0xa, [all...] |
H A D | oss_3_0_enum.h | 64 IH_PERF_SEL_CLIENT7_IH_STALL = 0xa, 216 SRBM_PERF_SEL_SEM_BUSY = 0xa, 246 GRBM_GFX_INDEX_SAMSCP = 0xa, 263 SRBM_GFX_CNTL_SAMSCP = 0xa, 280 SDMA_PERF_SEL_RB_CMD_FULL = 0xa, 343 ARRAY_PRT_2D_TILED_THICK = 0xa, 441 DBG_CLIENT_BLKID_uvdf_0 = 0xa, 601 DBG_BLOCK_ID_IH = 0xa, 835 DBG_BLOCK_ID_SPIS_BY2 = 0xa, 953 DBG_BLOCK_ID_TCAA_BY4 = 0xa, [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/ |
H A D | gc_11_5_0_sh_mask.h | 59 #define SDMA0_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa 94 #define SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa 182 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 239 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 354 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 422 #define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa 442 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa 472 #define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT 0xa 535 #define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT 0xa 623 #define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
H A D | gmc_7_0_sh_mask.h | 60 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa 110 #define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa 232 #define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa 262 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa 342 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa 420 #define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa 460 #define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa 506 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa 532 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa 550 #define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa [all...] |
H A D | gmc_8_1_enum.h | 44 ARRAY_PRT_2D_TILED_THICK = 0xa, 142 DBG_CLIENT_BLKID_uvdf_0 = 0xa, 302 DBG_BLOCK_ID_IH = 0xa, 536 DBG_BLOCK_ID_SPIS_BY2 = 0xa, 654 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 714 DBG_BLOCK_ID_CB00_BY8 = 0xa, 745 DBG_BLOCK_ID_TA00_BY16 = 0xa, 802 CMASK_ALPHA1_FRAG4 = 0xa, 838 COLOR_8_8_8_8 = 0xa, 864 FMT_8_8_8_8 = 0xa, [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
H A D | mmhub_3_0_0_sh_mask.h | 546 #define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 561 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 832 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 845 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xa 1415 #define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1430 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1810 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 1837 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 1854 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 1934 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/bif/ |
H A D | bif_5_0_enum.h | 44 ARRAY_PRT_2D_TILED_THICK = 0xa, 142 DBG_CLIENT_BLKID_uvdf_0 = 0xa, 302 DBG_BLOCK_ID_IH = 0xa, 536 DBG_BLOCK_ID_SPIS_BY2 = 0xa, 654 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 714 DBG_BLOCK_ID_CB00_BY8 = 0xa, 745 DBG_BLOCK_ID_TA00_BY16 = 0xa, 802 CMASK_ALPHA1_FRAG4 = 0xa, 838 COLOR_8_8_8_8 = 0xa, 864 FMT_8_8_8_8 = 0xa, [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/dce/ |
H A D | dce_8_0_enum.h | 44 ARRAY_PRT_2D_TILED_THICK = 0xa, 142 DBG_CLIENT_BLKID_uvdm_1 = 0xa, 266 DBG_BLOCK_ID_IH = 0xa, 500 DBG_BLOCK_ID_SPIS_BY2 = 0xa, 618 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 678 DBG_BLOCK_ID_CB00_BY8 = 0xa, 709 DBG_BLOCK_ID_TA00_BY16 = 0xa, 760 CMASK_ALPHA1_FRAG4 = 0xa, 796 COLOR_8_8_8_8 = 0xa, 822 FMT_8_8_8_8 = 0xa, [all...] |
H A D | dce_10_0_enum.h | 38 DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa, 90 DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa, 108 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa, 428 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0xa, 466 DCIO_IMPCAL_STEP_DELAY_11us = 0xa, 619 ARRAY_PRT_2D_TILED_THICK = 0xa, 717 DBG_CLIENT_BLKID_uvdf_0 = 0xa, 877 DBG_BLOCK_ID_IH = 0xa, 1111 DBG_BLOCK_ID_SPIS_BY2 = 0xa, 1229 DBG_BLOCK_ID_TCAA_BY4 = 0xa, [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/athub/ |
H A D | athub_3_0_0_sh_mask.h | 256 #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 267 #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 278 #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 289 #define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 300 #define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 311 #define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 322 #define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 333 #define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 368 #define XPB_LB_ADDR__MASK0__SHIFT 0xa 392 #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa [all...] |
H A D | athub_4_1_0_sh_mask.h | 256 #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 267 #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 278 #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 289 #define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 300 #define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 311 #define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 322 #define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 333 #define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 369 #define XPB_LB_ADDR__MASK0__SHIFT 0xa 386 #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa [all...] |