Lines Matching refs:xa
72 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
105 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
144 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
169 #define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
225 #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa
290 #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa
360 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
419 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
489 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
546 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
634 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
694 #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
712 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
767 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
824 #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
903 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
988 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
1149 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1338 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1524 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1710 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa