Lines Matching refs:xa
69 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
102 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
141 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
166 #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
222 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa
287 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa
359 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
424 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
494 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
551 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
623 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
675 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
735 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
753 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
808 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
865 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
944 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
1022 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
1183 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1372 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1558 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa