asic_reg/oss/oss_3_0_1_sh_mask.h

100 #define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
138 #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
150 #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
188 #define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
228 #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
334 #define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa
370 #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
414 #define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa
444 #define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
554 #define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa
578 #define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT 0xa
692 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa
748 #define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
920 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
1028 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
1082 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
1100 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
1156 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
1232 #define SDMA0_ATCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
1258 #define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
1308 #define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
1358 #define SDMA0_ATCL1_INV0__WR_INV_IDLE__SHIFT 0xa
1424 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
1450 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
1488 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
1508 #define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT 0xa
1570 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0xa
1656 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1802 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1944 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2018 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
2126 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
2180 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
2198 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
2292 #define SDMA1_ATCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
2318 #define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
2368 #define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
2418 #define SDMA1_ATCL1_INV0__WR_INV_IDLE__SHIFT 0xa
2484 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
2514 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
2552 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
2572 #define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT 0xa
2628 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0xa
2714 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2860 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
3002 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
3102 #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa