Lines Matching refs:xa
59 #define SDMA0_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa
94 #define SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa
182 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
239 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
354 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
422 #define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa
442 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa
472 #define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT 0xa
535 #define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT 0xa
623 #define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa
643 #define SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa
666 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
858 #define SDMA0_STATUS4_REG__REG_POLLING__SHIFT 0xa
997 #define SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa
1073 #define SDMA0_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1192 #define SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa
1267 #define SDMA0_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1385 #define SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa
1460 #define SDMA0_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1578 #define SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa
1653 #define SDMA0_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1771 #define SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa
1846 #define SDMA0_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1964 #define SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa
2039 #define SDMA0_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2157 #define SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa
2232 #define SDMA0_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2350 #define SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa
2425 #define SDMA0_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2582 #define SDMA0_F32_CNTL__TH0_ENABLE__SHIFT 0xa
2636 #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2647 #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2656 #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
2667 #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
2935 #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1__SHIFT 0xa
3102 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
3151 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
3204 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
3239 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
3298 #define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT 0xa
3362 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
3385 #define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa
3453 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
3491 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
3531 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
3589 #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
3620 #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
3728 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0xa
3735 #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0xa
3804 #define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT 0xa
3967 #define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT 0xa
4013 #define GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD__SHIFT 0xa
4077 #define SQ_CONFIG__DISABLE_SGPR_RD_KILL__SHIFT 0xa
4100 #define SQC_CONFIG__EVICT_LRU__SHIFT 0xa
4145 #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
4301 #define SQC_MISC_CONFIG__SQC_GCR_RSP_FGCG_OVERRIDE__SHIFT 0xa
4355 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
4726 #define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
4836 #define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xa
4938 #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
4962 #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa
4975 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
5000 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
5100 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
5159 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
5237 #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
5339 #define DB_DEBUG6__OREO_TRANSITION_EVENT_EN__SHIFT 0xa
5389 #define DB_DEBUG5__DISABLE_HTILE_HARVESTING__SHIFT 0xa
5440 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT 0xa
5615 #define CB_HW_CONTROL_4__SMT_TIMEOUT_THRESHOLD__SHIFT 0xa
5735 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
5758 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
5808 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
5841 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
5874 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
5907 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
6193 #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
6226 #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
6259 #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
6292 #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
6465 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
6530 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
6660 #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
6793 #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa
6814 #define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
6865 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
6955 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
6988 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
7048 #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT 0xa
7076 #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
7142 #define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa
7179 #define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT 0xa
7243 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
7296 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
7308 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
7330 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
7397 #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
7567 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
7607 #define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT 0xa
7744 #define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT 0xa
7918 #define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
8022 #define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
8148 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
8204 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
8217 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
8317 #define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa
8320 #define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa
8323 #define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa
8326 #define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa
8329 #define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa
8523 #define GCUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT 0xa
8572 #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
8611 #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
8650 #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
8689 #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
8728 #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
8767 #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
8806 #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
8845 #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
8884 #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
8923 #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
8962 #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
9001 #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
9040 #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
9079 #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
9118 #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
9157 #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
9200 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
10143 #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10150 #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10157 #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10164 #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10171 #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10178 #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10185 #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10192 #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10199 #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10206 #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10213 #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10220 #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10227 #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10234 #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10241 #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10248 #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10255 #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
10329 #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT 0xa
10340 #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT 0xa
10351 #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT 0xa
10360 #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT 0xa
10559 #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
10570 #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
10760 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
10904 #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
10980 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
11138 #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
11197 #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa
11212 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
11354 #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
11392 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
11475 #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
11504 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
11605 #define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
11634 #define COMPUTE_PGM_RSRC3__TRAP_ON_START__SHIFT 0xa
11741 #define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE__SHIFT 0xa
11770 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa
11807 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa
11988 #define CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT 0xa
12027 #define CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT 0xa
12207 #define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT 0xa
12269 #define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT 0xa
12339 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
12367 #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
13091 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
13124 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
13405 #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
13516 #define CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT 0xa
13544 #define CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT 0xa
13572 #define CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT 0xa
13600 #define CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT 0xa
13676 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa
13799 #define CP_SD_CNTL__SDMA_EN__SHIFT 0xa
13941 #define CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT__SHIFT 0xa
14156 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
14223 #define CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE__SHIFT 0xa
14256 #define CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE__SHIFT 0xa
14399 #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa
14467 #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT 0xa
14933 #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
14998 #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
15075 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
15330 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
15375 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
16029 #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
16122 #define PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_RD__SHIFT 0xa
16185 #define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa
16608 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
16635 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
16662 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
16689 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
16716 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
16743 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
16770 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
16797 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
16824 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
16851 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
16878 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
16905 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
16932 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
16959 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
16986 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
17013 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
17040 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
17067 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
17094 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
17121 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
17148 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
17171 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
17194 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
17217 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
17240 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
17263 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
17286 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
17309 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
17332 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
17355 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
17378 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
17401 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
17439 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
17472 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
18037 #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
18148 #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
18171 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
18230 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
18393 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
18452 #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
18482 #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
18508 #define DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT 0xa
18624 #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa
18646 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
18719 #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
19063 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa
19092 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa
19223 #define CB_COLOR0_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa
19303 #define CB_COLOR1_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa
19383 #define CB_COLOR2_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa
19463 #define CB_COLOR3_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa
19543 #define CB_COLOR4_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa
19623 #define CB_COLOR5_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa
19703 #define CB_COLOR6_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa
19783 #define CB_COLOR7_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa
20136 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
20196 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
20249 #define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT 0xa
20298 #define PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES__SHIFT 0xa
20366 #define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT 0xa
20413 #define PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE__SHIFT 0xa
20449 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
20482 #define PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC__SHIFT 0xa
20515 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
20548 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
20580 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
20590 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
20626 #define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT 0xa
20826 #define DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0xa
20929 #define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa
20988 #define PC_CONFIG_CNTL_0__MAX_PRIMS_PER_PROBE__SHIFT 0xa
21030 #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY__SHIFT 0xa
21101 #define TCP_STATUS__GCR_BUSY__SHIFT 0xa
21148 #define TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE__SHIFT 0xa
21257 #define UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM__SHIFT 0xa
21299 #define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT 0xa
21331 #define GCR_TARGET_DISABLE__DISABLE_SE3_PHY__SHIFT 0xa
21453 #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0xa
21485 #define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY__SHIFT 0xa
21514 #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0xa
21544 #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa
21565 #define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT 0xa
21580 #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa
21701 #define EDC_HYSTERESIS_STAT__EDC_THRESHOLD_SEL__SHIFT 0xa
22814 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
22833 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
23156 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
23272 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0xa
23524 #define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
23738 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
23763 #define SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE__SHIFT 0xa
25456 #define GL1C_CTRL__HIT_QUEUE_DISABLE__SHIFT 0xa
25488 #define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa
25547 #define GL1C_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa
25654 #define CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa
25712 #define GL2C_CTRL2__GCR_ARB_CTRL__SHIFT 0xa
25803 #define GL2C_CM_CTRL2__CM_NBC_IND64_DISABLE__SHIFT 0xa
25831 #define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY__SHIFT 0xa
25928 #define GL2C_CTRL4__FED_SAFE_MODE__SHIFT 0xa
26528 #define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0xa
26892 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
26901 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
26919 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
26935 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
26944 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
26957 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
26964 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
27043 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
27084 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
27125 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
27160 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
27233 #define GE1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
27244 #define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
27253 #define GE1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
27264 #define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
27273 #define GE1_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
27284 #define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
27293 #define GE1_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
27304 #define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
27313 #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
27324 #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
27333 #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
27344 #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
27353 #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
27364 #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
27373 #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
27384 #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
27393 #define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
27404 #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
27413 #define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
27424 #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
27433 #define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
27444 #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
27453 #define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
27464 #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
27473 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
27484 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
27493 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
27504 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
27513 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
27524 #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
27533 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
27544 #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
27553 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
27564 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
27594 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
27605 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
27616 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
27627 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
27638 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
27647 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
27656 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
27665 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
27697 #define PC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
27708 #define PC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
27719 #define PC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
27730 #define PC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
27741 #define PC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
27750 #define PC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
27759 #define PC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
27768 #define PC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
28055 #define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT 0xa
28123 #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
28134 #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
28191 #define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
28202 #define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
28227 #define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
28236 #define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
28245 #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
28256 #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
28267 #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
28278 #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
28289 #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
28298 #define GDS_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
28307 #define GDS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
28316 #define GDS_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
28325 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
28336 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
28352 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
28363 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
28379 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
28390 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
28399 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
28410 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
28433 #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
28444 #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
28453 #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
28464 #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
28487 #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
28498 #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
28507 #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
28518 #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
28541 #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
28552 #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
28582 #define CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
28593 #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
28626 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
28648 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
28659 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
28683 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
28694 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
28703 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
28714 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
28723 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
28734 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
28840 #define RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT 0xa
28881 #define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires__SHIFT 0xa
28902 #define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride__SHIFT 0xa
29031 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
29042 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
29053 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
29067 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
29078 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
29096 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa
29113 #define GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
29124 #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
29140 #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
29151 #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
29160 #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
29171 #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
29182 #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
29205 #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
29214 #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
29223 #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
29252 #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
29263 #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
29293 #define GL1H_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
29304 #define GL1H_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
29334 #define CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
29345 #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
29407 #define GRTAVFS_TARG_VOLT__VALID__SHIFT 0xa
29661 #define RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT 0xa
29715 #define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT 0xa
29752 #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa
30041 #define RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE__SHIFT 0xa
30644 #define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT 0xa
31186 #define RLC_XT_INT_VEC_FORCE__NUM_10__SHIFT 0xa
31239 #define RLC_XT_INT_VEC_CLEAR__NUM_10__SHIFT 0xa
31534 #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
32144 #define SQ_CLK_CTRL__WCLK_SLEEP_VMEM_OVERRIDE__SHIFT 0xa
32177 #define ICG_SQ_CLK_CTRL__VALU_SGPR_CLK_OVERRIDE__SHIFT 0xa
32297 #define GFX_ICG_TA_CTRL__SOFT_OVERRIDE10__SHIFT 0xa
32346 #define GFX_ICG_TD_CTRL__SOFT_OVERRIDE10__SHIFT 0xa
32402 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE10__SHIFT 0xa
32453 #define GFX_ICG_CB_CTRL__SOFT_OVERRIDE21__SHIFT 0xa
32515 #define GFX_ICG_GL2A_CTRL__CLIENT2_OVERRIDE__SHIFT 0xa
32651 #define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE__SHIFT 0xa
32708 #define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE__SHIFT 0xa
32896 #define ICG_GL1C_CLK_CTRL__LATENCY_FIFO_CLK_OVERRIDE__SHIFT 0xa
33021 #define GFX_ICG_GL2C_CTRL__LATENCY_FIFO_OVERRIDE__SHIFT 0xa
33084 #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT10_OVERRIDE__SHIFT 0xa
33131 #define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_10__SHIFT 0xa
33196 #define ICG_LDS_CLK_CTRL__LDS_MEM_OVERRIDE__SHIFT 0xa
33251 #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE10__SHIFT 0xa
33368 #define GRBM_SA_REMAP_CNTL__SE5_SA_REMAP__SHIFT 0xa
33479 #define RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE__SHIFT 0xa
33509 #define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa
34127 #define GFX_IMU_PIC_INT_MASK__MASK_10__SHIFT 0xa
34192 #define GFX_IMU_PIC_INT_LVL__LVL_10__SHIFT 0xa
34257 #define GFX_IMU_PIC_INT_EDGE__EDGE_10__SHIFT 0xa
34394 #define GFX_IMU_PIC_INT_STATUS__INT_STATUS10__SHIFT 0xa
35068 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT 0xa
35198 #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5__SHIFT 0xa
35219 #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV5__SHIFT 0xa
35240 #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV5__SHIFT 0xa
35261 #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV5__SHIFT 0xa
35282 #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5__SHIFT 0xa
35327 #define RTAVFS_REG31__RTAVFSCPOCLKDIV5__SHIFT 0xa
35414 #define RTAVFS_REG44__RTAVFSV2__SHIFT 0xa
35461 #define RTAVFS_REG47__RTAVFSVOLTCODEPIMAX__SHIFT 0xa
35480 #define RTAVFS_REG49__RTAVFSPSMOSCENVDD__SHIFT 0xa
35497 #define RTAVFS_REG50__RTAVFSPSMOSCENVREG__SHIFT 0xa
35517 #define RTAVFS_REG51__RTAVFSSENDVDDTOPSMOUT__SHIFT 0xa
35874 #define RTAVFS_REG120__RTAVFSCPOAVGDIV5__SHIFT 0xa
36243 #define RTAVFS_REG189__RTAVFSVOLTCODEFROMBINARYSEARCH__SHIFT 0xa
36259 #define RTAVFS_REG190__RESERVED__SHIFT 0xa
36278 #define RTAVFS_REG191__RTAVFSSTOPATWAITFORACK__SHIFT 0xa
36341 #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
36366 #define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
36412 #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
36448 #define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0xa
36477 #define SQ_WAVE_HW_ID1__WGP_ID__SHIFT 0xa
36511 #define SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT 0xa