Searched refs:reg1 (Results 151 - 175 of 175) sorted by relevance

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/linux-master/drivers/net/ethernet/adaptec/
H A Dstarfire.c1620 u16 reg0, reg1, reg4, reg5; local
1629 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1631 if (reg1 & BMSR_LSTATUS) {
/linux-master/drivers/pinctrl/
H A Dpinctrl-ingenic.c3343 u8 reg1, reg2; local
3370 reg1 = JZ4770_GPIO_PAT1;
3373 reg1 = JZ4740_GPIO_TRIG;
3384 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3389 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3393 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
/linux-master/drivers/net/ethernet/socionext/
H A Dsni_ave.c374 int reg1, int reg2)
379 mac_addr[2] << 16 | mac_addr[3] << 24, priv->base + reg1);
372 ave_hw_write_macaddr(struct net_device *ndev, const unsigned char *mac_addr, int reg1, int reg2) argument
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_0.c1310 uint32_t reg0, uint32_t reg1,
1316 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1309 sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask) argument
H A Dsdma_v6_0.c1183 uint32_t reg0, uint32_t reg1,
1189 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1182 sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask) argument
H A Dsdma_v5_2.c1150 uint32_t reg0, uint32_t reg1,
1156 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1149 sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask) argument
H A Dmes_v11_0.c341 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
H A Dgfx_v9_4_3.c2761 uint32_t reg0, uint32_t reg1,
2764 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
2760 gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask) argument
H A Dgfx_v9_0.c5675 uint32_t reg0, uint32_t reg1,
5684 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5687 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
5674 gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask) argument
H A Dgfx_v11_0.c5781 uint32_t reg0, uint32_t reg1,
5786 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5780 gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask) argument
H A Dgfx_v10_0.c8760 uint32_t reg0, uint32_t reg1,
8770 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8773 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8759 gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask) argument
/linux-master/drivers/scsi/qedi/
H A Dqedi_fw_api.c267 SET_FIELD(ustorm_st_cxt->reg1.reg1_map, ISCSI_REG1_NUM_SGES, num_sges);
/linux-master/drivers/pinctrl/nuvoton/
H A Dpinctrl-npcm8xx.c1301 .fn1 = fn_ ## e, .reg1 = NPCM8XX_GCR_ ## f, .bit1 = g, \
1325 int fn1, reg1, bit1; member in struct:npcm8xx_pincfg
1835 if (cfg->reg1)
1836 regmap_update_bits(gcr_regmap, cfg->reg1,
/linux-master/drivers/edac/
H A Damd64_edac.c1506 int reg1 = DCSB1 + (cs * 4); local
1519 cs, *base1, (pvt->fam == 0x10) ? reg1
1525 int reg1 = DCSM1 + (cs * 4); local
1538 cs, *mask1, (pvt->fam == 0x10) ? reg1
/linux-master/tools/perf/util/
H A Dannotate.c3606 op_loc->reg1 = get_dwarf_regnum(regname, 0);
3676 op_loc->reg1 = -1;
3690 op_loc->reg1 = get_dwarf_regnum(s, 0);
3886 if (op_loc->reg1 == DWARF_REG_PC) {
/linux-master/drivers/net/wireless/ath/ath12k/
H A Dwmi.c2522 __le32 *reg1, *reg2; local
2566 reg1 = &chan_info->reg_info_1;
2594 *reg1 |= le32_encode_bits(channel_arg->minpower,
2596 *reg1 |= le32_encode_bits(channel_arg->maxpower,
2598 *reg1 |= le32_encode_bits(channel_arg->maxregpower,
2600 *reg1 |= le32_encode_bits(channel_arg->reg_class_id,
/linux-master/drivers/infiniband/hw/qib/
H A Dqib_iba7322.c6715 u64 reg, reg1, reg2; local
6730 reg1 = qib_read_kreg_port(ppd, krp_senddmabufmask1);
6734 reg, reg1, reg2);
6739 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1);
6740 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg1);
6746 reg, reg1, reg2);
6748 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1);
6753 reg, reg1, reg2);
/linux-master/drivers/staging/octeon/
H A Docteon-stubs.h1157 uint64_t reg1:11; member in struct:cvmx_pko_command_word0::__anon273
/linux-master/sound/soc/codecs/
H A Dwcd938x.c2259 s16 reg0, reg1, reg2, reg3, reg4; local
2279 reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6);
2425 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1);
H A Dwcd939x.c2189 unsigned int reg0, reg1, reg2, reg3, reg4; local
2195 reg1 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN6);
2306 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN6, reg1);
H A Dwcd934x.c2766 s16 reg0, reg1, reg2, reg3, reg4; local
2786 reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6);
2918 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1);
/linux-master/drivers/net/wireless/ath/ath11k/
H A Dwmi.c2508 u32 *reg1, *reg2; local
2557 reg1 = &chan_info->reg_info_1;
2582 *reg1 |= FIELD_PREP(WMI_CHAN_REG_INFO1_MIN_PWR,
2584 *reg1 |= FIELD_PREP(WMI_CHAN_REG_INFO1_MAX_PWR,
2586 *reg1 |= FIELD_PREP(WMI_CHAN_REG_INFO1_MAX_REG_PWR,
2588 *reg1 |= FIELD_PREP(WMI_CHAN_REG_INFO1_REG_CLS,
/linux-master/drivers/net/ethernet/sun/
H A Dniu.c2628 u16 reg1 = addr[2] << 8 | addr[3]; local
2633 nw64_mac(XMAC_ADDR1, reg1);
2637 nw64_mac(BMAC_ADDR1, reg1);
2653 u16 reg1 = addr[2] << 8 | addr[3]; local
2661 nw64_mac(XMAC_ALT_ADDR1(index), reg1); local
2665 nw64_mac(BMAC_ALT_ADDR1(index), reg1); local
/linux-master/drivers/net/wireless/ath/ath10k/
H A Dwmi.h3529 __le32 reg1; /* RADAR_REPORT_REG1_* */ member in struct:phyerr_radar_report
3567 __le32 reg1; /* SEARCH_FFT_REPORT_REG1_ * */ member in struct:phyerr_fft_report
/linux-master/drivers/video/fbdev/sis/
H A Dinit301.c7664 unsigned short vclkindex, temp, reg1, reg2; local
7667 reg1 = SiS_Pr->CSR2B;
7671 reg1 = SiS_Pr->SiS_VBVCLKData[vclkindex].Part4_A;
7681 SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0a,reg1);
7687 SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0a,reg1);

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