1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2019, Linaro Limited 3 4#include <linux/clk.h> 5#include <linux/clk-provider.h> 6#include <linux/interrupt.h> 7#include <linux/kernel.h> 8#include <linux/mfd/wcd934x/registers.h> 9#include <linux/mfd/wcd934x/wcd934x.h> 10#include <linux/module.h> 11#include <linux/mutex.h> 12#include <linux/of_clk.h> 13#include <linux/of.h> 14#include <linux/platform_device.h> 15#include <linux/regmap.h> 16#include <linux/slab.h> 17#include <linux/slimbus.h> 18#include <sound/pcm_params.h> 19#include <sound/soc.h> 20#include <sound/soc-dapm.h> 21#include <sound/tlv.h> 22#include "wcd-clsh-v2.h" 23#include "wcd-mbhc-v2.h" 24 25#define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 26 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 27 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 28/* Fractional Rates */ 29#define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 30 SNDRV_PCM_RATE_176400) 31#define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 32 SNDRV_PCM_FMTBIT_S24_LE) 33 34/* slave port water mark level 35 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 36 */ 37#define SLAVE_PORT_WATER_MARK_6BYTES 0 38#define SLAVE_PORT_WATER_MARK_9BYTES 1 39#define SLAVE_PORT_WATER_MARK_12BYTES 2 40#define SLAVE_PORT_WATER_MARK_15BYTES 3 41#define SLAVE_PORT_WATER_MARK_SHIFT 1 42#define SLAVE_PORT_ENABLE 1 43#define SLAVE_PORT_DISABLE 0 44#define WCD934X_SLIM_WATER_MARK_VAL \ 45 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 46 (SLAVE_PORT_ENABLE)) 47 48#define WCD934X_SLIM_NUM_PORT_REG 3 49#define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2) 50#define WCD934X_SLIM_IRQ_OVERFLOW BIT(0) 51#define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1) 52#define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2) 53 54#define WCD934X_MCLK_CLK_12P288MHZ 12288000 55#define WCD934X_MCLK_CLK_9P6MHZ 9600000 56 57/* Only valid for 9.6 MHz mclk */ 58#define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000 59#define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000 60 61/* Only valid for 12.288 MHz mclk */ 62#define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000 63 64#define WCD934X_DMIC_CLK_DIV_2 0x0 65#define WCD934X_DMIC_CLK_DIV_3 0x1 66#define WCD934X_DMIC_CLK_DIV_4 0x2 67#define WCD934X_DMIC_CLK_DIV_6 0x3 68#define WCD934X_DMIC_CLK_DIV_8 0x4 69#define WCD934X_DMIC_CLK_DIV_16 0x5 70#define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02 71 72#define TX_HPF_CUT_OFF_FREQ_MASK 0x60 73#define CF_MIN_3DB_4HZ 0x0 74#define CF_MIN_3DB_75HZ 0x1 75#define CF_MIN_3DB_150HZ 0x2 76 77#define WCD934X_RX_START 16 78#define WCD934X_NUM_INTERPOLATORS 9 79#define WCD934X_RX_PATH_CTL_OFFSET 20 80#define WCD934X_MAX_VALID_ADC_MUX 13 81#define WCD934X_INVALID_ADC_MUX 9 82 83#define WCD934X_SLIM_RX_CH(p) \ 84 {.port = p + WCD934X_RX_START, .shift = p,} 85 86#define WCD934X_SLIM_TX_CH(p) \ 87 {.port = p, .shift = p,} 88 89/* Feature masks to distinguish codec version */ 90#define DSD_DISABLED_MASK 0 91#define SLNQ_DISABLED_MASK 1 92 93#define DSD_DISABLED BIT(DSD_DISABLED_MASK) 94#define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK) 95 96/* As fine version info cannot be retrieved before wcd probe. 97 * Define three coarse versions for possible future use before wcd probe. 98 */ 99#define WCD_VERSION_WCD9340_1_0 0x400 100#define WCD_VERSION_WCD9341_1_0 0x410 101#define WCD_VERSION_WCD9340_1_1 0x401 102#define WCD_VERSION_WCD9341_1_1 0x411 103#define WCD934X_AMIC_PWR_LEVEL_LP 0 104#define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1 105#define WCD934X_AMIC_PWR_LEVEL_HP 2 106#define WCD934X_AMIC_PWR_LEVEL_HYBRID 3 107#define WCD934X_AMIC_PWR_LVL_MASK 0x60 108#define WCD934X_AMIC_PWR_LVL_SHIFT 0x5 109 110#define WCD934X_DEC_PWR_LVL_MASK 0x06 111#define WCD934X_DEC_PWR_LVL_LP 0x02 112#define WCD934X_DEC_PWR_LVL_HP 0x04 113#define WCD934X_DEC_PWR_LVL_DF 0x00 114#define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF 115 116#define WCD934X_DEF_MICBIAS_MV 1800 117#define WCD934X_MAX_MICBIAS_MV 2850 118 119#define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX) 120 121#define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \ 122{ \ 123 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 124 .info = wcd934x_iir_filter_info, \ 125 .get = wcd934x_get_iir_band_audio_mixer, \ 126 .put = wcd934x_put_iir_band_audio_mixer, \ 127 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \ 128 .iir_idx = iidx, \ 129 .band_idx = bidx, \ 130 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \ 131 } \ 132} 133 134/* Z value defined in milliohm */ 135#define WCD934X_ZDET_VAL_32 32000 136#define WCD934X_ZDET_VAL_400 400000 137#define WCD934X_ZDET_VAL_1200 1200000 138#define WCD934X_ZDET_VAL_100K 100000000 139/* Z floating defined in ohms */ 140#define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE 141 142#define WCD934X_ZDET_NUM_MEASUREMENTS 900 143#define WCD934X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 144#define WCD934X_MBHC_GET_X1(x) (x & 0x3FFF) 145/* Z value compared in milliOhm */ 146#define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 147#define WCD934X_MBHC_ZDET_CONST (86 * 16384) 148#define WCD934X_MBHC_MOISTURE_RREF R_24_KOHM 149#define WCD934X_MBHC_MAX_BUTTONS (8) 150#define WCD_MBHC_HS_V_MAX 1600 151 152#define WCD934X_INTERPOLATOR_PATH(id) \ 153 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 154 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 155 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 156 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 157 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 158 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 159 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 160 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 161 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \ 162 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \ 163 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 164 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 165 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 166 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 167 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 168 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 169 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 170 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 171 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \ 172 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \ 173 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 174 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 175 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 176 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 177 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 178 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 179 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 180 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 181 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \ 182 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \ 183 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 184 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 185 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 186 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 187 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 188 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 189 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 190 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 191 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 192 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 193 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 194 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \ 195 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \ 196 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \ 197 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \ 198 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \ 199 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \ 200 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \ 201 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"} 202 203#define WCD934X_INTERPOLATOR_MIX2(id) \ 204 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 205 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"} 206 207#define WCD934X_SLIM_RX_AIF_PATH(id) \ 208 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \ 209 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \ 210 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \ 211 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \ 212 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"} 213 214#define WCD934X_ADC_MUX(id) \ 215 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \ 216 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \ 217 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 218 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 219 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 220 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 221 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 222 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 223 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 224 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 225 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 226 {"AMIC MUX" #id, "ADC4", "ADC4"} 227 228#define WCD934X_IIR_INP_MUX(id) \ 229 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \ 230 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \ 231 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \ 232 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \ 233 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \ 234 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \ 235 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \ 236 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \ 237 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \ 238 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \ 239 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \ 240 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \ 241 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \ 242 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \ 243 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \ 244 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \ 245 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \ 246 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \ 247 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \ 248 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \ 249 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \ 250 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \ 251 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \ 252 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \ 253 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \ 254 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \ 255 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \ 256 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \ 257 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \ 258 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \ 259 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \ 260 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \ 261 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \ 262 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \ 263 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \ 264 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \ 265 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \ 266 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \ 267 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \ 268 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \ 269 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \ 270 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \ 271 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \ 272 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \ 273 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \ 274 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \ 275 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \ 276 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \ 277 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \ 278 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \ 279 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \ 280 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \ 281 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \ 282 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \ 283 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \ 284 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \ 285 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \ 286 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \ 287 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \ 288 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \ 289 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \ 290 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \ 291 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \ 292 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \ 293 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \ 294 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \ 295 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \ 296 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \ 297 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \ 298 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \ 299 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \ 300 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"} 301 302#define WCD934X_SLIM_TX_AIF_PATH(id) \ 303 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 304 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 305 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 306 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"} 307 308#define WCD934X_MAX_MICBIAS MIC_BIAS_4 309 310enum { 311 SIDO_SOURCE_INTERNAL, 312 SIDO_SOURCE_RCO_BG, 313}; 314 315enum { 316 INTERP_EAR = 0, 317 INTERP_HPHL, 318 INTERP_HPHR, 319 INTERP_LO1, 320 INTERP_LO2, 321 INTERP_LO3_NA, /* LO3 not avalible in Tavil */ 322 INTERP_LO4_NA, 323 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */ 324 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */ 325 INTERP_MAX, 326}; 327 328enum { 329 WCD934X_RX0 = 0, 330 WCD934X_RX1, 331 WCD934X_RX2, 332 WCD934X_RX3, 333 WCD934X_RX4, 334 WCD934X_RX5, 335 WCD934X_RX6, 336 WCD934X_RX7, 337 WCD934X_RX8, 338 WCD934X_RX9, 339 WCD934X_RX10, 340 WCD934X_RX11, 341 WCD934X_RX12, 342 WCD934X_RX_MAX, 343}; 344 345enum { 346 WCD934X_TX0 = 0, 347 WCD934X_TX1, 348 WCD934X_TX2, 349 WCD934X_TX3, 350 WCD934X_TX4, 351 WCD934X_TX5, 352 WCD934X_TX6, 353 WCD934X_TX7, 354 WCD934X_TX8, 355 WCD934X_TX9, 356 WCD934X_TX10, 357 WCD934X_TX11, 358 WCD934X_TX12, 359 WCD934X_TX13, 360 WCD934X_TX14, 361 WCD934X_TX15, 362 WCD934X_TX_MAX, 363}; 364 365struct wcd934x_slim_ch { 366 u32 ch_num; 367 u16 port; 368 u16 shift; 369 struct list_head list; 370}; 371 372static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = { 373 WCD934X_SLIM_TX_CH(0), 374 WCD934X_SLIM_TX_CH(1), 375 WCD934X_SLIM_TX_CH(2), 376 WCD934X_SLIM_TX_CH(3), 377 WCD934X_SLIM_TX_CH(4), 378 WCD934X_SLIM_TX_CH(5), 379 WCD934X_SLIM_TX_CH(6), 380 WCD934X_SLIM_TX_CH(7), 381 WCD934X_SLIM_TX_CH(8), 382 WCD934X_SLIM_TX_CH(9), 383 WCD934X_SLIM_TX_CH(10), 384 WCD934X_SLIM_TX_CH(11), 385 WCD934X_SLIM_TX_CH(12), 386 WCD934X_SLIM_TX_CH(13), 387 WCD934X_SLIM_TX_CH(14), 388 WCD934X_SLIM_TX_CH(15), 389}; 390 391static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = { 392 WCD934X_SLIM_RX_CH(0), /* 16 */ 393 WCD934X_SLIM_RX_CH(1), /* 17 */ 394 WCD934X_SLIM_RX_CH(2), 395 WCD934X_SLIM_RX_CH(3), 396 WCD934X_SLIM_RX_CH(4), 397 WCD934X_SLIM_RX_CH(5), 398 WCD934X_SLIM_RX_CH(6), 399 WCD934X_SLIM_RX_CH(7), 400 WCD934X_SLIM_RX_CH(8), 401 WCD934X_SLIM_RX_CH(9), 402 WCD934X_SLIM_RX_CH(10), 403 WCD934X_SLIM_RX_CH(11), 404 WCD934X_SLIM_RX_CH(12), 405}; 406 407/* Codec supports 2 IIR filters */ 408enum { 409 IIR0 = 0, 410 IIR1, 411 IIR_MAX, 412}; 413 414/* Each IIR has 5 Filter Stages */ 415enum { 416 BAND1 = 0, 417 BAND2, 418 BAND3, 419 BAND4, 420 BAND5, 421 BAND_MAX, 422}; 423 424enum { 425 COMPANDER_1, /* HPH_L */ 426 COMPANDER_2, /* HPH_R */ 427 COMPANDER_3, /* LO1_DIFF */ 428 COMPANDER_4, /* LO2_DIFF */ 429 COMPANDER_5, /* LO3_SE - not used in Tavil */ 430 COMPANDER_6, /* LO4_SE - not used in Tavil */ 431 COMPANDER_7, /* SWR SPK CH1 */ 432 COMPANDER_8, /* SWR SPK CH2 */ 433 COMPANDER_MAX, 434}; 435 436enum { 437 AIF1_PB = 0, 438 AIF1_CAP, 439 AIF2_PB, 440 AIF2_CAP, 441 AIF3_PB, 442 AIF3_CAP, 443 AIF4_PB, 444 AIF4_VIFEED, 445 AIF4_MAD_TX, 446 NUM_CODEC_DAIS, 447}; 448 449enum { 450 INTn_1_INP_SEL_ZERO = 0, 451 INTn_1_INP_SEL_DEC0, 452 INTn_1_INP_SEL_DEC1, 453 INTn_1_INP_SEL_IIR0, 454 INTn_1_INP_SEL_IIR1, 455 INTn_1_INP_SEL_RX0, 456 INTn_1_INP_SEL_RX1, 457 INTn_1_INP_SEL_RX2, 458 INTn_1_INP_SEL_RX3, 459 INTn_1_INP_SEL_RX4, 460 INTn_1_INP_SEL_RX5, 461 INTn_1_INP_SEL_RX6, 462 INTn_1_INP_SEL_RX7, 463}; 464 465enum { 466 INTn_2_INP_SEL_ZERO = 0, 467 INTn_2_INP_SEL_RX0, 468 INTn_2_INP_SEL_RX1, 469 INTn_2_INP_SEL_RX2, 470 INTn_2_INP_SEL_RX3, 471 INTn_2_INP_SEL_RX4, 472 INTn_2_INP_SEL_RX5, 473 INTn_2_INP_SEL_RX6, 474 INTn_2_INP_SEL_RX7, 475 INTn_2_INP_SEL_PROXIMITY, 476}; 477 478enum { 479 INTERP_MAIN_PATH, 480 INTERP_MIX_PATH, 481}; 482 483struct interp_sample_rate { 484 int sample_rate; 485 int rate_val; 486}; 487 488static struct interp_sample_rate sr_val_tbl[] = { 489 {8000, 0x0}, 490 {16000, 0x1}, 491 {32000, 0x3}, 492 {48000, 0x4}, 493 {96000, 0x5}, 494 {192000, 0x6}, 495 {384000, 0x7}, 496 {44100, 0x9}, 497 {88200, 0xA}, 498 {176400, 0xB}, 499 {352800, 0xC}, 500}; 501 502struct wcd934x_mbhc_zdet_param { 503 u16 ldo_ctl; 504 u16 noff; 505 u16 nshift; 506 u16 btn5; 507 u16 btn6; 508 u16 btn7; 509}; 510 511struct wcd_slim_codec_dai_data { 512 struct list_head slim_ch_list; 513 struct slim_stream_config sconfig; 514 struct slim_stream_runtime *sruntime; 515}; 516 517static const struct regmap_range_cfg wcd934x_ifc_ranges[] = { 518 { 519 .name = "WCD9335-IFC-DEV", 520 .range_min = 0x0, 521 .range_max = 0xffff, 522 .selector_reg = 0x800, 523 .selector_mask = 0xfff, 524 .selector_shift = 0, 525 .window_start = 0x800, 526 .window_len = 0x400, 527 }, 528}; 529 530static struct regmap_config wcd934x_ifc_regmap_config = { 531 .reg_bits = 16, 532 .val_bits = 8, 533 .max_register = 0xffff, 534 .ranges = wcd934x_ifc_ranges, 535 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges), 536}; 537 538struct wcd934x_codec { 539 struct device *dev; 540 struct clk_hw hw; 541 struct clk *extclk; 542 struct regmap *regmap; 543 struct regmap *if_regmap; 544 struct slim_device *sdev; 545 struct slim_device *sidev; 546 struct wcd_clsh_ctrl *clsh_ctrl; 547 struct snd_soc_component *component; 548 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX]; 549 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX]; 550 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 551 int rate; 552 u32 version; 553 u32 hph_mode; 554 int num_rx_port; 555 int num_tx_port; 556 u32 tx_port_value[WCD934X_TX_MAX]; 557 u32 rx_port_value[WCD934X_RX_MAX]; 558 int sido_input_src; 559 int dmic_0_1_clk_cnt; 560 int dmic_2_3_clk_cnt; 561 int dmic_4_5_clk_cnt; 562 int dmic_sample_rate; 563 int comp_enabled[COMPANDER_MAX]; 564 int sysclk_users; 565 struct mutex sysclk_mutex; 566 /* mbhc module */ 567 struct wcd_mbhc *mbhc; 568 struct wcd_mbhc_config mbhc_cfg; 569 struct wcd_mbhc_intr intr_ids; 570 bool mbhc_started; 571 struct mutex micb_lock; 572 u32 micb_ref[WCD934X_MAX_MICBIAS]; 573 u32 pullup_ref[WCD934X_MAX_MICBIAS]; 574 u32 micb1_mv; 575 u32 micb2_mv; 576 u32 micb3_mv; 577 u32 micb4_mv; 578}; 579 580#define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw) 581 582struct wcd_iir_filter_ctl { 583 unsigned int iir_idx; 584 unsigned int band_idx; 585 struct soc_bytes_ext bytes_ext; 586}; 587 588static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 589static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 590static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 591static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 592 593/* Cutoff frequency for high pass filter */ 594static const char * const cf_text[] = { 595 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 596}; 597 598static const char * const rx_cf_text[] = { 599 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 600 "CF_NEG_3DB_0P48HZ" 601}; 602 603static const char * const rx_hph_mode_mux_text[] = { 604 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 605 "Class-H Hi-Fi Low Power" 606}; 607 608static const char *const slim_rx_mux_text[] = { 609 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 610}; 611 612static const char * const rx_int0_7_mix_mux_text[] = { 613 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 614 "RX6", "RX7", "PROXIMITY" 615}; 616 617static const char * const rx_int_mix_mux_text[] = { 618 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 619 "RX6", "RX7" 620}; 621 622static const char * const rx_prim_mix_text[] = { 623 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 624 "RX3", "RX4", "RX5", "RX6", "RX7" 625}; 626 627static const char * const rx_sidetone_mix_text[] = { 628 "ZERO", "SRC0", "SRC1", "SRC_SUM" 629}; 630 631static const char * const iir_inp_mux_text[] = { 632 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", 633 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7" 634}; 635 636static const char * const rx_int_dem_inp_mux_text[] = { 637 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 638}; 639 640static const char * const rx_int0_1_interp_mux_text[] = { 641 "ZERO", "RX INT0_1 MIX1", 642}; 643 644static const char * const rx_int1_1_interp_mux_text[] = { 645 "ZERO", "RX INT1_1 MIX1", 646}; 647 648static const char * const rx_int2_1_interp_mux_text[] = { 649 "ZERO", "RX INT2_1 MIX1", 650}; 651 652static const char * const rx_int3_1_interp_mux_text[] = { 653 "ZERO", "RX INT3_1 MIX1", 654}; 655 656static const char * const rx_int4_1_interp_mux_text[] = { 657 "ZERO", "RX INT4_1 MIX1", 658}; 659 660static const char * const rx_int7_1_interp_mux_text[] = { 661 "ZERO", "RX INT7_1 MIX1", 662}; 663 664static const char * const rx_int8_1_interp_mux_text[] = { 665 "ZERO", "RX INT8_1 MIX1", 666}; 667 668static const char * const rx_int0_2_interp_mux_text[] = { 669 "ZERO", "RX INT0_2 MUX", 670}; 671 672static const char * const rx_int1_2_interp_mux_text[] = { 673 "ZERO", "RX INT1_2 MUX", 674}; 675 676static const char * const rx_int2_2_interp_mux_text[] = { 677 "ZERO", "RX INT2_2 MUX", 678}; 679 680static const char * const rx_int3_2_interp_mux_text[] = { 681 "ZERO", "RX INT3_2 MUX", 682}; 683 684static const char * const rx_int4_2_interp_mux_text[] = { 685 "ZERO", "RX INT4_2 MUX", 686}; 687 688static const char * const rx_int7_2_interp_mux_text[] = { 689 "ZERO", "RX INT7_2 MUX", 690}; 691 692static const char * const rx_int8_2_interp_mux_text[] = { 693 "ZERO", "RX INT8_2 MUX", 694}; 695 696static const char * const dmic_mux_text[] = { 697 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5" 698}; 699 700static const char * const amic_mux_text[] = { 701 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4" 702}; 703 704static const char * const amic4_5_sel_text[] = { 705 "AMIC4", "AMIC5" 706}; 707 708static const char * const adc_mux_text[] = { 709 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 710}; 711 712static const char * const cdc_if_tx0_mux_text[] = { 713 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 714}; 715 716static const char * const cdc_if_tx1_mux_text[] = { 717 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 718}; 719 720static const char * const cdc_if_tx2_mux_text[] = { 721 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 722}; 723 724static const char * const cdc_if_tx3_mux_text[] = { 725 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 726}; 727 728static const char * const cdc_if_tx4_mux_text[] = { 729 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 730}; 731 732static const char * const cdc_if_tx5_mux_text[] = { 733 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 734}; 735 736static const char * const cdc_if_tx6_mux_text[] = { 737 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 738}; 739 740static const char * const cdc_if_tx7_mux_text[] = { 741 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 742}; 743 744static const char * const cdc_if_tx8_mux_text[] = { 745 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 746}; 747 748static const char * const cdc_if_tx9_mux_text[] = { 749 "ZERO", "DEC7", "DEC7_192" 750}; 751 752static const char * const cdc_if_tx10_mux_text[] = { 753 "ZERO", "DEC6", "DEC6_192" 754}; 755 756static const char * const cdc_if_tx11_mux_text[] = { 757 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST" 758}; 759 760static const char * const cdc_if_tx11_inp1_mux_text[] = { 761 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", 762 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12" 763}; 764 765static const char * const cdc_if_tx13_mux_text[] = { 766 "CDC_DEC_5", "MAD_BRDCST" 767}; 768 769static const char * const cdc_if_tx13_inp1_mux_text[] = { 770 "ZERO", "DEC5", "DEC5_192" 771}; 772 773static const struct soc_enum cf_dec0_enum = 774 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 775 776static const struct soc_enum cf_dec1_enum = 777 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 778 779static const struct soc_enum cf_dec2_enum = 780 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 781 782static const struct soc_enum cf_dec3_enum = 783 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 784 785static const struct soc_enum cf_dec4_enum = 786 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 787 788static const struct soc_enum cf_dec5_enum = 789 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 790 791static const struct soc_enum cf_dec6_enum = 792 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 793 794static const struct soc_enum cf_dec7_enum = 795 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 796 797static const struct soc_enum cf_dec8_enum = 798 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 799 800static const struct soc_enum cf_int0_1_enum = 801 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 802 803static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2, 804 rx_cf_text); 805 806static const struct soc_enum cf_int1_1_enum = 807 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 808 809static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2, 810 rx_cf_text); 811 812static const struct soc_enum cf_int2_1_enum = 813 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 814 815static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2, 816 rx_cf_text); 817 818static const struct soc_enum cf_int3_1_enum = 819 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 820 821static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2, 822 rx_cf_text); 823 824static const struct soc_enum cf_int4_1_enum = 825 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 826 827static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2, 828 rx_cf_text); 829 830static const struct soc_enum cf_int7_1_enum = 831 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 832 833static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2, 834 rx_cf_text); 835 836static const struct soc_enum cf_int8_1_enum = 837 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 838 839static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2, 840 rx_cf_text); 841 842static const struct soc_enum rx_hph_mode_mux_enum = 843 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 844 rx_hph_mode_mux_text); 845 846static const struct soc_enum slim_rx_mux_enum = 847 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 848 849static const struct soc_enum rx_int0_2_mux_chain_enum = 850 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 851 rx_int0_7_mix_mux_text); 852 853static const struct soc_enum rx_int1_2_mux_chain_enum = 854 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 855 rx_int_mix_mux_text); 856 857static const struct soc_enum rx_int2_2_mux_chain_enum = 858 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 859 rx_int_mix_mux_text); 860 861static const struct soc_enum rx_int3_2_mux_chain_enum = 862 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 863 rx_int_mix_mux_text); 864 865static const struct soc_enum rx_int4_2_mux_chain_enum = 866 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 867 rx_int_mix_mux_text); 868 869static const struct soc_enum rx_int7_2_mux_chain_enum = 870 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 871 rx_int0_7_mix_mux_text); 872 873static const struct soc_enum rx_int8_2_mux_chain_enum = 874 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 875 rx_int_mix_mux_text); 876 877static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 878 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 879 rx_prim_mix_text); 880 881static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 882 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 883 rx_prim_mix_text); 884 885static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 886 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 887 rx_prim_mix_text); 888 889static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 890 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 891 rx_prim_mix_text); 892 893static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 894 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 895 rx_prim_mix_text); 896 897static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 898 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 899 rx_prim_mix_text); 900 901static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 902 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 903 rx_prim_mix_text); 904 905static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 906 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 907 rx_prim_mix_text); 908 909static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 910 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 911 rx_prim_mix_text); 912 913static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 914 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 915 rx_prim_mix_text); 916 917static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 918 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 919 rx_prim_mix_text); 920 921static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 922 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 923 rx_prim_mix_text); 924 925static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 926 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 927 rx_prim_mix_text); 928 929static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 930 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 931 rx_prim_mix_text); 932 933static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 934 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 935 rx_prim_mix_text); 936 937static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 938 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 939 rx_prim_mix_text); 940 941static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 942 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 943 rx_prim_mix_text); 944 945static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 946 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 947 rx_prim_mix_text); 948 949static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 950 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 951 rx_prim_mix_text); 952 953static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 954 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 955 rx_prim_mix_text); 956 957static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 958 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 959 rx_prim_mix_text); 960 961static const struct soc_enum rx_int0_mix2_inp_mux_enum = 962 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4, 963 rx_sidetone_mix_text); 964 965static const struct soc_enum rx_int1_mix2_inp_mux_enum = 966 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4, 967 rx_sidetone_mix_text); 968 969static const struct soc_enum rx_int2_mix2_inp_mux_enum = 970 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4, 971 rx_sidetone_mix_text); 972 973static const struct soc_enum rx_int3_mix2_inp_mux_enum = 974 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4, 975 rx_sidetone_mix_text); 976 977static const struct soc_enum rx_int4_mix2_inp_mux_enum = 978 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4, 979 rx_sidetone_mix_text); 980 981static const struct soc_enum rx_int7_mix2_inp_mux_enum = 982 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4, 983 rx_sidetone_mix_text); 984 985static const struct soc_enum iir0_inp0_mux_enum = 986 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 987 0, 18, iir_inp_mux_text); 988 989static const struct soc_enum iir0_inp1_mux_enum = 990 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 991 0, 18, iir_inp_mux_text); 992 993static const struct soc_enum iir0_inp2_mux_enum = 994 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 995 0, 18, iir_inp_mux_text); 996 997static const struct soc_enum iir0_inp3_mux_enum = 998 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 999 0, 18, iir_inp_mux_text); 1000 1001static const struct soc_enum iir1_inp0_mux_enum = 1002 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 1003 0, 18, iir_inp_mux_text); 1004 1005static const struct soc_enum iir1_inp1_mux_enum = 1006 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 1007 0, 18, iir_inp_mux_text); 1008 1009static const struct soc_enum iir1_inp2_mux_enum = 1010 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 1011 0, 18, iir_inp_mux_text); 1012 1013static const struct soc_enum iir1_inp3_mux_enum = 1014 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 1015 0, 18, iir_inp_mux_text); 1016 1017static const struct soc_enum rx_int0_dem_inp_mux_enum = 1018 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0, 1019 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1020 rx_int_dem_inp_mux_text); 1021 1022static const struct soc_enum rx_int1_dem_inp_mux_enum = 1023 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0, 1024 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1025 rx_int_dem_inp_mux_text); 1026 1027static const struct soc_enum rx_int2_dem_inp_mux_enum = 1028 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0, 1029 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1030 rx_int_dem_inp_mux_text); 1031 1032static const struct soc_enum tx_adc_mux0_enum = 1033 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 1034 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1035static const struct soc_enum tx_adc_mux1_enum = 1036 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 1037 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1038static const struct soc_enum tx_adc_mux2_enum = 1039 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 1040 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1041static const struct soc_enum tx_adc_mux3_enum = 1042 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 1043 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1044static const struct soc_enum tx_adc_mux4_enum = 1045 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2, 1046 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1047static const struct soc_enum tx_adc_mux5_enum = 1048 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2, 1049 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1050static const struct soc_enum tx_adc_mux6_enum = 1051 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2, 1052 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1053static const struct soc_enum tx_adc_mux7_enum = 1054 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2, 1055 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1056static const struct soc_enum tx_adc_mux8_enum = 1057 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4, 1058 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1059 1060static const struct soc_enum rx_int0_1_interp_mux_enum = 1061 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1062 rx_int0_1_interp_mux_text); 1063 1064static const struct soc_enum rx_int1_1_interp_mux_enum = 1065 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1066 rx_int1_1_interp_mux_text); 1067 1068static const struct soc_enum rx_int2_1_interp_mux_enum = 1069 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1070 rx_int2_1_interp_mux_text); 1071 1072static const struct soc_enum rx_int3_1_interp_mux_enum = 1073 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text); 1074 1075static const struct soc_enum rx_int4_1_interp_mux_enum = 1076 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text); 1077 1078static const struct soc_enum rx_int7_1_interp_mux_enum = 1079 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text); 1080 1081static const struct soc_enum rx_int8_1_interp_mux_enum = 1082 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text); 1083 1084static const struct soc_enum rx_int0_2_interp_mux_enum = 1085 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text); 1086 1087static const struct soc_enum rx_int1_2_interp_mux_enum = 1088 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text); 1089 1090static const struct soc_enum rx_int2_2_interp_mux_enum = 1091 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text); 1092 1093static const struct soc_enum rx_int3_2_interp_mux_enum = 1094 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text); 1095 1096static const struct soc_enum rx_int4_2_interp_mux_enum = 1097 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text); 1098 1099static const struct soc_enum rx_int7_2_interp_mux_enum = 1100 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text); 1101 1102static const struct soc_enum rx_int8_2_interp_mux_enum = 1103 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text); 1104 1105static const struct soc_enum tx_dmic_mux0_enum = 1106 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7, 1107 dmic_mux_text); 1108 1109static const struct soc_enum tx_dmic_mux1_enum = 1110 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7, 1111 dmic_mux_text); 1112 1113static const struct soc_enum tx_dmic_mux2_enum = 1114 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7, 1115 dmic_mux_text); 1116 1117static const struct soc_enum tx_dmic_mux3_enum = 1118 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7, 1119 dmic_mux_text); 1120 1121static const struct soc_enum tx_dmic_mux4_enum = 1122 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 1123 dmic_mux_text); 1124 1125static const struct soc_enum tx_dmic_mux5_enum = 1126 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 1127 dmic_mux_text); 1128 1129static const struct soc_enum tx_dmic_mux6_enum = 1130 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 1131 dmic_mux_text); 1132 1133static const struct soc_enum tx_dmic_mux7_enum = 1134 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 1135 dmic_mux_text); 1136 1137static const struct soc_enum tx_dmic_mux8_enum = 1138 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 1139 dmic_mux_text); 1140 1141static const struct soc_enum tx_amic_mux0_enum = 1142 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5, 1143 amic_mux_text); 1144static const struct soc_enum tx_amic_mux1_enum = 1145 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5, 1146 amic_mux_text); 1147static const struct soc_enum tx_amic_mux2_enum = 1148 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5, 1149 amic_mux_text); 1150static const struct soc_enum tx_amic_mux3_enum = 1151 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5, 1152 amic_mux_text); 1153static const struct soc_enum tx_amic_mux4_enum = 1154 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5, 1155 amic_mux_text); 1156static const struct soc_enum tx_amic_mux5_enum = 1157 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5, 1158 amic_mux_text); 1159static const struct soc_enum tx_amic_mux6_enum = 1160 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5, 1161 amic_mux_text); 1162static const struct soc_enum tx_amic_mux7_enum = 1163 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5, 1164 amic_mux_text); 1165static const struct soc_enum tx_amic_mux8_enum = 1166 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5, 1167 amic_mux_text); 1168 1169static const struct soc_enum tx_amic4_5_enum = 1170 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text); 1171 1172static const struct soc_enum cdc_if_tx0_mux_enum = 1173 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 1174 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text); 1175static const struct soc_enum cdc_if_tx1_mux_enum = 1176 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 1177 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text); 1178static const struct soc_enum cdc_if_tx2_mux_enum = 1179 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 1180 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text); 1181static const struct soc_enum cdc_if_tx3_mux_enum = 1182 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 1183 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text); 1184static const struct soc_enum cdc_if_tx4_mux_enum = 1185 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 1186 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text); 1187static const struct soc_enum cdc_if_tx5_mux_enum = 1188 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 1189 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text); 1190static const struct soc_enum cdc_if_tx6_mux_enum = 1191 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 1192 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text); 1193static const struct soc_enum cdc_if_tx7_mux_enum = 1194 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 1195 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text); 1196static const struct soc_enum cdc_if_tx8_mux_enum = 1197 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 1198 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text); 1199static const struct soc_enum cdc_if_tx9_mux_enum = 1200 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2, 1201 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text); 1202static const struct soc_enum cdc_if_tx10_mux_enum = 1203 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4, 1204 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text); 1205static const struct soc_enum cdc_if_tx11_inp1_mux_enum = 1206 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0, 1207 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text), 1208 cdc_if_tx11_inp1_mux_text); 1209static const struct soc_enum cdc_if_tx11_mux_enum = 1210 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0, 1211 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text); 1212static const struct soc_enum cdc_if_tx13_inp1_mux_enum = 1213 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4, 1214 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text), 1215 cdc_if_tx13_inp1_mux_text); 1216static const struct soc_enum cdc_if_tx13_mux_enum = 1217 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0, 1218 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text); 1219 1220static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 1221 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80), 1222 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40), 1223 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20), 1224 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 1225 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08), 1226 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0), 1227 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04), 1228 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10), 1229 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08), 1230 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01), 1231 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06), 1232 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80), 1233 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 1234 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03), 1235 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03), 1236 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08), 1237 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1238 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20), 1239 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80), 1240 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40), 1241 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10), 1242 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07), 1243 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70), 1244 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF), 1245 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0), 1246 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF), 1247 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40), 1248 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80), 1249 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0), 1250 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1251 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02), 1252 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01), 1253 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70), 1254 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20), 1255 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40), 1256 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10), 1257 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01), 1258 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01), 1259 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04), 1260 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08), 1261 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08), 1262 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40), 1263 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80), 1264 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF), 1265 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F), 1266 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10), 1267 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04), 1268 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02), 1269}; 1270 1271static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src) 1272{ 1273 if (sido_src == wcd->sido_input_src) 1274 return 0; 1275 1276 if (sido_src == SIDO_SOURCE_RCO_BG) { 1277 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO, 1278 WCD934X_ANA_RCO_BG_EN_MASK, 1279 WCD934X_ANA_RCO_BG_ENABLE); 1280 usleep_range(100, 110); 1281 } 1282 wcd->sido_input_src = sido_src; 1283 1284 return 0; 1285} 1286 1287static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd) 1288{ 1289 mutex_lock(&wcd->sysclk_mutex); 1290 1291 if (++wcd->sysclk_users != 1) { 1292 mutex_unlock(&wcd->sysclk_mutex); 1293 return 0; 1294 } 1295 mutex_unlock(&wcd->sysclk_mutex); 1296 1297 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1298 WCD934X_ANA_BIAS_EN_MASK, 1299 WCD934X_ANA_BIAS_EN); 1300 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1301 WCD934X_ANA_PRECHRG_EN_MASK, 1302 WCD934X_ANA_PRECHRG_EN); 1303 /* 1304 * 1ms delay is required after pre-charge is enabled 1305 * as per HW requirement 1306 */ 1307 usleep_range(1000, 1100); 1308 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1309 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1310 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1311 WCD934X_ANA_PRECHRG_MODE_MASK, 0); 1312 1313 /* 1314 * In data clock contrl register is changed 1315 * to CLK_SYS_MCLK_PRG 1316 */ 1317 1318 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1319 WCD934X_EXT_CLK_BUF_EN_MASK, 1320 WCD934X_EXT_CLK_BUF_EN); 1321 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1322 WCD934X_EXT_CLK_DIV_RATIO_MASK, 1323 WCD934X_EXT_CLK_DIV_BY_2); 1324 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1325 WCD934X_MCLK_SRC_MASK, 1326 WCD934X_MCLK_SRC_EXT_CLK); 1327 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1328 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN); 1329 regmap_update_bits(wcd->regmap, 1330 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 1331 WCD934X_CDC_FS_MCLK_CNT_EN_MASK, 1332 WCD934X_CDC_FS_MCLK_CNT_ENABLE); 1333 regmap_update_bits(wcd->regmap, 1334 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL, 1335 WCD934X_MCLK_EN_MASK, 1336 WCD934X_MCLK_EN); 1337 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE, 1338 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0); 1339 /* 1340 * 10us sleep is required after clock is enabled 1341 * as per HW requirement 1342 */ 1343 usleep_range(10, 15); 1344 1345 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1346 1347 return 0; 1348} 1349 1350static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd) 1351{ 1352 mutex_lock(&wcd->sysclk_mutex); 1353 if (--wcd->sysclk_users != 0) { 1354 mutex_unlock(&wcd->sysclk_mutex); 1355 return 0; 1356 } 1357 mutex_unlock(&wcd->sysclk_mutex); 1358 1359 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1360 WCD934X_EXT_CLK_BUF_EN_MASK | 1361 WCD934X_MCLK_EN_MASK, 0x0); 1362 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1363 WCD934X_ANA_BIAS_EN_MASK, 0); 1364 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1365 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1366 1367 return 0; 1368} 1369 1370static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable) 1371{ 1372 int ret = 0; 1373 1374 if (enable) { 1375 ret = clk_prepare_enable(wcd->extclk); 1376 1377 if (ret) { 1378 dev_err(wcd->dev, "%s: ext clk enable failed\n", 1379 __func__); 1380 return ret; 1381 } 1382 ret = wcd934x_enable_ana_bias_and_sysclk(wcd); 1383 } else { 1384 int val; 1385 1386 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1387 &val); 1388 1389 /* Don't disable clock if soundwire using it.*/ 1390 if (val & WCD934X_CDC_SWR_CLK_EN_MASK) 1391 return 0; 1392 1393 wcd934x_disable_ana_bias_and_syclk(wcd); 1394 clk_disable_unprepare(wcd->extclk); 1395 } 1396 1397 return ret; 1398} 1399 1400static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w, 1401 struct snd_kcontrol *kc, int event) 1402{ 1403 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 1404 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1405 1406 switch (event) { 1407 case SND_SOC_DAPM_PRE_PMU: 1408 return __wcd934x_cdc_mclk_enable(wcd, true); 1409 case SND_SOC_DAPM_POST_PMD: 1410 return __wcd934x_cdc_mclk_enable(wcd, false); 1411 } 1412 1413 return 0; 1414} 1415 1416static int wcd934x_get_version(struct wcd934x_codec *wcd) 1417{ 1418 int val1, val2, ver, ret; 1419 struct regmap *regmap; 1420 u16 id_minor; 1421 u32 version_mask = 0; 1422 1423 regmap = wcd->regmap; 1424 ver = 0; 1425 1426 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 1427 (u8 *)&id_minor, sizeof(u16)); 1428 1429 if (ret) 1430 return ret; 1431 1432 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1); 1433 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2); 1434 1435 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK; 1436 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK; 1437 1438 switch (version_mask) { 1439 case DSD_DISABLED | SLNQ_DISABLED: 1440 if (id_minor == 0) 1441 ver = WCD_VERSION_WCD9340_1_0; 1442 else if (id_minor == 0x01) 1443 ver = WCD_VERSION_WCD9340_1_1; 1444 break; 1445 case SLNQ_DISABLED: 1446 if (id_minor == 0) 1447 ver = WCD_VERSION_WCD9341_1_0; 1448 else if (id_minor == 0x01) 1449 ver = WCD_VERSION_WCD9341_1_1; 1450 break; 1451 } 1452 1453 wcd->version = ver; 1454 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver); 1455 1456 return 0; 1457} 1458 1459static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd) 1460{ 1461 int rc, val; 1462 1463 __wcd934x_cdc_mclk_enable(wcd, true); 1464 1465 regmap_update_bits(wcd->regmap, 1466 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1467 WCD934X_EFUSE_SENSE_STATE_MASK, 1468 WCD934X_EFUSE_SENSE_STATE_DEF); 1469 regmap_update_bits(wcd->regmap, 1470 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1471 WCD934X_EFUSE_SENSE_EN_MASK, 1472 WCD934X_EFUSE_SENSE_ENABLE); 1473 /* 1474 * 5ms sleep required after enabling efuse control 1475 * before checking the status. 1476 */ 1477 usleep_range(5000, 5500); 1478 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1479 1480 rc = regmap_read(wcd->regmap, 1481 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val); 1482 if (rc || (!(val & 0x01))) 1483 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n", 1484 __func__, val, rc); 1485 1486 __wcd934x_cdc_mclk_enable(wcd, false); 1487} 1488 1489static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable) 1490{ 1491 if (enable) { 1492 __wcd934x_cdc_mclk_enable(wcd, true); 1493 regmap_update_bits(wcd->regmap, 1494 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1495 WCD934X_CDC_SWR_CLK_EN_MASK, 1496 WCD934X_CDC_SWR_CLK_ENABLE); 1497 } else { 1498 regmap_update_bits(wcd->regmap, 1499 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1500 WCD934X_CDC_SWR_CLK_EN_MASK, 0); 1501 __wcd934x_cdc_mclk_enable(wcd, false); 1502 } 1503 1504 return 0; 1505} 1506 1507static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1508 u8 rate_val, u32 rate) 1509{ 1510 struct snd_soc_component *comp = dai->component; 1511 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1512 struct wcd934x_slim_ch *ch; 1513 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1514 int inp, j; 1515 1516 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1517 inp = ch->shift + INTn_1_INP_SEL_RX0; 1518 /* 1519 * Loop through all interpolator MUX inputs and find out 1520 * to which interpolator input, the slim rx port 1521 * is connected 1522 */ 1523 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1524 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1525 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1526 continue; 1527 1528 cfg0 = snd_soc_component_read(comp, 1529 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1530 cfg1 = snd_soc_component_read(comp, 1531 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1532 1533 inp0_sel = cfg0 & 1534 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1535 inp1_sel = (cfg0 >> 4) & 1536 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1537 inp2_sel = (cfg1 >> 4) & 1538 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1539 1540 if ((inp0_sel == inp) || (inp1_sel == inp) || 1541 (inp2_sel == inp)) { 1542 /* rate is in Hz */ 1543 /* 1544 * Ear and speaker primary path does not support 1545 * native sample rates 1546 */ 1547 if ((j == INTERP_EAR || j == INTERP_SPKR1 || 1548 j == INTERP_SPKR2) && rate == 44100) 1549 dev_err(wcd->dev, 1550 "Cannot set 44.1KHz on INT%d\n", 1551 j); 1552 else 1553 snd_soc_component_update_bits(comp, 1554 WCD934X_CDC_RX_PATH_CTL(j), 1555 WCD934X_CDC_MIX_PCM_RATE_MASK, 1556 rate_val); 1557 } 1558 } 1559 } 1560 1561 return 0; 1562} 1563 1564static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1565 int rate_val, u32 rate) 1566{ 1567 struct snd_soc_component *component = dai->component; 1568 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 1569 struct wcd934x_slim_ch *ch; 1570 int val, j; 1571 1572 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1573 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1574 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1575 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1576 continue; 1577 val = snd_soc_component_read(component, 1578 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1579 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1580 1581 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) { 1582 /* 1583 * Ear mix path supports only 48, 96, 192, 1584 * 384KHz only 1585 */ 1586 if ((j == INTERP_EAR) && 1587 (rate_val < 0x4 || 1588 rate_val > 0x7)) { 1589 dev_err(component->dev, 1590 "Invalid rate for AIF_PB DAI(%d)\n", 1591 dai->id); 1592 return -EINVAL; 1593 } 1594 1595 snd_soc_component_update_bits(component, 1596 WCD934X_CDC_RX_PATH_MIX_CTL(j), 1597 WCD934X_CDC_MIX_PCM_RATE_MASK, 1598 rate_val); 1599 } 1600 } 1601 } 1602 1603 return 0; 1604} 1605 1606static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai, 1607 u32 sample_rate) 1608{ 1609 int rate_val = 0; 1610 int i, ret; 1611 1612 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) { 1613 if (sample_rate == sr_val_tbl[i].sample_rate) { 1614 rate_val = sr_val_tbl[i].rate_val; 1615 break; 1616 } 1617 } 1618 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) { 1619 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate); 1620 return -EINVAL; 1621 } 1622 1623 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val, 1624 sample_rate); 1625 if (ret) 1626 return ret; 1627 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val, 1628 sample_rate); 1629 1630 return ret; 1631} 1632 1633static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai, 1634 u8 rate_val, u32 rate) 1635{ 1636 struct snd_soc_component *comp = dai->component; 1637 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 1638 u8 shift = 0, shift_val = 0, tx_mux_sel; 1639 struct wcd934x_slim_ch *ch; 1640 int tx_port, tx_port_reg; 1641 int decimator = -1; 1642 1643 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1644 tx_port = ch->port; 1645 /* Find the SB TX MUX input - which decimator is connected */ 1646 switch (tx_port) { 1647 case 0 ... 3: 1648 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0; 1649 shift = (tx_port << 1); 1650 shift_val = 0x03; 1651 break; 1652 case 4 ... 7: 1653 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1; 1654 shift = ((tx_port - 4) << 1); 1655 shift_val = 0x03; 1656 break; 1657 case 8 ... 10: 1658 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2; 1659 shift = ((tx_port - 8) << 1); 1660 shift_val = 0x03; 1661 break; 1662 case 11: 1663 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1664 shift = 0; 1665 shift_val = 0x0F; 1666 break; 1667 case 13: 1668 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1669 shift = 4; 1670 shift_val = 0x03; 1671 break; 1672 default: 1673 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1674 tx_port, dai->id); 1675 return -EINVAL; 1676 } 1677 1678 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1679 (shift_val << shift); 1680 1681 tx_mux_sel = tx_mux_sel >> shift; 1682 switch (tx_port) { 1683 case 0 ... 8: 1684 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1685 decimator = tx_port; 1686 break; 1687 case 9 ... 10: 1688 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1689 decimator = ((tx_port == 9) ? 7 : 6); 1690 break; 1691 case 11: 1692 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1693 decimator = tx_mux_sel - 1; 1694 break; 1695 case 13: 1696 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1697 decimator = 5; 1698 break; 1699 default: 1700 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n", 1701 tx_port); 1702 return -EINVAL; 1703 } 1704 1705 snd_soc_component_update_bits(comp, 1706 WCD934X_CDC_TX_PATH_CTL(decimator), 1707 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1708 rate_val); 1709 } 1710 1711 return 0; 1712} 1713 1714static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd, 1715 struct wcd_slim_codec_dai_data *dai_data, 1716 int direction) 1717{ 1718 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1719 struct slim_stream_config *cfg = &dai_data->sconfig; 1720 struct wcd934x_slim_ch *ch; 1721 u16 payload = 0; 1722 int ret, i; 1723 1724 cfg->ch_count = 0; 1725 cfg->direction = direction; 1726 cfg->port_mask = 0; 1727 1728 /* Configure slave interface device */ 1729 list_for_each_entry(ch, slim_ch_list, list) { 1730 cfg->ch_count++; 1731 payload |= 1 << ch->shift; 1732 cfg->port_mask |= BIT(ch->port); 1733 } 1734 1735 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1736 if (!cfg->chs) 1737 return -ENOMEM; 1738 1739 i = 0; 1740 list_for_each_entry(ch, slim_ch_list, list) { 1741 cfg->chs[i++] = ch->ch_num; 1742 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1743 /* write to interface device */ 1744 ret = regmap_write(wcd->if_regmap, 1745 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1746 payload); 1747 1748 if (ret < 0) 1749 goto err; 1750 1751 /* configure the slave port for water mark and enable*/ 1752 ret = regmap_write(wcd->if_regmap, 1753 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port), 1754 WCD934X_SLIM_WATER_MARK_VAL); 1755 if (ret < 0) 1756 goto err; 1757 } else { 1758 ret = regmap_write(wcd->if_regmap, 1759 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1760 payload & 0x00FF); 1761 if (ret < 0) 1762 goto err; 1763 1764 /* ports 8,9 */ 1765 ret = regmap_write(wcd->if_regmap, 1766 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1767 (payload & 0xFF00) >> 8); 1768 if (ret < 0) 1769 goto err; 1770 1771 /* configure the slave port for water mark and enable*/ 1772 ret = regmap_write(wcd->if_regmap, 1773 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port), 1774 WCD934X_SLIM_WATER_MARK_VAL); 1775 1776 if (ret < 0) 1777 goto err; 1778 } 1779 } 1780 1781 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM"); 1782 1783 return 0; 1784 1785err: 1786 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1787 kfree(cfg->chs); 1788 cfg->chs = NULL; 1789 1790 return ret; 1791} 1792 1793static int wcd934x_hw_params(struct snd_pcm_substream *substream, 1794 struct snd_pcm_hw_params *params, 1795 struct snd_soc_dai *dai) 1796{ 1797 struct wcd934x_codec *wcd; 1798 int ret, tx_fs_rate = 0; 1799 1800 wcd = snd_soc_component_get_drvdata(dai->component); 1801 1802 switch (substream->stream) { 1803 case SNDRV_PCM_STREAM_PLAYBACK: 1804 ret = wcd934x_set_interpolator_rate(dai, params_rate(params)); 1805 if (ret) { 1806 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1807 params_rate(params)); 1808 return ret; 1809 } 1810 switch (params_width(params)) { 1811 case 16 ... 24: 1812 wcd->dai[dai->id].sconfig.bps = params_width(params); 1813 break; 1814 default: 1815 dev_err(wcd->dev, "Invalid format 0x%x\n", 1816 params_width(params)); 1817 return -EINVAL; 1818 } 1819 break; 1820 1821 case SNDRV_PCM_STREAM_CAPTURE: 1822 switch (params_rate(params)) { 1823 case 8000: 1824 tx_fs_rate = 0; 1825 break; 1826 case 16000: 1827 tx_fs_rate = 1; 1828 break; 1829 case 32000: 1830 tx_fs_rate = 3; 1831 break; 1832 case 48000: 1833 tx_fs_rate = 4; 1834 break; 1835 case 96000: 1836 tx_fs_rate = 5; 1837 break; 1838 case 192000: 1839 tx_fs_rate = 6; 1840 break; 1841 case 384000: 1842 tx_fs_rate = 7; 1843 break; 1844 default: 1845 dev_err(wcd->dev, "Invalid TX sample rate: %d\n", 1846 params_rate(params)); 1847 return -EINVAL; 1848 1849 } 1850 1851 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate, 1852 params_rate(params)); 1853 if (ret < 0) { 1854 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1855 return ret; 1856 } 1857 switch (params_width(params)) { 1858 case 16 ... 32: 1859 wcd->dai[dai->id].sconfig.bps = params_width(params); 1860 break; 1861 default: 1862 dev_err(wcd->dev, "Invalid format 0x%x\n", 1863 params_width(params)); 1864 return -EINVAL; 1865 } 1866 break; 1867 default: 1868 dev_err(wcd->dev, "Invalid stream type %d\n", 1869 substream->stream); 1870 return -EINVAL; 1871 } 1872 1873 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1874 1875 return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1876} 1877 1878static int wcd934x_hw_free(struct snd_pcm_substream *substream, 1879 struct snd_soc_dai *dai) 1880{ 1881 struct wcd_slim_codec_dai_data *dai_data; 1882 struct wcd934x_codec *wcd; 1883 1884 wcd = snd_soc_component_get_drvdata(dai->component); 1885 1886 dai_data = &wcd->dai[dai->id]; 1887 1888 kfree(dai_data->sconfig.chs); 1889 1890 return 0; 1891} 1892 1893static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd, 1894 struct snd_soc_dai *dai) 1895{ 1896 struct wcd_slim_codec_dai_data *dai_data; 1897 struct wcd934x_codec *wcd; 1898 struct slim_stream_config *cfg; 1899 1900 wcd = snd_soc_component_get_drvdata(dai->component); 1901 1902 dai_data = &wcd->dai[dai->id]; 1903 1904 switch (cmd) { 1905 case SNDRV_PCM_TRIGGER_START: 1906 case SNDRV_PCM_TRIGGER_RESUME: 1907 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1908 cfg = &dai_data->sconfig; 1909 slim_stream_prepare(dai_data->sruntime, cfg); 1910 slim_stream_enable(dai_data->sruntime); 1911 break; 1912 case SNDRV_PCM_TRIGGER_STOP: 1913 case SNDRV_PCM_TRIGGER_SUSPEND: 1914 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1915 slim_stream_disable(dai_data->sruntime); 1916 slim_stream_unprepare(dai_data->sruntime); 1917 break; 1918 default: 1919 break; 1920 } 1921 1922 return 0; 1923} 1924 1925static int wcd934x_set_channel_map(struct snd_soc_dai *dai, 1926 unsigned int tx_num, unsigned int *tx_slot, 1927 unsigned int rx_num, unsigned int *rx_slot) 1928{ 1929 struct wcd934x_codec *wcd; 1930 int i; 1931 1932 wcd = snd_soc_component_get_drvdata(dai->component); 1933 1934 if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) { 1935 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n", 1936 tx_num, rx_num); 1937 return -EINVAL; 1938 } 1939 1940 if (!tx_slot || !rx_slot) { 1941 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1942 tx_slot, rx_slot); 1943 return -EINVAL; 1944 } 1945 1946 wcd->num_rx_port = rx_num; 1947 for (i = 0; i < rx_num; i++) { 1948 wcd->rx_chs[i].ch_num = rx_slot[i]; 1949 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 1950 } 1951 1952 wcd->num_tx_port = tx_num; 1953 for (i = 0; i < tx_num; i++) { 1954 wcd->tx_chs[i].ch_num = tx_slot[i]; 1955 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 1956 } 1957 1958 return 0; 1959} 1960 1961static int wcd934x_get_channel_map(struct snd_soc_dai *dai, 1962 unsigned int *tx_num, unsigned int *tx_slot, 1963 unsigned int *rx_num, unsigned int *rx_slot) 1964{ 1965 struct wcd934x_slim_ch *ch; 1966 struct wcd934x_codec *wcd; 1967 int i = 0; 1968 1969 wcd = snd_soc_component_get_drvdata(dai->component); 1970 1971 switch (dai->id) { 1972 case AIF1_PB: 1973 case AIF2_PB: 1974 case AIF3_PB: 1975 case AIF4_PB: 1976 if (!rx_slot || !rx_num) { 1977 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 1978 rx_slot, rx_num); 1979 return -EINVAL; 1980 } 1981 1982 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 1983 rx_slot[i++] = ch->ch_num; 1984 1985 *rx_num = i; 1986 break; 1987 case AIF1_CAP: 1988 case AIF2_CAP: 1989 case AIF3_CAP: 1990 if (!tx_slot || !tx_num) { 1991 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 1992 tx_slot, tx_num); 1993 return -EINVAL; 1994 } 1995 1996 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 1997 tx_slot[i++] = ch->ch_num; 1998 1999 *tx_num = i; 2000 break; 2001 default: 2002 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2003 break; 2004 } 2005 2006 return 0; 2007} 2008 2009static const struct snd_soc_dai_ops wcd934x_dai_ops = { 2010 .hw_params = wcd934x_hw_params, 2011 .hw_free = wcd934x_hw_free, 2012 .trigger = wcd934x_trigger, 2013 .set_channel_map = wcd934x_set_channel_map, 2014 .get_channel_map = wcd934x_get_channel_map, 2015}; 2016 2017static struct snd_soc_dai_driver wcd934x_slim_dais[] = { 2018 [0] = { 2019 .name = "wcd934x_rx1", 2020 .id = AIF1_PB, 2021 .playback = { 2022 .stream_name = "AIF1 Playback", 2023 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2024 .formats = WCD934X_FORMATS_S16_S24_LE, 2025 .rate_max = 192000, 2026 .rate_min = 8000, 2027 .channels_min = 1, 2028 .channels_max = 2, 2029 }, 2030 .ops = &wcd934x_dai_ops, 2031 }, 2032 [1] = { 2033 .name = "wcd934x_tx1", 2034 .id = AIF1_CAP, 2035 .capture = { 2036 .stream_name = "AIF1 Capture", 2037 .rates = WCD934X_RATES_MASK, 2038 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2039 .rate_min = 8000, 2040 .rate_max = 192000, 2041 .channels_min = 1, 2042 .channels_max = 4, 2043 }, 2044 .ops = &wcd934x_dai_ops, 2045 }, 2046 [2] = { 2047 .name = "wcd934x_rx2", 2048 .id = AIF2_PB, 2049 .playback = { 2050 .stream_name = "AIF2 Playback", 2051 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2052 .formats = WCD934X_FORMATS_S16_S24_LE, 2053 .rate_min = 8000, 2054 .rate_max = 192000, 2055 .channels_min = 1, 2056 .channels_max = 2, 2057 }, 2058 .ops = &wcd934x_dai_ops, 2059 }, 2060 [3] = { 2061 .name = "wcd934x_tx2", 2062 .id = AIF2_CAP, 2063 .capture = { 2064 .stream_name = "AIF2 Capture", 2065 .rates = WCD934X_RATES_MASK, 2066 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2067 .rate_min = 8000, 2068 .rate_max = 192000, 2069 .channels_min = 1, 2070 .channels_max = 4, 2071 }, 2072 .ops = &wcd934x_dai_ops, 2073 }, 2074 [4] = { 2075 .name = "wcd934x_rx3", 2076 .id = AIF3_PB, 2077 .playback = { 2078 .stream_name = "AIF3 Playback", 2079 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2080 .formats = WCD934X_FORMATS_S16_S24_LE, 2081 .rate_min = 8000, 2082 .rate_max = 192000, 2083 .channels_min = 1, 2084 .channels_max = 2, 2085 }, 2086 .ops = &wcd934x_dai_ops, 2087 }, 2088 [5] = { 2089 .name = "wcd934x_tx3", 2090 .id = AIF3_CAP, 2091 .capture = { 2092 .stream_name = "AIF3 Capture", 2093 .rates = WCD934X_RATES_MASK, 2094 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2095 .rate_min = 8000, 2096 .rate_max = 192000, 2097 .channels_min = 1, 2098 .channels_max = 4, 2099 }, 2100 .ops = &wcd934x_dai_ops, 2101 }, 2102 [6] = { 2103 .name = "wcd934x_rx4", 2104 .id = AIF4_PB, 2105 .playback = { 2106 .stream_name = "AIF4 Playback", 2107 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2108 .formats = WCD934X_FORMATS_S16_S24_LE, 2109 .rate_min = 8000, 2110 .rate_max = 192000, 2111 .channels_min = 1, 2112 .channels_max = 2, 2113 }, 2114 .ops = &wcd934x_dai_ops, 2115 }, 2116}; 2117 2118static int swclk_gate_enable(struct clk_hw *hw) 2119{ 2120 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true); 2121} 2122 2123static void swclk_gate_disable(struct clk_hw *hw) 2124{ 2125 wcd934x_swrm_clock(to_wcd934x_codec(hw), false); 2126} 2127 2128static int swclk_gate_is_enabled(struct clk_hw *hw) 2129{ 2130 struct wcd934x_codec *wcd = to_wcd934x_codec(hw); 2131 int ret, val; 2132 2133 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val); 2134 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK; 2135 2136 return ret; 2137} 2138 2139static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2140 unsigned long parent_rate) 2141{ 2142 return parent_rate / 2; 2143} 2144 2145static const struct clk_ops swclk_gate_ops = { 2146 .prepare = swclk_gate_enable, 2147 .unprepare = swclk_gate_disable, 2148 .is_enabled = swclk_gate_is_enabled, 2149 .recalc_rate = swclk_recalc_rate, 2150 2151}; 2152 2153static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd) 2154{ 2155 struct clk *parent = wcd->extclk; 2156 struct device *dev = wcd->dev; 2157 struct device_node *np = dev->parent->of_node; 2158 const char *parent_clk_name = NULL; 2159 const char *clk_name = "mclk"; 2160 struct clk_hw *hw; 2161 struct clk_init_data init; 2162 int ret; 2163 2164 if (of_property_read_u32(np, "clock-frequency", &wcd->rate)) 2165 return NULL; 2166 2167 parent_clk_name = __clk_get_name(parent); 2168 2169 of_property_read_string(np, "clock-output-names", &clk_name); 2170 2171 init.name = clk_name; 2172 init.ops = &swclk_gate_ops; 2173 init.flags = 0; 2174 init.parent_names = &parent_clk_name; 2175 init.num_parents = 1; 2176 wcd->hw.init = &init; 2177 2178 hw = &wcd->hw; 2179 ret = devm_clk_hw_register(wcd->dev->parent, hw); 2180 if (ret) 2181 return ERR_PTR(ret); 2182 2183 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 2184 if (ret) 2185 return ERR_PTR(ret); 2186 2187 return NULL; 2188} 2189 2190static int wcd934x_get_micbias_val(struct device *dev, const char *micbias, 2191 u32 *micb_mv) 2192{ 2193 int mv; 2194 2195 if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) { 2196 dev_err(dev, "%s value not found, using default\n", micbias); 2197 mv = WCD934X_DEF_MICBIAS_MV; 2198 } else { 2199 /* convert it to milli volts */ 2200 mv = mv/1000; 2201 } 2202 2203 if (mv < 1000 || mv > 2850) { 2204 dev_err(dev, "%s value not in valid range, using default\n", 2205 micbias); 2206 mv = WCD934X_DEF_MICBIAS_MV; 2207 } 2208 2209 *micb_mv = mv; 2210 2211 return (mv - 1000) / 50; 2212} 2213 2214static int wcd934x_init_dmic(struct snd_soc_component *comp) 2215{ 2216 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 2217 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 2218 u32 def_dmic_rate, dmic_clk_drv; 2219 2220 vout_ctl_1 = wcd934x_get_micbias_val(comp->dev, 2221 "qcom,micbias1-microvolt", 2222 &wcd->micb1_mv); 2223 vout_ctl_2 = wcd934x_get_micbias_val(comp->dev, 2224 "qcom,micbias2-microvolt", 2225 &wcd->micb2_mv); 2226 vout_ctl_3 = wcd934x_get_micbias_val(comp->dev, 2227 "qcom,micbias3-microvolt", 2228 &wcd->micb3_mv); 2229 vout_ctl_4 = wcd934x_get_micbias_val(comp->dev, 2230 "qcom,micbias4-microvolt", 2231 &wcd->micb4_mv); 2232 2233 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1, 2234 WCD934X_MICB_VAL_MASK, vout_ctl_1); 2235 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2, 2236 WCD934X_MICB_VAL_MASK, vout_ctl_2); 2237 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3, 2238 WCD934X_MICB_VAL_MASK, vout_ctl_3); 2239 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4, 2240 WCD934X_MICB_VAL_MASK, vout_ctl_4); 2241 2242 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ) 2243 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 2244 else 2245 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ; 2246 2247 wcd->dmic_sample_rate = def_dmic_rate; 2248 2249 dmic_clk_drv = 0; 2250 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0, 2251 0x0C, dmic_clk_drv << 2); 2252 2253 return 0; 2254} 2255 2256static void wcd934x_hw_init(struct wcd934x_codec *wcd) 2257{ 2258 struct regmap *rm = wcd->regmap; 2259 2260 /* set SPKR rate to FS_2P4_3P072 */ 2261 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08); 2262 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08); 2263 2264 /* Take DMICs out of reset */ 2265 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00); 2266} 2267 2268static int wcd934x_comp_init(struct snd_soc_component *component) 2269{ 2270 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2271 2272 wcd934x_hw_init(wcd); 2273 wcd934x_enable_efuse_sensing(wcd); 2274 wcd934x_get_version(wcd); 2275 2276 return 0; 2277} 2278 2279static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data) 2280{ 2281 struct wcd934x_codec *wcd = data; 2282 unsigned long status = 0; 2283 int i, j, port_id; 2284 unsigned int val, int_val = 0; 2285 irqreturn_t ret = IRQ_NONE; 2286 bool tx; 2287 unsigned short reg = 0; 2288 2289 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 2290 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 2291 regmap_read(wcd->if_regmap, i, &val); 2292 status |= ((u32)val << (8 * j)); 2293 } 2294 2295 for_each_set_bit(j, &status, 32) { 2296 tx = false; 2297 port_id = j; 2298 2299 if (j >= 16) { 2300 tx = true; 2301 port_id = j - 16; 2302 } 2303 2304 regmap_read(wcd->if_regmap, 2305 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 2306 if (val) { 2307 if (!tx) 2308 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2309 (port_id / 8); 2310 else 2311 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2312 (port_id / 8); 2313 regmap_read(wcd->if_regmap, reg, &int_val); 2314 } 2315 2316 if (val & WCD934X_SLIM_IRQ_OVERFLOW) 2317 dev_err_ratelimited(wcd->dev, 2318 "overflow error on %s port %d, value %x\n", 2319 (tx ? "TX" : "RX"), port_id, val); 2320 2321 if (val & WCD934X_SLIM_IRQ_UNDERFLOW) 2322 dev_err_ratelimited(wcd->dev, 2323 "underflow error on %s port %d, value %x\n", 2324 (tx ? "TX" : "RX"), port_id, val); 2325 2326 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) || 2327 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) { 2328 if (!tx) 2329 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2330 (port_id / 8); 2331 else 2332 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2333 (port_id / 8); 2334 regmap_read( 2335 wcd->if_regmap, reg, &int_val); 2336 if (int_val & (1 << (port_id % 8))) { 2337 int_val = int_val ^ (1 << (port_id % 8)); 2338 regmap_write(wcd->if_regmap, 2339 reg, int_val); 2340 } 2341 } 2342 2343 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED) 2344 dev_err_ratelimited(wcd->dev, 2345 "Port Closed %s port %d, value %x\n", 2346 (tx ? "TX" : "RX"), port_id, val); 2347 2348 regmap_write(wcd->if_regmap, 2349 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 2350 BIT(j % 8)); 2351 ret = IRQ_HANDLED; 2352 } 2353 2354 return ret; 2355} 2356 2357static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component, 2358 bool enable) 2359{ 2360 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1, 2361 WCD934X_MBHC_CTL_RCO_EN_MASK, enable); 2362} 2363 2364static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 2365 bool enable) 2366{ 2367 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT, 2368 WCD934X_ANA_MBHC_BIAS_EN, enable); 2369} 2370 2371static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component, 2372 int *btn_low, int *btn_high, 2373 int num_btn, bool is_micbias) 2374{ 2375 int i, vth; 2376 2377 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 2378 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 2379 __func__, num_btn); 2380 return; 2381 } 2382 2383 for (i = 0; i < num_btn; i++) { 2384 vth = ((btn_high[i] * 2) / 25) & 0x3F; 2385 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i, 2386 WCD934X_MBHC_BTN_VTH_MASK, vth); 2387 } 2388} 2389 2390static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 2391{ 2392 u8 val; 2393 2394 if (micb_num == MIC_BIAS_2) { 2395 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2, 2396 WCD934X_ANA_MICB2_ENABLE_MASK); 2397 if (val == WCD934X_MICB_ENABLE) 2398 return true; 2399 } 2400 return false; 2401} 2402 2403static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 2404 enum mbhc_hs_pullup_iref pull_up_cur) 2405{ 2406 /* Default pull up current to 2uA */ 2407 if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA || 2408 pull_up_cur == I_DEFAULT) 2409 pull_up_cur = I_2P0_UA; 2410 2411 2412 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 2413 WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur); 2414} 2415 2416static int wcd934x_micbias_control(struct snd_soc_component *component, 2417 int micb_num, int req, bool is_dapm) 2418{ 2419 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2420 int micb_index = micb_num - 1; 2421 u16 micb_reg; 2422 2423 switch (micb_num) { 2424 case MIC_BIAS_1: 2425 micb_reg = WCD934X_ANA_MICB1; 2426 break; 2427 case MIC_BIAS_2: 2428 micb_reg = WCD934X_ANA_MICB2; 2429 break; 2430 case MIC_BIAS_3: 2431 micb_reg = WCD934X_ANA_MICB3; 2432 break; 2433 case MIC_BIAS_4: 2434 micb_reg = WCD934X_ANA_MICB4; 2435 break; 2436 default: 2437 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2438 __func__, micb_num); 2439 return -EINVAL; 2440 } 2441 mutex_lock(&wcd934x->micb_lock); 2442 2443 switch (req) { 2444 case MICB_PULLUP_ENABLE: 2445 wcd934x->pullup_ref[micb_index]++; 2446 if ((wcd934x->pullup_ref[micb_index] == 1) && 2447 (wcd934x->micb_ref[micb_index] == 0)) 2448 snd_soc_component_write_field(component, micb_reg, 2449 WCD934X_ANA_MICB_EN_MASK, 2450 WCD934X_MICB_PULL_UP); 2451 break; 2452 case MICB_PULLUP_DISABLE: 2453 if (wcd934x->pullup_ref[micb_index] > 0) 2454 wcd934x->pullup_ref[micb_index]--; 2455 2456 if ((wcd934x->pullup_ref[micb_index] == 0) && 2457 (wcd934x->micb_ref[micb_index] == 0)) 2458 snd_soc_component_write_field(component, micb_reg, 2459 WCD934X_ANA_MICB_EN_MASK, 0); 2460 break; 2461 case MICB_ENABLE: 2462 wcd934x->micb_ref[micb_index]++; 2463 if (wcd934x->micb_ref[micb_index] == 1) { 2464 snd_soc_component_write_field(component, micb_reg, 2465 WCD934X_ANA_MICB_EN_MASK, 2466 WCD934X_MICB_ENABLE); 2467 if (micb_num == MIC_BIAS_2) 2468 wcd_mbhc_event_notify(wcd934x->mbhc, 2469 WCD_EVENT_POST_MICBIAS_2_ON); 2470 } 2471 2472 if (micb_num == MIC_BIAS_2 && is_dapm) 2473 wcd_mbhc_event_notify(wcd934x->mbhc, 2474 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 2475 break; 2476 case MICB_DISABLE: 2477 if (wcd934x->micb_ref[micb_index] > 0) 2478 wcd934x->micb_ref[micb_index]--; 2479 2480 if ((wcd934x->micb_ref[micb_index] == 0) && 2481 (wcd934x->pullup_ref[micb_index] > 0)) 2482 snd_soc_component_write_field(component, micb_reg, 2483 WCD934X_ANA_MICB_EN_MASK, 2484 WCD934X_MICB_PULL_UP); 2485 else if ((wcd934x->micb_ref[micb_index] == 0) && 2486 (wcd934x->pullup_ref[micb_index] == 0)) { 2487 if (micb_num == MIC_BIAS_2) 2488 wcd_mbhc_event_notify(wcd934x->mbhc, 2489 WCD_EVENT_PRE_MICBIAS_2_OFF); 2490 2491 snd_soc_component_write_field(component, micb_reg, 2492 WCD934X_ANA_MICB_EN_MASK, 0); 2493 if (micb_num == MIC_BIAS_2) 2494 wcd_mbhc_event_notify(wcd934x->mbhc, 2495 WCD_EVENT_POST_MICBIAS_2_OFF); 2496 } 2497 if (is_dapm && micb_num == MIC_BIAS_2) 2498 wcd_mbhc_event_notify(wcd934x->mbhc, 2499 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 2500 break; 2501 } 2502 2503 mutex_unlock(&wcd934x->micb_lock); 2504 2505 return 0; 2506} 2507 2508static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component, 2509 int micb_num, int req) 2510{ 2511 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2512 int ret; 2513 2514 if (req == MICB_ENABLE) 2515 __wcd934x_cdc_mclk_enable(wcd, true); 2516 2517 ret = wcd934x_micbias_control(component, micb_num, req, false); 2518 2519 if (req == MICB_DISABLE) 2520 __wcd934x_cdc_mclk_enable(wcd, false); 2521 2522 return ret; 2523} 2524 2525static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component, 2526 bool enable) 2527{ 2528 if (enable) { 2529 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2530 WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3); 2531 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2532 WCD934X_RAMP_EN_MASK, 1); 2533 } else { 2534 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2535 WCD934X_RAMP_EN_MASK, 0); 2536 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2537 WCD934X_RAMP_SHIFT_CTRL_MASK, 0); 2538 } 2539} 2540 2541static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv) 2542{ 2543 /* min micbias voltage is 1V and maximum is 2.85V */ 2544 if (micb_mv < 1000 || micb_mv > 2850) 2545 return -EINVAL; 2546 2547 return (micb_mv - 1000) / 50; 2548} 2549 2550static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 2551 int req_volt, int micb_num) 2552{ 2553 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2554 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 2555 2556 switch (micb_num) { 2557 case MIC_BIAS_1: 2558 micb_reg = WCD934X_ANA_MICB1; 2559 break; 2560 case MIC_BIAS_2: 2561 micb_reg = WCD934X_ANA_MICB2; 2562 break; 2563 case MIC_BIAS_3: 2564 micb_reg = WCD934X_ANA_MICB3; 2565 break; 2566 case MIC_BIAS_4: 2567 micb_reg = WCD934X_ANA_MICB4; 2568 break; 2569 default: 2570 return -EINVAL; 2571 } 2572 mutex_lock(&wcd934x->micb_lock); 2573 /* 2574 * If requested micbias voltage is same as current micbias 2575 * voltage, then just return. Otherwise, adjust voltage as 2576 * per requested value. If micbias is already enabled, then 2577 * to avoid slow micbias ramp-up or down enable pull-up 2578 * momentarily, change the micbias value and then re-enable 2579 * micbias. 2580 */ 2581 micb_en = snd_soc_component_read_field(component, micb_reg, 2582 WCD934X_ANA_MICB_EN_MASK); 2583 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2584 WCD934X_MICB_VAL_MASK); 2585 2586 req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt); 2587 if (req_vout_ctl < 0) { 2588 ret = -EINVAL; 2589 goto exit; 2590 } 2591 2592 if (cur_vout_ctl == req_vout_ctl) { 2593 ret = 0; 2594 goto exit; 2595 } 2596 2597 if (micb_en == WCD934X_MICB_ENABLE) 2598 snd_soc_component_write_field(component, micb_reg, 2599 WCD934X_ANA_MICB_EN_MASK, 2600 WCD934X_MICB_PULL_UP); 2601 2602 snd_soc_component_write_field(component, micb_reg, 2603 WCD934X_MICB_VAL_MASK, 2604 req_vout_ctl); 2605 2606 if (micb_en == WCD934X_MICB_ENABLE) { 2607 snd_soc_component_write_field(component, micb_reg, 2608 WCD934X_ANA_MICB_EN_MASK, 2609 WCD934X_MICB_ENABLE); 2610 /* 2611 * Add 2ms delay as per HW requirement after enabling 2612 * micbias 2613 */ 2614 usleep_range(2000, 2100); 2615 } 2616exit: 2617 mutex_unlock(&wcd934x->micb_lock); 2618 return ret; 2619} 2620 2621static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2622 int micb_num, bool req_en) 2623{ 2624 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2625 int rc, micb_mv; 2626 2627 if (micb_num != MIC_BIAS_2) 2628 return -EINVAL; 2629 /* 2630 * If device tree micbias level is already above the minimum 2631 * voltage needed to detect threshold microphone, then do 2632 * not change the micbias, just return. 2633 */ 2634 if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 2635 return 0; 2636 2637 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv; 2638 2639 rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2640 2641 return rc; 2642} 2643 2644static void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x, 2645 s16 *d1_a, u16 noff, 2646 int32_t *zdet) 2647{ 2648 int i; 2649 int val, val1; 2650 s16 c1; 2651 s32 x1, d1; 2652 int32_t denom; 2653 int minCode_param[] = { 2654 3277, 1639, 820, 410, 205, 103, 52, 26 2655 }; 2656 2657 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20); 2658 for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) { 2659 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val); 2660 if (val & 0x80) 2661 break; 2662 } 2663 val = val << 0x8; 2664 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1); 2665 val |= val1; 2666 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00); 2667 x1 = WCD934X_MBHC_GET_X1(val); 2668 c1 = WCD934X_MBHC_GET_C1(val); 2669 /* If ramp is not complete, give additional 5ms */ 2670 if ((c1 < 2) && x1) 2671 usleep_range(5000, 5050); 2672 2673 if (!c1 || !x1) { 2674 dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 2675 __func__, c1, x1); 2676 goto ramp_down; 2677 } 2678 d1 = d1_a[c1]; 2679 denom = (x1 * d1) - (1 << (14 - noff)); 2680 if (denom > 0) 2681 *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom; 2682 else if (x1 < minCode_param[noff]) 2683 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE; 2684 2685 dev_dbg(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%di (milliohm)\n", 2686 __func__, d1, c1, x1, *zdet); 2687ramp_down: 2688 i = 0; 2689 2690 while (x1) { 2691 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val); 2692 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1); 2693 val = val << 0x08; 2694 val |= val1; 2695 x1 = WCD934X_MBHC_GET_X1(val); 2696 i++; 2697 if (i == WCD934X_ZDET_NUM_MEASUREMENTS) 2698 break; 2699 } 2700} 2701 2702static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component, 2703 struct wcd934x_mbhc_zdet_param *zdet_param, 2704 int32_t *zl, int32_t *zr, s16 *d1_a) 2705{ 2706 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2707 int32_t zdet = 0; 2708 2709 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2710 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2711 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5, 2712 WCD934X_VTH_MASK, zdet_param->btn5); 2713 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6, 2714 WCD934X_VTH_MASK, zdet_param->btn6); 2715 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7, 2716 WCD934X_VTH_MASK, zdet_param->btn7); 2717 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2718 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2719 snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL, 2720 0x0F, zdet_param->nshift); 2721 2722 if (!zl) 2723 goto z_right; 2724 /* Start impedance measurement for HPH_L */ 2725 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80); 2726 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2727 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00); 2728 2729 *zl = zdet; 2730 2731z_right: 2732 if (!zr) 2733 return; 2734 /* Start impedance measurement for HPH_R */ 2735 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40); 2736 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2737 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00); 2738 2739 *zr = zdet; 2740} 2741 2742static void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2743 int32_t *z_val, int flag_l_r) 2744{ 2745 s16 q1; 2746 int q1_cal; 2747 2748 if (*z_val < (WCD934X_ZDET_VAL_400/1000)) 2749 q1 = snd_soc_component_read(component, 2750 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r)); 2751 else 2752 q1 = snd_soc_component_read(component, 2753 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r)); 2754 if (q1 & 0x80) 2755 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2756 else 2757 q1_cal = (10000 + (q1 * 25)); 2758 if (q1_cal > 0) 2759 *z_val = ((*z_val) * 10000) / q1_cal; 2760} 2761 2762static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2763 uint32_t *zl, uint32_t *zr) 2764{ 2765 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2766 s16 reg0, reg1, reg2, reg3, reg4; 2767 int32_t z1L, z1R, z1Ls; 2768 int zMono, z_diff1, z_diff2; 2769 bool is_fsm_disable = false; 2770 struct wcd934x_mbhc_zdet_param zdet_param[] = { 2771 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2772 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2773 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2774 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2775 }; 2776 struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL; 2777 s16 d1_a[][4] = { 2778 {0, 30, 90, 30}, 2779 {0, 30, 30, 5}, 2780 {0, 30, 30, 5}, 2781 {0, 30, 30, 5}, 2782 }; 2783 s16 *d1 = NULL; 2784 2785 reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5); 2786 reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6); 2787 reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7); 2788 reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK); 2789 reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL); 2790 2791 if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) { 2792 is_fsm_disable = true; 2793 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00); 2794 } 2795 2796 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2797 if (wcd934x->mbhc_cfg.hphl_swh) 2798 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00); 2799 2800 /* Turn off 100k pull down on HPHL */ 2801 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00); 2802 2803 /* First get impedance on Left */ 2804 d1 = d1_a[1]; 2805 zdet_param_ptr = &zdet_param[1]; 2806 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2807 2808 if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2809 goto left_ch_impedance; 2810 2811 /* Second ramp for left ch */ 2812 if (z1L < WCD934X_ZDET_VAL_32) { 2813 zdet_param_ptr = &zdet_param[0]; 2814 d1 = d1_a[0]; 2815 } else if ((z1L > WCD934X_ZDET_VAL_400) && 2816 (z1L <= WCD934X_ZDET_VAL_1200)) { 2817 zdet_param_ptr = &zdet_param[2]; 2818 d1 = d1_a[2]; 2819 } else if (z1L > WCD934X_ZDET_VAL_1200) { 2820 zdet_param_ptr = &zdet_param[3]; 2821 d1 = d1_a[3]; 2822 } 2823 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2824 2825left_ch_impedance: 2826 if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2827 (z1L > WCD934X_ZDET_VAL_100K)) { 2828 *zl = WCD934X_ZDET_FLOATING_IMPEDANCE; 2829 zdet_param_ptr = &zdet_param[1]; 2830 d1 = d1_a[1]; 2831 } else { 2832 *zl = z1L/1000; 2833 wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0); 2834 } 2835 dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2836 __func__, *zl); 2837 2838 /* Start of right impedance ramp and calculation */ 2839 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2840 if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2841 if (((z1R > WCD934X_ZDET_VAL_1200) && 2842 (zdet_param_ptr->noff == 0x6)) || 2843 ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE)) 2844 goto right_ch_impedance; 2845 /* Second ramp for right ch */ 2846 if (z1R < WCD934X_ZDET_VAL_32) { 2847 zdet_param_ptr = &zdet_param[0]; 2848 d1 = d1_a[0]; 2849 } else if ((z1R > WCD934X_ZDET_VAL_400) && 2850 (z1R <= WCD934X_ZDET_VAL_1200)) { 2851 zdet_param_ptr = &zdet_param[2]; 2852 d1 = d1_a[2]; 2853 } else if (z1R > WCD934X_ZDET_VAL_1200) { 2854 zdet_param_ptr = &zdet_param[3]; 2855 d1 = d1_a[3]; 2856 } 2857 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2858 } 2859right_ch_impedance: 2860 if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2861 (z1R > WCD934X_ZDET_VAL_100K)) { 2862 *zr = WCD934X_ZDET_FLOATING_IMPEDANCE; 2863 } else { 2864 *zr = z1R/1000; 2865 wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1); 2866 } 2867 dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2868 __func__, *zr); 2869 2870 /* Mono/stereo detection */ 2871 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) && 2872 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) { 2873 dev_dbg(component->dev, 2874 "%s: plug type is invalid or extension cable\n", 2875 __func__); 2876 goto zdet_complete; 2877 } 2878 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2879 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2880 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2881 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2882 dev_dbg(component->dev, 2883 "%s: Mono plug type with one ch floating or shorted to GND\n", 2884 __func__); 2885 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2886 goto zdet_complete; 2887 } 2888 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2889 WCD934X_HPHPA_GND_OVR_MASK, 1); 2890 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2891 WCD934X_HPHPA_GND_R_MASK, 1); 2892 if (*zl < (WCD934X_ZDET_VAL_32/1000)) 2893 wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2894 else 2895 wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2896 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2897 WCD934X_HPHPA_GND_R_MASK, 0); 2898 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2899 WCD934X_HPHPA_GND_OVR_MASK, 0); 2900 z1Ls /= 1000; 2901 wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2902 /* Parallel of left Z and 9 ohm pull down resistor */ 2903 zMono = ((*zl) * 9) / ((*zl) + 9); 2904 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2905 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2906 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2907 dev_err(component->dev, "%s: stereo plug type detected\n", 2908 __func__); 2909 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO); 2910 } else { 2911 dev_err(component->dev, "%s: MONO plug type detected\n", 2912 __func__); 2913 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2914 } 2915 2916zdet_complete: 2917 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0); 2918 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1); 2919 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2); 2920 /* Turn on 100k pull down on HPHL */ 2921 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01); 2922 2923 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2924 if (wcd934x->mbhc_cfg.hphl_swh) 2925 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80); 2926 2927 snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2928 snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3); 2929 if (is_fsm_disable) 2930 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80); 2931} 2932 2933static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2934 bool enable) 2935{ 2936 if (enable) { 2937 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2938 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1); 2939 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2940 WCD934X_MBHC_GND_DET_EN_MASK, 1); 2941 } else { 2942 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2943 WCD934X_MBHC_GND_DET_EN_MASK, 0); 2944 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2945 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0); 2946 } 2947} 2948 2949static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2950 bool enable) 2951{ 2952 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2953 WCD934X_HPHPA_GND_R_MASK, enable); 2954 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2955 WCD934X_HPHPA_GND_L_MASK, enable); 2956} 2957 2958static const struct wcd_mbhc_cb mbhc_cb = { 2959 .clk_setup = wcd934x_mbhc_clk_setup, 2960 .mbhc_bias = wcd934x_mbhc_mbhc_bias_control, 2961 .set_btn_thr = wcd934x_mbhc_program_btn_thr, 2962 .micbias_enable_status = wcd934x_mbhc_micb_en_status, 2963 .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control, 2964 .mbhc_micbias_control = wcd934x_mbhc_request_micbias, 2965 .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control, 2966 .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic, 2967 .compute_impedance = wcd934x_wcd_mbhc_calc_impedance, 2968 .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl, 2969 .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl, 2970}; 2971 2972static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol, 2973 struct snd_ctl_elem_value *ucontrol) 2974{ 2975 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2976 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2977 2978 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc); 2979 2980 return 0; 2981} 2982 2983static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2984 struct snd_ctl_elem_value *ucontrol) 2985{ 2986 uint32_t zl, zr; 2987 bool hphr; 2988 struct soc_mixer_control *mc; 2989 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2990 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2991 2992 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2993 hphr = mc->shift; 2994 wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr); 2995 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2996 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2997 2998 return 0; 2999} 3000static const struct snd_kcontrol_new hph_type_detect_controls[] = { 3001 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 3002 wcd934x_get_hph_type, NULL), 3003}; 3004 3005static const struct snd_kcontrol_new impedance_detect_controls[] = { 3006 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 3007 wcd934x_hph_impedance_get, NULL), 3008 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 3009 wcd934x_hph_impedance_get, NULL), 3010}; 3011 3012static int wcd934x_mbhc_init(struct snd_soc_component *component) 3013{ 3014 struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent); 3015 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3016 struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids; 3017 3018 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data, 3019 WCD934X_IRQ_MBHC_SW_DET); 3020 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data, 3021 WCD934X_IRQ_MBHC_BUTTON_PRESS_DET); 3022 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data, 3023 WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET); 3024 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data, 3025 WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 3026 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data, 3027 WCD934X_IRQ_MBHC_ELECT_INS_REM_DET); 3028 intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data, 3029 WCD934X_IRQ_HPH_PA_OCPL_FAULT); 3030 intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data, 3031 WCD934X_IRQ_HPH_PA_OCPR_FAULT); 3032 3033 wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 3034 if (IS_ERR(wcd->mbhc)) { 3035 wcd->mbhc = NULL; 3036 return -EINVAL; 3037 } 3038 3039 snd_soc_add_component_controls(component, impedance_detect_controls, 3040 ARRAY_SIZE(impedance_detect_controls)); 3041 snd_soc_add_component_controls(component, hph_type_detect_controls, 3042 ARRAY_SIZE(hph_type_detect_controls)); 3043 3044 return 0; 3045} 3046 3047static void wcd934x_mbhc_deinit(struct snd_soc_component *component) 3048{ 3049 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3050 3051 if (!wcd->mbhc) 3052 return; 3053 3054 wcd_mbhc_deinit(wcd->mbhc); 3055} 3056 3057static int wcd934x_comp_probe(struct snd_soc_component *component) 3058{ 3059 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3060 int i; 3061 3062 snd_soc_component_init_regmap(component, wcd->regmap); 3063 wcd->component = component; 3064 3065 /* Class-H Init*/ 3066 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version); 3067 if (IS_ERR(wcd->clsh_ctrl)) 3068 return PTR_ERR(wcd->clsh_ctrl); 3069 3070 /* Default HPH Mode to Class-H Low HiFi */ 3071 wcd->hph_mode = CLS_H_LOHIFI; 3072 3073 wcd934x_comp_init(component); 3074 3075 for (i = 0; i < NUM_CODEC_DAIS; i++) 3076 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 3077 3078 wcd934x_init_dmic(component); 3079 3080 if (wcd934x_mbhc_init(component)) 3081 dev_err(component->dev, "Failed to Initialize MBHC\n"); 3082 3083 return 0; 3084} 3085 3086static void wcd934x_comp_remove(struct snd_soc_component *comp) 3087{ 3088 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3089 3090 wcd934x_mbhc_deinit(comp); 3091 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 3092} 3093 3094static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp, 3095 int clk_id, int source, 3096 unsigned int freq, int dir) 3097{ 3098 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3099 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ; 3100 3101 wcd->rate = freq; 3102 3103 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ) 3104 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ; 3105 3106 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 3107 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 3108 val); 3109 3110 return clk_set_rate(wcd->extclk, freq); 3111} 3112 3113static uint32_t get_iir_band_coeff(struct snd_soc_component *component, 3114 int iir_idx, int band_idx, int coeff_idx) 3115{ 3116 u32 value = 0; 3117 int reg, b2_reg; 3118 3119 /* Address does not automatically update if reading */ 3120 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3121 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3122 3123 snd_soc_component_write(component, reg, 3124 ((band_idx * BAND_MAX + coeff_idx) * 3125 sizeof(uint32_t)) & 0x7F); 3126 3127 value |= snd_soc_component_read(component, b2_reg); 3128 snd_soc_component_write(component, reg, 3129 ((band_idx * BAND_MAX + coeff_idx) 3130 * sizeof(uint32_t) + 1) & 0x7F); 3131 3132 value |= (snd_soc_component_read(component, b2_reg) << 8); 3133 snd_soc_component_write(component, reg, 3134 ((band_idx * BAND_MAX + coeff_idx) 3135 * sizeof(uint32_t) + 2) & 0x7F); 3136 3137 value |= (snd_soc_component_read(component, b2_reg) << 16); 3138 snd_soc_component_write(component, reg, 3139 ((band_idx * BAND_MAX + coeff_idx) 3140 * sizeof(uint32_t) + 3) & 0x7F); 3141 3142 /* Mask bits top 2 bits since they are reserved */ 3143 value |= (snd_soc_component_read(component, b2_reg) << 24); 3144 return value; 3145} 3146 3147static void set_iir_band_coeff(struct snd_soc_component *component, 3148 int iir_idx, int band_idx, uint32_t value) 3149{ 3150 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3151 3152 snd_soc_component_write(component, reg, (value & 0xFF)); 3153 snd_soc_component_write(component, reg, (value >> 8) & 0xFF); 3154 snd_soc_component_write(component, reg, (value >> 16) & 0xFF); 3155 /* Mask top 2 bits, 7-8 are reserved */ 3156 snd_soc_component_write(component, reg, (value >> 24) & 0x3F); 3157} 3158 3159static int wcd934x_put_iir_band_audio_mixer( 3160 struct snd_kcontrol *kcontrol, 3161 struct snd_ctl_elem_value *ucontrol) 3162{ 3163 struct snd_soc_component *component = 3164 snd_soc_kcontrol_component(kcontrol); 3165 struct wcd_iir_filter_ctl *ctl = 3166 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3167 struct soc_bytes_ext *params = &ctl->bytes_ext; 3168 int iir_idx = ctl->iir_idx; 3169 int band_idx = ctl->band_idx; 3170 u32 coeff[BAND_MAX]; 3171 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3172 3173 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); 3174 3175 /* Mask top bit it is reserved */ 3176 /* Updates addr automatically for each B2 write */ 3177 snd_soc_component_write(component, reg, (band_idx * BAND_MAX * 3178 sizeof(uint32_t)) & 0x7F); 3179 3180 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]); 3181 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]); 3182 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]); 3183 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]); 3184 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]); 3185 3186 return 0; 3187} 3188 3189static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol, 3190 struct snd_ctl_elem_value *ucontrol) 3191{ 3192 struct snd_soc_component *component = 3193 snd_soc_kcontrol_component(kcontrol); 3194 struct wcd_iir_filter_ctl *ctl = 3195 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3196 struct soc_bytes_ext *params = &ctl->bytes_ext; 3197 int iir_idx = ctl->iir_idx; 3198 int band_idx = ctl->band_idx; 3199 u32 coeff[BAND_MAX]; 3200 3201 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0); 3202 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1); 3203 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2); 3204 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3); 3205 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4); 3206 3207 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); 3208 3209 return 0; 3210} 3211 3212static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol, 3213 struct snd_ctl_elem_info *ucontrol) 3214{ 3215 struct wcd_iir_filter_ctl *ctl = 3216 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3217 struct soc_bytes_ext *params = &ctl->bytes_ext; 3218 3219 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 3220 ucontrol->count = params->max; 3221 3222 return 0; 3223} 3224 3225static int wcd934x_compander_get(struct snd_kcontrol *kc, 3226 struct snd_ctl_elem_value *ucontrol) 3227{ 3228 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3229 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3230 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3231 3232 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 3233 3234 return 0; 3235} 3236 3237static int wcd934x_compander_set(struct snd_kcontrol *kc, 3238 struct snd_ctl_elem_value *ucontrol) 3239{ 3240 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3241 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3242 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3243 int value = ucontrol->value.integer.value[0]; 3244 int sel; 3245 3246 if (wcd->comp_enabled[comp] == value) 3247 return 0; 3248 3249 wcd->comp_enabled[comp] = value; 3250 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER : 3251 WCD934X_HPH_GAIN_SRC_SEL_REGISTER; 3252 3253 /* Any specific register configuration for compander */ 3254 switch (comp) { 3255 case COMPANDER_1: 3256 /* Set Gain Source Select based on compander enable/disable */ 3257 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN, 3258 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3259 sel); 3260 break; 3261 case COMPANDER_2: 3262 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN, 3263 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3264 sel); 3265 break; 3266 case COMPANDER_3: 3267 case COMPANDER_4: 3268 case COMPANDER_7: 3269 case COMPANDER_8: 3270 break; 3271 default: 3272 return 0; 3273 } 3274 3275 return 1; 3276} 3277 3278static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc, 3279 struct snd_ctl_elem_value *ucontrol) 3280{ 3281 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3282 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3283 3284 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 3285 3286 return 0; 3287} 3288 3289static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc, 3290 struct snd_ctl_elem_value *ucontrol) 3291{ 3292 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3293 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3294 u32 mode_val; 3295 3296 mode_val = ucontrol->value.enumerated.item[0]; 3297 3298 if (mode_val == wcd->hph_mode) 3299 return 0; 3300 3301 if (mode_val == 0) { 3302 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 3303 mode_val = CLS_H_LOHIFI; 3304 } 3305 wcd->hph_mode = mode_val; 3306 3307 return 1; 3308} 3309 3310static int slim_rx_mux_get(struct snd_kcontrol *kc, 3311 struct snd_ctl_elem_value *ucontrol) 3312{ 3313 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 3314 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 3315 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev); 3316 3317 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift]; 3318 3319 return 0; 3320} 3321 3322static int slim_rx_mux_to_dai_id(int mux) 3323{ 3324 int aif_id; 3325 3326 switch (mux) { 3327 case 1: 3328 aif_id = AIF1_PB; 3329 break; 3330 case 2: 3331 aif_id = AIF2_PB; 3332 break; 3333 case 3: 3334 aif_id = AIF3_PB; 3335 break; 3336 case 4: 3337 aif_id = AIF4_PB; 3338 break; 3339 default: 3340 aif_id = -1; 3341 break; 3342 } 3343 3344 return aif_id; 3345} 3346 3347static int slim_rx_mux_put(struct snd_kcontrol *kc, 3348 struct snd_ctl_elem_value *ucontrol) 3349{ 3350 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 3351 struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev); 3352 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3353 struct snd_soc_dapm_update *update = NULL; 3354 struct wcd934x_slim_ch *ch, *c; 3355 u32 port_id = w->shift; 3356 bool found = false; 3357 int mux_idx; 3358 int prev_mux_idx = wcd->rx_port_value[port_id]; 3359 int aif_id; 3360 3361 mux_idx = ucontrol->value.enumerated.item[0]; 3362 3363 if (mux_idx == prev_mux_idx) 3364 return 0; 3365 3366 switch(mux_idx) { 3367 case 0: 3368 aif_id = slim_rx_mux_to_dai_id(prev_mux_idx); 3369 if (aif_id < 0) 3370 return 0; 3371 3372 list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) { 3373 if (ch->port == port_id + WCD934X_RX_START) { 3374 found = true; 3375 list_del_init(&ch->list); 3376 break; 3377 } 3378 } 3379 if (!found) 3380 return 0; 3381 3382 break; 3383 case 1 ... 4: 3384 aif_id = slim_rx_mux_to_dai_id(mux_idx); 3385 if (aif_id < 0) 3386 return 0; 3387 3388 if (list_empty(&wcd->rx_chs[port_id].list)) { 3389 list_add_tail(&wcd->rx_chs[port_id].list, 3390 &wcd->dai[aif_id].slim_ch_list); 3391 } else { 3392 dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id); 3393 return 0; 3394 } 3395 break; 3396 3397 default: 3398 dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx); 3399 goto err; 3400 } 3401 3402 wcd->rx_port_value[port_id] = mux_idx; 3403 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 3404 e, update); 3405 3406 return 1; 3407err: 3408 return -EINVAL; 3409} 3410 3411static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc, 3412 struct snd_ctl_elem_value *ucontrol) 3413{ 3414 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3415 struct snd_soc_component *component; 3416 int reg, val; 3417 3418 component = snd_soc_dapm_kcontrol_component(kc); 3419 val = ucontrol->value.enumerated.item[0]; 3420 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0) 3421 reg = WCD934X_CDC_RX0_RX_PATH_CFG0; 3422 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0) 3423 reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 3424 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0) 3425 reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 3426 else 3427 return -EINVAL; 3428 3429 /* Set Look Ahead Delay */ 3430 if (val) 3431 snd_soc_component_update_bits(component, reg, 3432 WCD934X_RX_DLY_ZN_EN_MASK, 3433 WCD934X_RX_DLY_ZN_ENABLE); 3434 else 3435 snd_soc_component_update_bits(component, reg, 3436 WCD934X_RX_DLY_ZN_EN_MASK, 3437 WCD934X_RX_DLY_ZN_DISABLE); 3438 3439 return snd_soc_dapm_put_enum_double(kc, ucontrol); 3440} 3441 3442static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol, 3443 struct snd_ctl_elem_value *ucontrol) 3444{ 3445 struct snd_soc_component *comp; 3446 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 3447 unsigned int val; 3448 u16 mic_sel_reg = 0; 3449 u8 mic_sel; 3450 3451 comp = snd_soc_dapm_kcontrol_component(kcontrol); 3452 3453 val = ucontrol->value.enumerated.item[0]; 3454 if (val > e->items - 1) 3455 return -EINVAL; 3456 3457 switch (e->reg) { 3458 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 3459 if (e->shift_l == 0) 3460 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0; 3461 else if (e->shift_l == 2) 3462 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0; 3463 else if (e->shift_l == 4) 3464 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0; 3465 break; 3466 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 3467 if (e->shift_l == 0) 3468 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0; 3469 else if (e->shift_l == 2) 3470 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0; 3471 break; 3472 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 3473 if (e->shift_l == 0) 3474 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0; 3475 else if (e->shift_l == 2) 3476 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0; 3477 break; 3478 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 3479 if (e->shift_l == 0) 3480 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0; 3481 else if (e->shift_l == 2) 3482 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0; 3483 break; 3484 default: 3485 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n", 3486 __func__, e->reg); 3487 return -EINVAL; 3488 } 3489 3490 /* ADC: 0, DMIC: 1 */ 3491 mic_sel = val ? 0x0 : 0x1; 3492 if (mic_sel_reg) 3493 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7), 3494 mic_sel << 7); 3495 3496 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 3497} 3498 3499static const struct snd_kcontrol_new rx_int0_2_mux = 3500 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 3501 3502static const struct snd_kcontrol_new rx_int1_2_mux = 3503 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 3504 3505static const struct snd_kcontrol_new rx_int2_2_mux = 3506 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 3507 3508static const struct snd_kcontrol_new rx_int3_2_mux = 3509 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 3510 3511static const struct snd_kcontrol_new rx_int4_2_mux = 3512 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 3513 3514static const struct snd_kcontrol_new rx_int7_2_mux = 3515 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 3516 3517static const struct snd_kcontrol_new rx_int8_2_mux = 3518 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 3519 3520static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 3521 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 3522 3523static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 3524 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 3525 3526static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 3527 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 3528 3529static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 3530 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 3531 3532static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 3533 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 3534 3535static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 3536 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 3537 3538static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 3539 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 3540 3541static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 3542 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 3543 3544static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 3545 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 3546 3547static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 3548 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 3549 3550static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 3551 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 3552 3553static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 3554 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 3555 3556static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 3557 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 3558 3559static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 3560 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 3561 3562static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 3563 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 3564 3565static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 3566 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 3567 3568static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 3569 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 3570 3571static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 3572 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 3573 3574static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 3575 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 3576 3577static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 3578 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 3579 3580static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 3581 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 3582 3583static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = 3584 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum); 3585 3586static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = 3587 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum); 3588 3589static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = 3590 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum); 3591 3592static const struct snd_kcontrol_new rx_int3_mix2_inp_mux = 3593 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum); 3594 3595static const struct snd_kcontrol_new rx_int4_mix2_inp_mux = 3596 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum); 3597 3598static const struct snd_kcontrol_new rx_int7_mix2_inp_mux = 3599 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum); 3600 3601static const struct snd_kcontrol_new iir0_inp0_mux = 3602 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum); 3603static const struct snd_kcontrol_new iir0_inp1_mux = 3604 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum); 3605static const struct snd_kcontrol_new iir0_inp2_mux = 3606 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum); 3607static const struct snd_kcontrol_new iir0_inp3_mux = 3608 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum); 3609 3610static const struct snd_kcontrol_new iir1_inp0_mux = 3611 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum); 3612static const struct snd_kcontrol_new iir1_inp1_mux = 3613 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); 3614static const struct snd_kcontrol_new iir1_inp2_mux = 3615 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum); 3616static const struct snd_kcontrol_new iir1_inp3_mux = 3617 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum); 3618 3619static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = { 3620 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 3621 slim_rx_mux_get, slim_rx_mux_put), 3622 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 3623 slim_rx_mux_get, slim_rx_mux_put), 3624 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 3625 slim_rx_mux_get, slim_rx_mux_put), 3626 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 3627 slim_rx_mux_get, slim_rx_mux_put), 3628 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 3629 slim_rx_mux_get, slim_rx_mux_put), 3630 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 3631 slim_rx_mux_get, slim_rx_mux_put), 3632 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 3633 slim_rx_mux_get, slim_rx_mux_put), 3634 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 3635 slim_rx_mux_get, slim_rx_mux_put), 3636}; 3637 3638static const struct snd_kcontrol_new rx_int1_asrc_switch[] = { 3639 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0), 3640}; 3641 3642static const struct snd_kcontrol_new rx_int2_asrc_switch[] = { 3643 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0), 3644}; 3645 3646static const struct snd_kcontrol_new rx_int3_asrc_switch[] = { 3647 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0), 3648}; 3649 3650static const struct snd_kcontrol_new rx_int4_asrc_switch[] = { 3651 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0), 3652}; 3653 3654static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 3655 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 3656 snd_soc_dapm_get_enum_double, 3657 wcd934x_int_dem_inp_mux_put); 3658 3659static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 3660 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 3661 snd_soc_dapm_get_enum_double, 3662 wcd934x_int_dem_inp_mux_put); 3663 3664static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 3665 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 3666 snd_soc_dapm_get_enum_double, 3667 wcd934x_int_dem_inp_mux_put); 3668 3669static const struct snd_kcontrol_new rx_int0_1_interp_mux = 3670 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum); 3671 3672static const struct snd_kcontrol_new rx_int1_1_interp_mux = 3673 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum); 3674 3675static const struct snd_kcontrol_new rx_int2_1_interp_mux = 3676 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum); 3677 3678static const struct snd_kcontrol_new rx_int3_1_interp_mux = 3679 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum); 3680 3681static const struct snd_kcontrol_new rx_int4_1_interp_mux = 3682 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum); 3683 3684static const struct snd_kcontrol_new rx_int7_1_interp_mux = 3685 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum); 3686 3687static const struct snd_kcontrol_new rx_int8_1_interp_mux = 3688 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum); 3689 3690static const struct snd_kcontrol_new rx_int0_2_interp_mux = 3691 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum); 3692 3693static const struct snd_kcontrol_new rx_int1_2_interp_mux = 3694 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum); 3695 3696static const struct snd_kcontrol_new rx_int2_2_interp_mux = 3697 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum); 3698 3699static const struct snd_kcontrol_new rx_int3_2_interp_mux = 3700 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum); 3701 3702static const struct snd_kcontrol_new rx_int4_2_interp_mux = 3703 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum); 3704 3705static const struct snd_kcontrol_new rx_int7_2_interp_mux = 3706 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum); 3707 3708static const struct snd_kcontrol_new rx_int8_2_interp_mux = 3709 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum); 3710 3711static const struct snd_kcontrol_new tx_dmic_mux0 = 3712 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 3713 3714static const struct snd_kcontrol_new tx_dmic_mux1 = 3715 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 3716 3717static const struct snd_kcontrol_new tx_dmic_mux2 = 3718 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 3719 3720static const struct snd_kcontrol_new tx_dmic_mux3 = 3721 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 3722 3723static const struct snd_kcontrol_new tx_dmic_mux4 = 3724 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 3725 3726static const struct snd_kcontrol_new tx_dmic_mux5 = 3727 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 3728 3729static const struct snd_kcontrol_new tx_dmic_mux6 = 3730 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 3731 3732static const struct snd_kcontrol_new tx_dmic_mux7 = 3733 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 3734 3735static const struct snd_kcontrol_new tx_dmic_mux8 = 3736 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 3737 3738static const struct snd_kcontrol_new tx_amic_mux0 = 3739 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 3740 3741static const struct snd_kcontrol_new tx_amic_mux1 = 3742 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 3743 3744static const struct snd_kcontrol_new tx_amic_mux2 = 3745 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 3746 3747static const struct snd_kcontrol_new tx_amic_mux3 = 3748 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 3749 3750static const struct snd_kcontrol_new tx_amic_mux4 = 3751 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 3752 3753static const struct snd_kcontrol_new tx_amic_mux5 = 3754 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 3755 3756static const struct snd_kcontrol_new tx_amic_mux6 = 3757 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 3758 3759static const struct snd_kcontrol_new tx_amic_mux7 = 3760 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 3761 3762static const struct snd_kcontrol_new tx_amic_mux8 = 3763 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 3764 3765static const struct snd_kcontrol_new tx_amic4_5 = 3766 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum); 3767 3768static const struct snd_kcontrol_new tx_adc_mux0_mux = 3769 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum, 3770 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3771static const struct snd_kcontrol_new tx_adc_mux1_mux = 3772 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum, 3773 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3774static const struct snd_kcontrol_new tx_adc_mux2_mux = 3775 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum, 3776 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3777static const struct snd_kcontrol_new tx_adc_mux3_mux = 3778 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum, 3779 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3780static const struct snd_kcontrol_new tx_adc_mux4_mux = 3781 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum, 3782 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3783static const struct snd_kcontrol_new tx_adc_mux5_mux = 3784 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum, 3785 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3786static const struct snd_kcontrol_new tx_adc_mux6_mux = 3787 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum, 3788 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3789static const struct snd_kcontrol_new tx_adc_mux7_mux = 3790 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum, 3791 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3792static const struct snd_kcontrol_new tx_adc_mux8_mux = 3793 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum, 3794 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3795 3796static const struct snd_kcontrol_new cdc_if_tx0_mux = 3797 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum); 3798static const struct snd_kcontrol_new cdc_if_tx1_mux = 3799 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum); 3800static const struct snd_kcontrol_new cdc_if_tx2_mux = 3801 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum); 3802static const struct snd_kcontrol_new cdc_if_tx3_mux = 3803 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum); 3804static const struct snd_kcontrol_new cdc_if_tx4_mux = 3805 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum); 3806static const struct snd_kcontrol_new cdc_if_tx5_mux = 3807 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum); 3808static const struct snd_kcontrol_new cdc_if_tx6_mux = 3809 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum); 3810static const struct snd_kcontrol_new cdc_if_tx7_mux = 3811 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum); 3812static const struct snd_kcontrol_new cdc_if_tx8_mux = 3813 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum); 3814static const struct snd_kcontrol_new cdc_if_tx9_mux = 3815 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum); 3816static const struct snd_kcontrol_new cdc_if_tx10_mux = 3817 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum); 3818static const struct snd_kcontrol_new cdc_if_tx11_mux = 3819 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum); 3820static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux = 3821 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum); 3822static const struct snd_kcontrol_new cdc_if_tx13_mux = 3823 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum); 3824static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux = 3825 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum); 3826 3827static int slim_tx_mixer_get(struct snd_kcontrol *kc, 3828 struct snd_ctl_elem_value *ucontrol) 3829{ 3830 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 3831 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev); 3832 struct soc_mixer_control *mixer = 3833 (struct soc_mixer_control *)kc->private_value; 3834 int port_id = mixer->shift; 3835 3836 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id]; 3837 3838 return 0; 3839} 3840 3841static int slim_tx_mixer_put(struct snd_kcontrol *kc, 3842 struct snd_ctl_elem_value *ucontrol) 3843{ 3844 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 3845 struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev); 3846 struct snd_soc_dapm_update *update = NULL; 3847 struct soc_mixer_control *mixer = 3848 (struct soc_mixer_control *)kc->private_value; 3849 int enable = ucontrol->value.integer.value[0]; 3850 struct wcd934x_slim_ch *ch, *c; 3851 int dai_id = widget->shift; 3852 int port_id = mixer->shift; 3853 3854 /* only add to the list if value not set */ 3855 if (enable == wcd->tx_port_value[port_id]) 3856 return 0; 3857 3858 if (enable) { 3859 if (list_empty(&wcd->tx_chs[port_id].list)) { 3860 list_add_tail(&wcd->tx_chs[port_id].list, 3861 &wcd->dai[dai_id].slim_ch_list); 3862 } else { 3863 dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id); 3864 return 0; 3865 } 3866 } else { 3867 bool found = false; 3868 3869 list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) { 3870 if (ch->port == port_id) { 3871 found = true; 3872 list_del_init(&wcd->tx_chs[port_id].list); 3873 break; 3874 } 3875 } 3876 if (!found) 3877 return 0; 3878 } 3879 3880 wcd->tx_port_value[port_id] = enable; 3881 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 3882 3883 return 1; 3884} 3885 3886static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = { 3887 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3888 slim_tx_mixer_get, slim_tx_mixer_put), 3889 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3890 slim_tx_mixer_get, slim_tx_mixer_put), 3891 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3892 slim_tx_mixer_get, slim_tx_mixer_put), 3893 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3894 slim_tx_mixer_get, slim_tx_mixer_put), 3895 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3896 slim_tx_mixer_get, slim_tx_mixer_put), 3897 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3898 slim_tx_mixer_get, slim_tx_mixer_put), 3899 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3900 slim_tx_mixer_get, slim_tx_mixer_put), 3901 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3902 slim_tx_mixer_get, slim_tx_mixer_put), 3903 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3904 slim_tx_mixer_get, slim_tx_mixer_put), 3905 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3906 slim_tx_mixer_get, slim_tx_mixer_put), 3907 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3908 slim_tx_mixer_get, slim_tx_mixer_put), 3909 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3910 slim_tx_mixer_get, slim_tx_mixer_put), 3911 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3912 slim_tx_mixer_get, slim_tx_mixer_put), 3913}; 3914 3915static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = { 3916 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3917 slim_tx_mixer_get, slim_tx_mixer_put), 3918 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3919 slim_tx_mixer_get, slim_tx_mixer_put), 3920 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3921 slim_tx_mixer_get, slim_tx_mixer_put), 3922 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3923 slim_tx_mixer_get, slim_tx_mixer_put), 3924 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3925 slim_tx_mixer_get, slim_tx_mixer_put), 3926 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3927 slim_tx_mixer_get, slim_tx_mixer_put), 3928 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3929 slim_tx_mixer_get, slim_tx_mixer_put), 3930 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3931 slim_tx_mixer_get, slim_tx_mixer_put), 3932 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3933 slim_tx_mixer_get, slim_tx_mixer_put), 3934 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3935 slim_tx_mixer_get, slim_tx_mixer_put), 3936 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3937 slim_tx_mixer_get, slim_tx_mixer_put), 3938 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3939 slim_tx_mixer_get, slim_tx_mixer_put), 3940 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3941 slim_tx_mixer_get, slim_tx_mixer_put), 3942}; 3943 3944static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = { 3945 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3946 slim_tx_mixer_get, slim_tx_mixer_put), 3947 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3948 slim_tx_mixer_get, slim_tx_mixer_put), 3949 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3950 slim_tx_mixer_get, slim_tx_mixer_put), 3951 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3952 slim_tx_mixer_get, slim_tx_mixer_put), 3953 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3954 slim_tx_mixer_get, slim_tx_mixer_put), 3955 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3956 slim_tx_mixer_get, slim_tx_mixer_put), 3957 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3958 slim_tx_mixer_get, slim_tx_mixer_put), 3959 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3960 slim_tx_mixer_get, slim_tx_mixer_put), 3961 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3962 slim_tx_mixer_get, slim_tx_mixer_put), 3963 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3964 slim_tx_mixer_get, slim_tx_mixer_put), 3965 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3966 slim_tx_mixer_get, slim_tx_mixer_put), 3967 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3968 slim_tx_mixer_get, slim_tx_mixer_put), 3969 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3970 slim_tx_mixer_get, slim_tx_mixer_put), 3971}; 3972 3973static const struct snd_kcontrol_new wcd934x_snd_controls[] = { 3974 /* Gain Controls */ 3975 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain), 3976 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain), 3977 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain), 3978 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER, 3979 3, 16, 1, line_gain), 3980 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER, 3981 3, 16, 1, line_gain), 3982 3983 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain), 3984 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain), 3985 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain), 3986 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain), 3987 3988 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL, 3989 -84, 40, digital_gain), /* -84dB min - 40dB max */ 3990 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL, 3991 -84, 40, digital_gain), 3992 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL, 3993 -84, 40, digital_gain), 3994 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL, 3995 -84, 40, digital_gain), 3996 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL, 3997 -84, 40, digital_gain), 3998 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL, 3999 -84, 40, digital_gain), 4000 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL, 4001 -84, 40, digital_gain), 4002 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", 4003 WCD934X_CDC_RX0_RX_VOL_MIX_CTL, 4004 -84, 40, digital_gain), 4005 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", 4006 WCD934X_CDC_RX1_RX_VOL_MIX_CTL, 4007 -84, 40, digital_gain), 4008 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", 4009 WCD934X_CDC_RX2_RX_VOL_MIX_CTL, 4010 -84, 40, digital_gain), 4011 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", 4012 WCD934X_CDC_RX3_RX_VOL_MIX_CTL, 4013 -84, 40, digital_gain), 4014 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", 4015 WCD934X_CDC_RX4_RX_VOL_MIX_CTL, 4016 -84, 40, digital_gain), 4017 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", 4018 WCD934X_CDC_RX7_RX_VOL_MIX_CTL, 4019 -84, 40, digital_gain), 4020 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", 4021 WCD934X_CDC_RX8_RX_VOL_MIX_CTL, 4022 -84, 40, digital_gain), 4023 4024 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL, 4025 -84, 40, digital_gain), 4026 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL, 4027 -84, 40, digital_gain), 4028 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL, 4029 -84, 40, digital_gain), 4030 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL, 4031 -84, 40, digital_gain), 4032 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL, 4033 -84, 40, digital_gain), 4034 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL, 4035 -84, 40, digital_gain), 4036 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL, 4037 -84, 40, digital_gain), 4038 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL, 4039 -84, 40, digital_gain), 4040 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL, 4041 -84, 40, digital_gain), 4042 4043 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume", 4044 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40, 4045 digital_gain), 4046 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume", 4047 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40, 4048 digital_gain), 4049 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume", 4050 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40, 4051 digital_gain), 4052 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume", 4053 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40, 4054 digital_gain), 4055 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume", 4056 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40, 4057 digital_gain), 4058 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", 4059 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40, 4060 digital_gain), 4061 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", 4062 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40, 4063 digital_gain), 4064 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", 4065 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40, 4066 digital_gain), 4067 4068 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 4069 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 4070 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 4071 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 4072 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 4073 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 4074 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 4075 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 4076 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 4077 4078 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 4079 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 4080 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 4081 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 4082 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 4083 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 4084 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 4085 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 4086 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 4087 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 4088 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 4089 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 4090 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 4091 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 4092 4093 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 4094 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put), 4095 4096 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4097 0, 1, 0), 4098 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4099 1, 1, 0), 4100 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4101 2, 1, 0), 4102 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4103 3, 1, 0), 4104 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4105 4, 1, 0), 4106 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4107 0, 1, 0), 4108 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4109 1, 1, 0), 4110 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4111 2, 1, 0), 4112 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4113 3, 1, 0), 4114 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4115 4, 1, 0), 4116 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1), 4117 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2), 4118 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3), 4119 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4), 4120 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5), 4121 4122 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1), 4123 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2), 4124 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3), 4125 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4), 4126 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5), 4127 4128 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 4129 wcd934x_compander_get, wcd934x_compander_set), 4130 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 4131 wcd934x_compander_get, wcd934x_compander_set), 4132 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 4133 wcd934x_compander_get, wcd934x_compander_set), 4134 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 4135 wcd934x_compander_get, wcd934x_compander_set), 4136 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 4137 wcd934x_compander_get, wcd934x_compander_set), 4138 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 4139 wcd934x_compander_get, wcd934x_compander_set), 4140}; 4141 4142static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 4143 struct snd_soc_component *component) 4144{ 4145 int port_num = 0; 4146 unsigned short reg = 0; 4147 unsigned int val = 0; 4148 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 4149 struct wcd934x_slim_ch *ch; 4150 4151 list_for_each_entry(ch, &dai->slim_ch_list, list) { 4152 if (ch->port >= WCD934X_RX_START) { 4153 port_num = ch->port - WCD934X_RX_START; 4154 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 4155 } else { 4156 port_num = ch->port; 4157 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 4158 } 4159 4160 regmap_read(wcd->if_regmap, reg, &val); 4161 if (!(val & BIT(port_num % 8))) 4162 regmap_write(wcd->if_regmap, reg, 4163 val | BIT(port_num % 8)); 4164 } 4165} 4166 4167static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w, 4168 struct snd_kcontrol *kc, int event) 4169{ 4170 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4171 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4172 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 4173 4174 switch (event) { 4175 case SND_SOC_DAPM_POST_PMU: 4176 wcd934x_codec_enable_int_port(dai, comp); 4177 break; 4178 } 4179 4180 return 0; 4181} 4182 4183static void wcd934x_codec_hd2_control(struct snd_soc_component *component, 4184 u16 interp_idx, int event) 4185{ 4186 u16 hd2_scale_reg; 4187 u16 hd2_enable_reg = 0; 4188 4189 switch (interp_idx) { 4190 case INTERP_HPHL: 4191 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3; 4192 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 4193 break; 4194 case INTERP_HPHR: 4195 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3; 4196 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 4197 break; 4198 default: 4199 return; 4200 } 4201 4202 if (SND_SOC_DAPM_EVENT_ON(event)) { 4203 snd_soc_component_update_bits(component, hd2_scale_reg, 4204 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4205 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125); 4206 snd_soc_component_update_bits(component, hd2_enable_reg, 4207 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4208 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE); 4209 } 4210 4211 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4212 snd_soc_component_update_bits(component, hd2_enable_reg, 4213 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4214 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE); 4215 snd_soc_component_update_bits(component, hd2_scale_reg, 4216 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4217 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 4218 } 4219} 4220 4221static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp, 4222 u16 interp_idx, int event) 4223{ 4224 u8 hph_dly_mask; 4225 u16 hph_lut_bypass_reg = 0; 4226 4227 switch (interp_idx) { 4228 case INTERP_HPHL: 4229 hph_dly_mask = 1; 4230 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT; 4231 break; 4232 case INTERP_HPHR: 4233 hph_dly_mask = 2; 4234 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT; 4235 break; 4236 default: 4237 return; 4238 } 4239 4240 if (SND_SOC_DAPM_EVENT_ON(event)) { 4241 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4242 hph_dly_mask, 0x0); 4243 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4244 WCD934X_HPH_LUT_BYPASS_MASK, 4245 WCD934X_HPH_LUT_BYPASS_ENABLE); 4246 } 4247 4248 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4249 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4250 hph_dly_mask, hph_dly_mask); 4251 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4252 WCD934X_HPH_LUT_BYPASS_MASK, 4253 WCD934X_HPH_LUT_BYPASS_DISABLE); 4254 } 4255} 4256 4257static int wcd934x_config_compander(struct snd_soc_component *comp, 4258 int interp_n, int event) 4259{ 4260 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4261 int compander; 4262 u16 comp_ctl0_reg, rx_path_cfg0_reg; 4263 4264 /* EAR does not have compander */ 4265 if (!interp_n) 4266 return 0; 4267 4268 compander = interp_n - 1; 4269 if (!wcd->comp_enabled[compander]) 4270 return 0; 4271 4272 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8); 4273 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20); 4274 4275 switch (event) { 4276 case SND_SOC_DAPM_PRE_PMU: 4277 /* Enable Compander Clock */ 4278 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4279 WCD934X_COMP_CLK_EN_MASK, 4280 WCD934X_COMP_CLK_ENABLE); 4281 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4282 WCD934X_COMP_SOFT_RST_MASK, 4283 WCD934X_COMP_SOFT_RST_ENABLE); 4284 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4285 WCD934X_COMP_SOFT_RST_MASK, 4286 WCD934X_COMP_SOFT_RST_DISABLE); 4287 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4288 WCD934X_HPH_CMP_EN_MASK, 4289 WCD934X_HPH_CMP_ENABLE); 4290 break; 4291 case SND_SOC_DAPM_POST_PMD: 4292 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4293 WCD934X_HPH_CMP_EN_MASK, 4294 WCD934X_HPH_CMP_DISABLE); 4295 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4296 WCD934X_COMP_HALT_MASK, 4297 WCD934X_COMP_HALT); 4298 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4299 WCD934X_COMP_SOFT_RST_MASK, 4300 WCD934X_COMP_SOFT_RST_ENABLE); 4301 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4302 WCD934X_COMP_SOFT_RST_MASK, 4303 WCD934X_COMP_SOFT_RST_DISABLE); 4304 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4305 WCD934X_COMP_CLK_EN_MASK, 0x0); 4306 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4307 WCD934X_COMP_SOFT_RST_MASK, 0x0); 4308 break; 4309 } 4310 4311 return 0; 4312} 4313 4314static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w, 4315 struct snd_kcontrol *kc, int event) 4316{ 4317 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4318 int interp_idx = w->shift; 4319 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20); 4320 4321 switch (event) { 4322 case SND_SOC_DAPM_PRE_PMU: 4323 /* Clk enable */ 4324 snd_soc_component_update_bits(comp, main_reg, 4325 WCD934X_RX_CLK_EN_MASK, 4326 WCD934X_RX_CLK_ENABLE); 4327 wcd934x_codec_hd2_control(comp, interp_idx, event); 4328 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4329 wcd934x_config_compander(comp, interp_idx, event); 4330 break; 4331 case SND_SOC_DAPM_POST_PMD: 4332 wcd934x_config_compander(comp, interp_idx, event); 4333 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4334 wcd934x_codec_hd2_control(comp, interp_idx, event); 4335 /* Clk Disable */ 4336 snd_soc_component_update_bits(comp, main_reg, 4337 WCD934X_RX_CLK_EN_MASK, 0); 4338 /* Reset enable and disable */ 4339 snd_soc_component_update_bits(comp, main_reg, 4340 WCD934X_RX_RESET_MASK, 4341 WCD934X_RX_RESET_ENABLE); 4342 snd_soc_component_update_bits(comp, main_reg, 4343 WCD934X_RX_RESET_MASK, 4344 WCD934X_RX_RESET_DISABLE); 4345 /* Reset rate to 48K*/ 4346 snd_soc_component_update_bits(comp, main_reg, 4347 WCD934X_RX_PCM_RATE_MASK, 4348 WCD934X_RX_PCM_RATE_F_48K); 4349 break; 4350 } 4351 4352 return 0; 4353} 4354 4355static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 4356 struct snd_kcontrol *kc, int event) 4357{ 4358 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4359 int offset_val = 0; 4360 u16 gain_reg, mix_reg; 4361 int val = 0; 4362 4363 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL + 4364 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4365 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL + 4366 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4367 4368 switch (event) { 4369 case SND_SOC_DAPM_PRE_PMU: 4370 /* Clk enable */ 4371 snd_soc_component_update_bits(comp, mix_reg, 4372 WCD934X_CDC_RX_MIX_CLK_EN_MASK, 4373 WCD934X_CDC_RX_MIX_CLK_ENABLE); 4374 break; 4375 4376 case SND_SOC_DAPM_POST_PMU: 4377 val = snd_soc_component_read(comp, gain_reg); 4378 val += offset_val; 4379 snd_soc_component_write(comp, gain_reg, val); 4380 break; 4381 } 4382 4383 return 0; 4384} 4385 4386static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w, 4387 struct snd_kcontrol *kcontrol, int event) 4388{ 4389 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4390 int reg = w->reg; 4391 4392 switch (event) { 4393 case SND_SOC_DAPM_POST_PMU: 4394 /* B1 GAIN */ 4395 snd_soc_component_write(comp, reg, 4396 snd_soc_component_read(comp, reg)); 4397 /* B2 GAIN */ 4398 reg++; 4399 snd_soc_component_write(comp, reg, 4400 snd_soc_component_read(comp, reg)); 4401 /* B3 GAIN */ 4402 reg++; 4403 snd_soc_component_write(comp, reg, 4404 snd_soc_component_read(comp, reg)); 4405 /* B4 GAIN */ 4406 reg++; 4407 snd_soc_component_write(comp, reg, 4408 snd_soc_component_read(comp, reg)); 4409 /* B5 GAIN */ 4410 reg++; 4411 snd_soc_component_write(comp, reg, 4412 snd_soc_component_read(comp, reg)); 4413 break; 4414 default: 4415 break; 4416 } 4417 return 0; 4418} 4419 4420static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w, 4421 struct snd_kcontrol *kcontrol, 4422 int event) 4423{ 4424 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4425 u16 gain_reg; 4426 4427 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift * 4428 WCD934X_RX_PATH_CTL_OFFSET); 4429 4430 switch (event) { 4431 case SND_SOC_DAPM_POST_PMU: 4432 snd_soc_component_write(comp, gain_reg, 4433 snd_soc_component_read(comp, gain_reg)); 4434 break; 4435 } 4436 4437 return 0; 4438} 4439 4440static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 4441 struct snd_kcontrol *kc, int event) 4442{ 4443 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4444 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4445 4446 switch (event) { 4447 case SND_SOC_DAPM_PRE_PMU: 4448 /* Disable AutoChop timer during power up */ 4449 snd_soc_component_update_bits(comp, 4450 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4451 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4452 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4453 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4454 4455 break; 4456 case SND_SOC_DAPM_POST_PMD: 4457 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4458 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4459 break; 4460 } 4461 4462 return 0; 4463} 4464 4465static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 4466 struct snd_kcontrol *kcontrol, 4467 int event) 4468{ 4469 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4470 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4471 int hph_mode = wcd->hph_mode; 4472 u8 dem_inp; 4473 4474 switch (event) { 4475 case SND_SOC_DAPM_PRE_PMU: 4476 /* Read DEM INP Select */ 4477 dem_inp = snd_soc_component_read(comp, 4478 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03; 4479 4480 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4481 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4482 return -EINVAL; 4483 } 4484 if (hph_mode != CLS_H_LP) 4485 /* Ripple freq control enable */ 4486 snd_soc_component_update_bits(comp, 4487 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4488 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4489 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4490 /* Disable AutoChop timer during power up */ 4491 snd_soc_component_update_bits(comp, 4492 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4493 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4494 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4495 WCD_CLSH_STATE_HPHL, hph_mode); 4496 4497 break; 4498 case SND_SOC_DAPM_POST_PMD: 4499 /* 1000us required as per HW requirement */ 4500 usleep_range(1000, 1100); 4501 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4502 WCD_CLSH_STATE_HPHL, hph_mode); 4503 if (hph_mode != CLS_H_LP) 4504 /* Ripple freq control disable */ 4505 snd_soc_component_update_bits(comp, 4506 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4507 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4508 4509 break; 4510 default: 4511 break; 4512 } 4513 4514 return 0; 4515} 4516 4517static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 4518 struct snd_kcontrol *kcontrol, 4519 int event) 4520{ 4521 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4522 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4523 int hph_mode = wcd->hph_mode; 4524 u8 dem_inp; 4525 4526 switch (event) { 4527 case SND_SOC_DAPM_PRE_PMU: 4528 dem_inp = snd_soc_component_read(comp, 4529 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03; 4530 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4531 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4532 return -EINVAL; 4533 } 4534 if (hph_mode != CLS_H_LP) 4535 /* Ripple freq control enable */ 4536 snd_soc_component_update_bits(comp, 4537 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4538 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4539 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4540 /* Disable AutoChop timer during power up */ 4541 snd_soc_component_update_bits(comp, 4542 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4543 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4544 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4545 WCD_CLSH_STATE_HPHR, 4546 hph_mode); 4547 break; 4548 case SND_SOC_DAPM_POST_PMD: 4549 /* 1000us required as per HW requirement */ 4550 usleep_range(1000, 1100); 4551 4552 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4553 WCD_CLSH_STATE_HPHR, hph_mode); 4554 if (hph_mode != CLS_H_LP) 4555 /* Ripple freq control disable */ 4556 snd_soc_component_update_bits(comp, 4557 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4558 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4559 break; 4560 default: 4561 break; 4562 } 4563 4564 return 0; 4565} 4566 4567static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 4568 struct snd_kcontrol *kc, int event) 4569{ 4570 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4571 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4572 4573 switch (event) { 4574 case SND_SOC_DAPM_PRE_PMU: 4575 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4576 WCD_CLSH_STATE_LO, CLS_AB); 4577 break; 4578 case SND_SOC_DAPM_POST_PMD: 4579 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4580 WCD_CLSH_STATE_LO, CLS_AB); 4581 break; 4582 } 4583 4584 return 0; 4585} 4586 4587static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 4588 struct snd_kcontrol *kcontrol, 4589 int event) 4590{ 4591 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4592 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4593 4594 switch (event) { 4595 case SND_SOC_DAPM_POST_PMU: 4596 /* 4597 * 7ms sleep is required after PA is enabled as per 4598 * HW requirement. If compander is disabled, then 4599 * 20ms delay is needed. 4600 */ 4601 usleep_range(20000, 20100); 4602 4603 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4604 WCD934X_HPH_OCP_DET_MASK, 4605 WCD934X_HPH_OCP_DET_ENABLE); 4606 /* Remove Mute on primary path */ 4607 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4608 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4609 0); 4610 /* Enable GM3 boost */ 4611 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4612 WCD934X_HPH_GM3_BOOST_EN_MASK, 4613 WCD934X_HPH_GM3_BOOST_ENABLE); 4614 /* Enable AutoChop timer at the end of power up */ 4615 snd_soc_component_update_bits(comp, 4616 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4617 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4618 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4619 /* Remove mix path mute */ 4620 snd_soc_component_update_bits(comp, 4621 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4622 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00); 4623 break; 4624 case SND_SOC_DAPM_PRE_PMD: 4625 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4626 /* Enable DSD Mute before PA disable */ 4627 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4628 WCD934X_HPH_OCP_DET_MASK, 4629 WCD934X_HPH_OCP_DET_DISABLE); 4630 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4631 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4632 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4633 snd_soc_component_update_bits(comp, 4634 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4635 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4636 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4637 break; 4638 case SND_SOC_DAPM_POST_PMD: 4639 /* 4640 * 5ms sleep is required after PA disable. If compander is 4641 * disabled, then 20ms delay is needed after PA disable. 4642 */ 4643 usleep_range(20000, 20100); 4644 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4645 break; 4646 } 4647 4648 return 0; 4649} 4650 4651static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 4652 struct snd_kcontrol *kcontrol, 4653 int event) 4654{ 4655 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4656 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4657 4658 switch (event) { 4659 case SND_SOC_DAPM_POST_PMU: 4660 /* 4661 * 7ms sleep is required after PA is enabled as per 4662 * HW requirement. If compander is disabled, then 4663 * 20ms delay is needed. 4664 */ 4665 usleep_range(20000, 20100); 4666 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4667 WCD934X_HPH_OCP_DET_MASK, 4668 WCD934X_HPH_OCP_DET_ENABLE); 4669 /* Remove mute */ 4670 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4671 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4672 0); 4673 /* Enable GM3 boost */ 4674 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4675 WCD934X_HPH_GM3_BOOST_EN_MASK, 4676 WCD934X_HPH_GM3_BOOST_ENABLE); 4677 /* Enable AutoChop timer at the end of power up */ 4678 snd_soc_component_update_bits(comp, 4679 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4680 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4681 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4682 /* Remove mix path mute if it is enabled */ 4683 if ((snd_soc_component_read(comp, 4684 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10) 4685 snd_soc_component_update_bits(comp, 4686 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4687 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4688 WCD934X_CDC_RX_PGA_MUTE_DISABLE); 4689 break; 4690 case SND_SOC_DAPM_PRE_PMD: 4691 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 4692 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4693 WCD934X_HPH_OCP_DET_MASK, 4694 WCD934X_HPH_OCP_DET_DISABLE); 4695 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4696 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4697 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4698 snd_soc_component_update_bits(comp, 4699 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4700 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4701 WCD934X_CDC_RX_PGA_MUTE_ENABLE); 4702 break; 4703 case SND_SOC_DAPM_POST_PMD: 4704 /* 4705 * 5ms sleep is required after PA disable. If compander is 4706 * disabled, then 20ms delay is needed after PA disable. 4707 */ 4708 usleep_range(20000, 20100); 4709 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 4710 break; 4711 } 4712 4713 return 0; 4714} 4715 4716static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp, 4717 unsigned int dmic, 4718 struct wcd934x_codec *wcd) 4719{ 4720 u8 tx_stream_fs; 4721 u8 adc_mux_index = 0, adc_mux_sel = 0; 4722 bool dec_found = false; 4723 u16 adc_mux_ctl_reg, tx_fs_reg; 4724 u32 dmic_fs; 4725 4726 while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) { 4727 if (adc_mux_index < 4) { 4728 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4729 (adc_mux_index * 2); 4730 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) { 4731 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4732 adc_mux_index - 4; 4733 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) { 4734 ++adc_mux_index; 4735 continue; 4736 } 4737 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg) 4738 & 0xF8) >> 3) - 1; 4739 4740 if (adc_mux_sel == dmic) { 4741 dec_found = true; 4742 break; 4743 } 4744 4745 ++adc_mux_index; 4746 } 4747 4748 if (dec_found && adc_mux_index <= 8) { 4749 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index); 4750 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F; 4751 if (tx_stream_fs <= 4) 4752 dmic_fs = min(wcd->dmic_sample_rate, WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ); 4753 else 4754 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 4755 } else { 4756 dmic_fs = wcd->dmic_sample_rate; 4757 } 4758 4759 return dmic_fs; 4760} 4761 4762static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp, 4763 u32 mclk_rate, u32 dmic_clk_rate) 4764{ 4765 u32 div_factor; 4766 u8 dmic_ctl_val; 4767 4768 /* Default value to return in case of error */ 4769 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ) 4770 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4771 else 4772 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4773 4774 if (dmic_clk_rate == 0) { 4775 dev_err(comp->dev, 4776 "%s: dmic_sample_rate cannot be 0\n", 4777 __func__); 4778 goto done; 4779 } 4780 4781 div_factor = mclk_rate / dmic_clk_rate; 4782 switch (div_factor) { 4783 case 2: 4784 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4785 break; 4786 case 3: 4787 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4788 break; 4789 case 4: 4790 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4; 4791 break; 4792 case 6: 4793 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6; 4794 break; 4795 case 8: 4796 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8; 4797 break; 4798 case 16: 4799 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16; 4800 break; 4801 default: 4802 dev_err(comp->dev, 4803 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 4804 __func__, div_factor, mclk_rate, dmic_clk_rate); 4805 break; 4806 } 4807 4808done: 4809 return dmic_ctl_val; 4810} 4811 4812static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 4813 struct snd_kcontrol *kcontrol, int event) 4814{ 4815 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4816 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4817 u8 dmic_clk_en = 0x01; 4818 u16 dmic_clk_reg; 4819 s32 *dmic_clk_cnt; 4820 u8 dmic_rate_val, dmic_rate_shift = 1; 4821 unsigned int dmic; 4822 u32 dmic_sample_rate; 4823 int ret; 4824 char *wname; 4825 4826 wname = strpbrk(w->name, "012345"); 4827 if (!wname) { 4828 dev_err(comp->dev, "%s: widget not found\n", __func__); 4829 return -EINVAL; 4830 } 4831 4832 ret = kstrtouint(wname, 10, &dmic); 4833 if (ret < 0) { 4834 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 4835 __func__); 4836 return -EINVAL; 4837 } 4838 4839 switch (dmic) { 4840 case 0: 4841 case 1: 4842 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt; 4843 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL; 4844 break; 4845 case 2: 4846 case 3: 4847 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt; 4848 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL; 4849 break; 4850 case 4: 4851 case 5: 4852 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt; 4853 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL; 4854 break; 4855 default: 4856 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 4857 __func__); 4858 return -EINVAL; 4859 } 4860 4861 switch (event) { 4862 case SND_SOC_DAPM_PRE_PMU: 4863 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic, 4864 wcd); 4865 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate, 4866 dmic_sample_rate); 4867 (*dmic_clk_cnt)++; 4868 if (*dmic_clk_cnt == 1) { 4869 dmic_rate_val = dmic_rate_val << dmic_rate_shift; 4870 snd_soc_component_update_bits(comp, dmic_clk_reg, 4871 WCD934X_DMIC_RATE_MASK, 4872 dmic_rate_val); 4873 snd_soc_component_update_bits(comp, dmic_clk_reg, 4874 dmic_clk_en, dmic_clk_en); 4875 } 4876 4877 break; 4878 case SND_SOC_DAPM_POST_PMD: 4879 (*dmic_clk_cnt)--; 4880 if (*dmic_clk_cnt == 0) 4881 snd_soc_component_update_bits(comp, dmic_clk_reg, 4882 dmic_clk_en, 0); 4883 break; 4884 } 4885 4886 return 0; 4887} 4888 4889static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp, 4890 int adc_mux_n) 4891{ 4892 u16 mask, shift, adc_mux_in_reg; 4893 u16 amic_mux_sel_reg; 4894 bool is_amic; 4895 4896 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX || 4897 adc_mux_n == WCD934X_INVALID_ADC_MUX) 4898 return 0; 4899 4900 if (adc_mux_n < 3) { 4901 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4902 adc_mux_n; 4903 mask = 0x03; 4904 shift = 0; 4905 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4906 2 * adc_mux_n; 4907 } else if (adc_mux_n < 4) { 4908 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4909 mask = 0x03; 4910 shift = 0; 4911 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4912 2 * adc_mux_n; 4913 } else if (adc_mux_n < 7) { 4914 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4915 (adc_mux_n - 4); 4916 mask = 0x0C; 4917 shift = 2; 4918 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4919 adc_mux_n - 4; 4920 } else if (adc_mux_n < 8) { 4921 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4922 mask = 0x0C; 4923 shift = 2; 4924 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4925 adc_mux_n - 4; 4926 } else if (adc_mux_n < 12) { 4927 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4928 ((adc_mux_n == 8) ? (adc_mux_n - 8) : 4929 (adc_mux_n - 9)); 4930 mask = 0x30; 4931 shift = 4; 4932 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4933 adc_mux_n - 4; 4934 } else if (adc_mux_n < 13) { 4935 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4936 mask = 0x30; 4937 shift = 4; 4938 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4939 adc_mux_n - 4; 4940 } else { 4941 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1; 4942 mask = 0xC0; 4943 shift = 6; 4944 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4945 adc_mux_n - 4; 4946 } 4947 4948 is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg) 4949 & mask) >> shift) == 1); 4950 if (!is_amic) 4951 return 0; 4952 4953 return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07; 4954} 4955 4956static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 4957 int amic) 4958{ 4959 u16 pwr_level_reg = 0; 4960 4961 switch (amic) { 4962 case 1: 4963 case 2: 4964 pwr_level_reg = WCD934X_ANA_AMIC1; 4965 break; 4966 4967 case 3: 4968 case 4: 4969 pwr_level_reg = WCD934X_ANA_AMIC3; 4970 break; 4971 default: 4972 break; 4973 } 4974 4975 return pwr_level_reg; 4976} 4977 4978static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w, 4979 struct snd_kcontrol *kcontrol, int event) 4980{ 4981 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4982 unsigned int decimator; 4983 char *dec_adc_mux_name = NULL; 4984 char *widget_name = NULL; 4985 char *wname; 4986 int ret = 0, amic_n; 4987 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 4988 u16 tx_gain_ctl_reg; 4989 char *dec; 4990 u8 hpf_coff_freq; 4991 4992 widget_name = kstrndup(w->name, 15, GFP_KERNEL); 4993 if (!widget_name) 4994 return -ENOMEM; 4995 4996 wname = widget_name; 4997 dec_adc_mux_name = strsep(&widget_name, " "); 4998 if (!dec_adc_mux_name) { 4999 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 5000 __func__, w->name); 5001 ret = -EINVAL; 5002 goto out; 5003 } 5004 dec_adc_mux_name = widget_name; 5005 5006 dec = strpbrk(dec_adc_mux_name, "012345678"); 5007 if (!dec) { 5008 dev_err(comp->dev, "%s: decimator index not found\n", 5009 __func__); 5010 ret = -EINVAL; 5011 goto out; 5012 } 5013 5014 ret = kstrtouint(dec, 10, &decimator); 5015 if (ret < 0) { 5016 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 5017 __func__, wname); 5018 ret = -EINVAL; 5019 goto out; 5020 } 5021 5022 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator; 5023 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 5024 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 5025 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator; 5026 5027 switch (event) { 5028 case SND_SOC_DAPM_PRE_PMU: 5029 amic_n = wcd934x_codec_find_amic_input(comp, decimator); 5030 if (amic_n) 5031 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp, 5032 amic_n); 5033 5034 if (!pwr_level_reg) 5035 break; 5036 5037 switch ((snd_soc_component_read(comp, pwr_level_reg) & 5038 WCD934X_AMIC_PWR_LVL_MASK) >> 5039 WCD934X_AMIC_PWR_LVL_SHIFT) { 5040 case WCD934X_AMIC_PWR_LEVEL_LP: 5041 snd_soc_component_update_bits(comp, dec_cfg_reg, 5042 WCD934X_DEC_PWR_LVL_MASK, 5043 WCD934X_DEC_PWR_LVL_LP); 5044 break; 5045 case WCD934X_AMIC_PWR_LEVEL_HP: 5046 snd_soc_component_update_bits(comp, dec_cfg_reg, 5047 WCD934X_DEC_PWR_LVL_MASK, 5048 WCD934X_DEC_PWR_LVL_HP); 5049 break; 5050 case WCD934X_AMIC_PWR_LEVEL_DEFAULT: 5051 case WCD934X_AMIC_PWR_LEVEL_HYBRID: 5052 default: 5053 snd_soc_component_update_bits(comp, dec_cfg_reg, 5054 WCD934X_DEC_PWR_LVL_MASK, 5055 WCD934X_DEC_PWR_LVL_DF); 5056 break; 5057 } 5058 break; 5059 case SND_SOC_DAPM_POST_PMU: 5060 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5061 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5062 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5063 snd_soc_component_update_bits(comp, dec_cfg_reg, 5064 TX_HPF_CUT_OFF_FREQ_MASK, 5065 CF_MIN_3DB_150HZ << 5); 5066 snd_soc_component_update_bits(comp, hpf_gate_reg, 5067 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5068 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5069 /* 5070 * Minimum 1 clk cycle delay is required as per 5071 * HW spec. 5072 */ 5073 usleep_range(1000, 1010); 5074 snd_soc_component_update_bits(comp, hpf_gate_reg, 5075 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5076 0); 5077 } 5078 /* apply gain after decimator is enabled */ 5079 snd_soc_component_write(comp, tx_gain_ctl_reg, 5080 snd_soc_component_read(comp, 5081 tx_gain_ctl_reg)); 5082 break; 5083 case SND_SOC_DAPM_PRE_PMD: 5084 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5085 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5086 5087 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5088 snd_soc_component_update_bits(comp, dec_cfg_reg, 5089 TX_HPF_CUT_OFF_FREQ_MASK, 5090 hpf_coff_freq << 5); 5091 snd_soc_component_update_bits(comp, hpf_gate_reg, 5092 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5093 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5094 /* 5095 * Minimum 1 clk cycle delay is required as per 5096 * HW spec. 5097 */ 5098 usleep_range(1000, 1010); 5099 snd_soc_component_update_bits(comp, hpf_gate_reg, 5100 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5101 0); 5102 } 5103 break; 5104 case SND_SOC_DAPM_POST_PMD: 5105 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 5106 0x10, 0x00); 5107 snd_soc_component_update_bits(comp, dec_cfg_reg, 5108 WCD934X_DEC_PWR_LVL_MASK, 5109 WCD934X_DEC_PWR_LVL_DF); 5110 break; 5111 } 5112out: 5113 kfree(wname); 5114 return ret; 5115} 5116 5117static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp, 5118 u16 amic_reg, bool set) 5119{ 5120 u8 mask = 0x20; 5121 u8 val; 5122 5123 if (amic_reg == WCD934X_ANA_AMIC1 || 5124 amic_reg == WCD934X_ANA_AMIC3) 5125 mask = 0x40; 5126 5127 val = set ? mask : 0x00; 5128 5129 switch (amic_reg) { 5130 case WCD934X_ANA_AMIC1: 5131 case WCD934X_ANA_AMIC2: 5132 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2, 5133 mask, val); 5134 break; 5135 case WCD934X_ANA_AMIC3: 5136 case WCD934X_ANA_AMIC4: 5137 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4, 5138 mask, val); 5139 break; 5140 default: 5141 break; 5142 } 5143} 5144 5145static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w, 5146 struct snd_kcontrol *kcontrol, int event) 5147{ 5148 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 5149 5150 switch (event) { 5151 case SND_SOC_DAPM_PRE_PMU: 5152 wcd934x_codec_set_tx_hold(comp, w->reg, true); 5153 break; 5154 default: 5155 break; 5156 } 5157 5158 return 0; 5159} 5160 5161static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 5162 struct snd_kcontrol *kcontrol, 5163 int event) 5164{ 5165 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 5166 int micb_num = w->shift; 5167 5168 switch (event) { 5169 case SND_SOC_DAPM_PRE_PMU: 5170 wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true); 5171 break; 5172 case SND_SOC_DAPM_POST_PMU: 5173 /* 1 msec delay as per HW requirement */ 5174 usleep_range(1000, 1100); 5175 break; 5176 case SND_SOC_DAPM_POST_PMD: 5177 wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true); 5178 break; 5179 } 5180 5181 return 0; 5182} 5183 5184static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = { 5185 /* Analog Outputs */ 5186 SND_SOC_DAPM_OUTPUT("EAR"), 5187 SND_SOC_DAPM_OUTPUT("HPHL"), 5188 SND_SOC_DAPM_OUTPUT("HPHR"), 5189 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 5190 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 5191 SND_SOC_DAPM_OUTPUT("SPK1 OUT"), 5192 SND_SOC_DAPM_OUTPUT("SPK2 OUT"), 5193 SND_SOC_DAPM_OUTPUT("ANC EAR"), 5194 SND_SOC_DAPM_OUTPUT("ANC HPHL"), 5195 SND_SOC_DAPM_OUTPUT("ANC HPHR"), 5196 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"), 5197 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"), 5198 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"), 5199 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 5200 AIF1_PB, 0, wcd934x_codec_enable_slim, 5201 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5202 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 5203 AIF2_PB, 0, wcd934x_codec_enable_slim, 5204 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5205 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 5206 AIF3_PB, 0, wcd934x_codec_enable_slim, 5207 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5208 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 5209 AIF4_PB, 0, wcd934x_codec_enable_slim, 5210 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5211 5212 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0, 5213 &slim_rx_mux[WCD934X_RX0]), 5214 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0, 5215 &slim_rx_mux[WCD934X_RX1]), 5216 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0, 5217 &slim_rx_mux[WCD934X_RX2]), 5218 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0, 5219 &slim_rx_mux[WCD934X_RX3]), 5220 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0, 5221 &slim_rx_mux[WCD934X_RX4]), 5222 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0, 5223 &slim_rx_mux[WCD934X_RX5]), 5224 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0, 5225 &slim_rx_mux[WCD934X_RX6]), 5226 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0, 5227 &slim_rx_mux[WCD934X_RX7]), 5228 5229 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5230 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5231 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5232 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5233 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5234 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5235 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5236 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5237 5238 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0, 5239 &rx_int0_2_mux, wcd934x_codec_enable_mix_path, 5240 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5241 SND_SOC_DAPM_POST_PMD), 5242 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, 5243 &rx_int1_2_mux, wcd934x_codec_enable_mix_path, 5244 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5245 SND_SOC_DAPM_POST_PMD), 5246 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, 5247 &rx_int2_2_mux, wcd934x_codec_enable_mix_path, 5248 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5249 SND_SOC_DAPM_POST_PMD), 5250 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0, 5251 &rx_int3_2_mux, wcd934x_codec_enable_mix_path, 5252 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5253 SND_SOC_DAPM_POST_PMD), 5254 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0, 5255 &rx_int4_2_mux, wcd934x_codec_enable_mix_path, 5256 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5257 SND_SOC_DAPM_POST_PMD), 5258 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0, 5259 &rx_int7_2_mux, wcd934x_codec_enable_mix_path, 5260 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5261 SND_SOC_DAPM_POST_PMD), 5262 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0, 5263 &rx_int8_2_mux, wcd934x_codec_enable_mix_path, 5264 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5265 SND_SOC_DAPM_POST_PMD), 5266 5267 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5268 &rx_int0_1_mix_inp0_mux), 5269 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5270 &rx_int0_1_mix_inp1_mux), 5271 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5272 &rx_int0_1_mix_inp2_mux), 5273 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5274 &rx_int1_1_mix_inp0_mux), 5275 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5276 &rx_int1_1_mix_inp1_mux), 5277 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5278 &rx_int1_1_mix_inp2_mux), 5279 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5280 &rx_int2_1_mix_inp0_mux), 5281 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5282 &rx_int2_1_mix_inp1_mux), 5283 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5284 &rx_int2_1_mix_inp2_mux), 5285 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5286 &rx_int3_1_mix_inp0_mux), 5287 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5288 &rx_int3_1_mix_inp1_mux), 5289 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5290 &rx_int3_1_mix_inp2_mux), 5291 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5292 &rx_int4_1_mix_inp0_mux), 5293 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5294 &rx_int4_1_mix_inp1_mux), 5295 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5296 &rx_int4_1_mix_inp2_mux), 5297 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5298 &rx_int7_1_mix_inp0_mux), 5299 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5300 &rx_int7_1_mix_inp1_mux), 5301 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5302 &rx_int7_1_mix_inp2_mux), 5303 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5304 &rx_int8_1_mix_inp0_mux), 5305 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5306 &rx_int8_1_mix_inp1_mux), 5307 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5308 &rx_int8_1_mix_inp2_mux), 5309 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5310 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5311 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5312 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, 5313 rx_int1_asrc_switch, 5314 ARRAY_SIZE(rx_int1_asrc_switch)), 5315 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5316 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, 5317 rx_int2_asrc_switch, 5318 ARRAY_SIZE(rx_int2_asrc_switch)), 5319 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5320 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, 5321 rx_int3_asrc_switch, 5322 ARRAY_SIZE(rx_int3_asrc_switch)), 5323 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5324 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, 5325 rx_int4_asrc_switch, 5326 ARRAY_SIZE(rx_int4_asrc_switch)), 5327 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5328 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5329 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5330 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5331 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5332 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5333 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5334 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5335 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5336 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5337 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5338 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5339 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5340 5341 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5342 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0, 5343 NULL, 0, NULL, 0), 5344 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0, 5345 NULL, 0, NULL, 0), 5346 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4, 5347 0, &rx_int0_mix2_inp_mux, NULL, 5348 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5349 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4, 5350 0, &rx_int1_mix2_inp_mux, NULL, 5351 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5352 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4, 5353 0, &rx_int2_mix2_inp_mux, NULL, 5354 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5355 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4, 5356 0, &rx_int3_mix2_inp_mux, NULL, 5357 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5358 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4, 5359 0, &rx_int4_mix2_inp_mux, NULL, 5360 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5361 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4, 5362 0, &rx_int7_mix2_inp_mux, NULL, 5363 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5364 5365 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux), 5366 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux), 5367 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux), 5368 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux), 5369 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux), 5370 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), 5371 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux), 5372 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux), 5373 5374 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 5375 0, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5376 SND_SOC_DAPM_POST_PMU), 5377 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 5378 1, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5379 SND_SOC_DAPM_POST_PMU), 5380 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL, 5381 4, 0, NULL, 0), 5382 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL, 5383 4, 0, NULL, 0), 5384 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 5385 &rx_int0_dem_inp_mux), 5386 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 5387 &rx_int1_dem_inp_mux), 5388 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 5389 &rx_int2_dem_inp_mux), 5390 5391 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0, 5392 &rx_int0_1_interp_mux, 5393 wcd934x_codec_enable_main_path, 5394 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5395 SND_SOC_DAPM_POST_PMD), 5396 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, 5397 &rx_int1_1_interp_mux, 5398 wcd934x_codec_enable_main_path, 5399 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5400 SND_SOC_DAPM_POST_PMD), 5401 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, 5402 &rx_int2_1_interp_mux, 5403 wcd934x_codec_enable_main_path, 5404 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5405 SND_SOC_DAPM_POST_PMD), 5406 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0, 5407 &rx_int3_1_interp_mux, 5408 wcd934x_codec_enable_main_path, 5409 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5410 SND_SOC_DAPM_POST_PMD), 5411 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0, 5412 &rx_int4_1_interp_mux, 5413 wcd934x_codec_enable_main_path, 5414 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5415 SND_SOC_DAPM_POST_PMD), 5416 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0, 5417 &rx_int7_1_interp_mux, 5418 wcd934x_codec_enable_main_path, 5419 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5420 SND_SOC_DAPM_POST_PMD), 5421 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0, 5422 &rx_int8_1_interp_mux, 5423 wcd934x_codec_enable_main_path, 5424 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5425 SND_SOC_DAPM_POST_PMD), 5426 5427 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0, 5428 &rx_int0_2_interp_mux), 5429 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0, 5430 &rx_int1_2_interp_mux), 5431 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0, 5432 &rx_int2_2_interp_mux), 5433 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0, 5434 &rx_int3_2_interp_mux), 5435 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0, 5436 &rx_int4_2_interp_mux), 5437 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0, 5438 &rx_int7_2_interp_mux), 5439 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0, 5440 &rx_int8_2_interp_mux), 5441 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 5442 0, 0, wcd934x_codec_ear_dac_event, 5443 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5444 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5445 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH, 5446 5, 0, wcd934x_codec_hphl_dac_event, 5447 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5448 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5449 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH, 5450 4, 0, wcd934x_codec_hphr_dac_event, 5451 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5452 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5453 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 5454 0, 0, wcd934x_codec_lineout_dac_event, 5455 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5456 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 5457 0, 0, wcd934x_codec_lineout_dac_event, 5458 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5459 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0), 5460 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0, 5461 wcd934x_codec_enable_hphl_pa, 5462 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5463 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5464 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0, 5465 wcd934x_codec_enable_hphr_pa, 5466 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5467 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5468 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0, 5469 NULL, 0), 5470 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0, 5471 NULL, 0), 5472 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL, 5473 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5474 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1, 5475 0, 0, NULL, 0), 5476 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL, 5477 0, 0, NULL, 0), 5478 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1, 5479 0, 0, NULL, 0), 5480 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL, 5481 0, 0, NULL, 0), 5482 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0, 5483 wcd934x_codec_enable_interp_clk, 5484 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5485 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0, 5486 wcd934x_codec_enable_interp_clk, 5487 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5488 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0, 5489 wcd934x_codec_enable_interp_clk, 5490 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5491 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0, 5492 wcd934x_codec_enable_interp_clk, 5493 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5494 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0, 5495 wcd934x_codec_enable_interp_clk, 5496 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5497 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0, 5498 wcd934x_codec_enable_interp_clk, 5499 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5500 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0, 5501 wcd934x_codec_enable_interp_clk, 5502 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5503 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL, 5504 0, 0, NULL, 0), 5505 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL, 5506 0, 0, NULL, 0), 5507 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL, 5508 0, 0, NULL, 0), 5509 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL, 5510 0, 0, NULL, 0), 5511 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL, 5512 0, 0, NULL, 0), 5513 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL, 5514 0, 0, NULL, 0), 5515 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL, 5516 0, 0, NULL, 0), 5517 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 5518 wcd934x_codec_enable_mclk, 5519 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5520 5521 /* TX */ 5522 SND_SOC_DAPM_INPUT("AMIC1"), 5523 SND_SOC_DAPM_INPUT("AMIC2"), 5524 SND_SOC_DAPM_INPUT("AMIC3"), 5525 SND_SOC_DAPM_INPUT("AMIC4"), 5526 SND_SOC_DAPM_INPUT("AMIC5"), 5527 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 5528 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 5529 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 5530 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 5531 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 5532 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 5533 5534 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 5535 AIF1_CAP, 0, wcd934x_codec_enable_slim, 5536 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5537 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 5538 AIF2_CAP, 0, wcd934x_codec_enable_slim, 5539 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5540 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 5541 AIF3_CAP, 0, wcd934x_codec_enable_slim, 5542 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5543 5544 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5545 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5546 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5547 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5548 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5549 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5550 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5551 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5552 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0), 5553 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0), 5554 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0), 5555 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0), 5556 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0), 5557 5558 /* Digital Mic Inputs */ 5559 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 5560 wcd934x_codec_enable_dmic, 5561 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5562 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 5563 wcd934x_codec_enable_dmic, 5564 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5565 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 5566 wcd934x_codec_enable_dmic, 5567 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5568 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 5569 wcd934x_codec_enable_dmic, 5570 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5571 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 5572 wcd934x_codec_enable_dmic, 5573 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5574 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 5575 wcd934x_codec_enable_dmic, 5576 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5577 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0), 5578 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1), 5579 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2), 5580 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3), 5581 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4), 5582 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5), 5583 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6), 5584 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7), 5585 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8), 5586 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0), 5587 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1), 5588 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2), 5589 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3), 5590 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4), 5591 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5), 5592 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6), 5593 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7), 5594 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8), 5595 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0, 5596 &tx_adc_mux0_mux, wcd934x_codec_enable_dec, 5597 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5598 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5599 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0, 5600 &tx_adc_mux1_mux, wcd934x_codec_enable_dec, 5601 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5602 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5603 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0, 5604 &tx_adc_mux2_mux, wcd934x_codec_enable_dec, 5605 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5606 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5607 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0, 5608 &tx_adc_mux3_mux, wcd934x_codec_enable_dec, 5609 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5610 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5611 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0, 5612 &tx_adc_mux4_mux, wcd934x_codec_enable_dec, 5613 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5614 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5615 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0, 5616 &tx_adc_mux5_mux, wcd934x_codec_enable_dec, 5617 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5618 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5619 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0, 5620 &tx_adc_mux6_mux, wcd934x_codec_enable_dec, 5621 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5622 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5623 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0, 5624 &tx_adc_mux7_mux, wcd934x_codec_enable_dec, 5625 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5626 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5627 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0, 5628 &tx_adc_mux8_mux, wcd934x_codec_enable_dec, 5629 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5630 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5631 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0, 5632 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5633 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0, 5634 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5635 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0, 5636 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5637 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0, 5638 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5639 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 5640 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5641 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5642 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 5643 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5644 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5645 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 5646 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5647 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5648 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 5649 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5650 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5651 5652 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5), 5653 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0, 5654 &cdc_if_tx0_mux), 5655 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0, 5656 &cdc_if_tx1_mux), 5657 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0, 5658 &cdc_if_tx2_mux), 5659 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0, 5660 &cdc_if_tx3_mux), 5661 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0, 5662 &cdc_if_tx4_mux), 5663 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0, 5664 &cdc_if_tx5_mux), 5665 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0, 5666 &cdc_if_tx6_mux), 5667 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0, 5668 &cdc_if_tx7_mux), 5669 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0, 5670 &cdc_if_tx8_mux), 5671 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0, 5672 &cdc_if_tx9_mux), 5673 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0, 5674 &cdc_if_tx10_mux), 5675 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5676 &cdc_if_tx11_mux), 5677 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5678 &cdc_if_tx11_inp1_mux), 5679 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5680 &cdc_if_tx13_mux), 5681 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5682 &cdc_if_tx13_inp1_mux), 5683 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 5684 aif1_slim_cap_mixer, 5685 ARRAY_SIZE(aif1_slim_cap_mixer)), 5686 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 5687 aif2_slim_cap_mixer, 5688 ARRAY_SIZE(aif2_slim_cap_mixer)), 5689 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 5690 aif3_slim_cap_mixer, 5691 ARRAY_SIZE(aif3_slim_cap_mixer)), 5692}; 5693 5694static const struct snd_soc_dapm_route wcd934x_audio_map[] = { 5695 /* RX0-RX7 */ 5696 WCD934X_SLIM_RX_AIF_PATH(0), 5697 WCD934X_SLIM_RX_AIF_PATH(1), 5698 WCD934X_SLIM_RX_AIF_PATH(2), 5699 WCD934X_SLIM_RX_AIF_PATH(3), 5700 WCD934X_SLIM_RX_AIF_PATH(4), 5701 WCD934X_SLIM_RX_AIF_PATH(5), 5702 WCD934X_SLIM_RX_AIF_PATH(6), 5703 WCD934X_SLIM_RX_AIF_PATH(7), 5704 5705 /* RX0 Ear out */ 5706 WCD934X_INTERPOLATOR_PATH(0), 5707 WCD934X_INTERPOLATOR_MIX2(0), 5708 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, 5709 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 5710 {"RX INT0 DAC", NULL, "RX_BIAS"}, 5711 {"EAR PA", NULL, "RX INT0 DAC"}, 5712 {"EAR", NULL, "EAR PA"}, 5713 5714 /* RX1 Headphone left */ 5715 WCD934X_INTERPOLATOR_PATH(1), 5716 WCD934X_INTERPOLATOR_MIX2(1), 5717 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"}, 5718 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"}, 5719 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 5720 {"RX INT1 DAC", NULL, "RX_BIAS"}, 5721 {"HPHL PA", NULL, "RX INT1 DAC"}, 5722 {"HPHL", NULL, "HPHL PA"}, 5723 5724 /* RX2 Headphone right */ 5725 WCD934X_INTERPOLATOR_PATH(2), 5726 WCD934X_INTERPOLATOR_MIX2(2), 5727 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"}, 5728 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"}, 5729 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 5730 {"RX INT2 DAC", NULL, "RX_BIAS"}, 5731 {"HPHR PA", NULL, "RX INT2 DAC"}, 5732 {"HPHR", NULL, "HPHR PA"}, 5733 5734 /* RX3 HIFi LineOut1 */ 5735 WCD934X_INTERPOLATOR_PATH(3), 5736 WCD934X_INTERPOLATOR_MIX2(3), 5737 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"}, 5738 {"RX INT3 DAC", NULL, "RX INT3 MIX3"}, 5739 {"RX INT3 DAC", NULL, "RX_BIAS"}, 5740 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 5741 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 5742 5743 /* RX4 HIFi LineOut2 */ 5744 WCD934X_INTERPOLATOR_PATH(4), 5745 WCD934X_INTERPOLATOR_MIX2(4), 5746 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"}, 5747 {"RX INT4 DAC", NULL, "RX INT4 MIX3"}, 5748 {"RX INT4 DAC", NULL, "RX_BIAS"}, 5749 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 5750 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 5751 5752 /* RX7 Speaker Left Out PA */ 5753 WCD934X_INTERPOLATOR_PATH(7), 5754 WCD934X_INTERPOLATOR_MIX2(7), 5755 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"}, 5756 {"RX INT7 CHAIN", NULL, "RX_BIAS"}, 5757 {"RX INT7 CHAIN", NULL, "SBOOST0"}, 5758 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"}, 5759 {"SPK1 OUT", NULL, "RX INT7 CHAIN"}, 5760 5761 /* RX8 Speaker Right Out PA */ 5762 WCD934X_INTERPOLATOR_PATH(8), 5763 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"}, 5764 {"RX INT8 CHAIN", NULL, "RX_BIAS"}, 5765 {"RX INT8 CHAIN", NULL, "SBOOST1"}, 5766 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"}, 5767 {"SPK2 OUT", NULL, "RX INT8 CHAIN"}, 5768 5769 /* Tx */ 5770 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 5771 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 5772 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 5773 5774 WCD934X_SLIM_TX_AIF_PATH(0), 5775 WCD934X_SLIM_TX_AIF_PATH(1), 5776 WCD934X_SLIM_TX_AIF_PATH(2), 5777 WCD934X_SLIM_TX_AIF_PATH(3), 5778 WCD934X_SLIM_TX_AIF_PATH(4), 5779 WCD934X_SLIM_TX_AIF_PATH(5), 5780 WCD934X_SLIM_TX_AIF_PATH(6), 5781 WCD934X_SLIM_TX_AIF_PATH(7), 5782 WCD934X_SLIM_TX_AIF_PATH(8), 5783 5784 WCD934X_ADC_MUX(0), 5785 WCD934X_ADC_MUX(1), 5786 WCD934X_ADC_MUX(2), 5787 WCD934X_ADC_MUX(3), 5788 WCD934X_ADC_MUX(4), 5789 WCD934X_ADC_MUX(5), 5790 WCD934X_ADC_MUX(6), 5791 WCD934X_ADC_MUX(7), 5792 WCD934X_ADC_MUX(8), 5793 5794 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"}, 5795 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"}, 5796 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"}, 5797 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"}, 5798 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"}, 5799 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"}, 5800 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"}, 5801 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"}, 5802 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"}, 5803 5804 {"AMIC4_5 SEL", "AMIC4", "AMIC4"}, 5805 {"AMIC4_5 SEL", "AMIC5", "AMIC5"}, 5806 5807 { "DMIC0", NULL, "DMIC0 Pin" }, 5808 { "DMIC1", NULL, "DMIC1 Pin" }, 5809 { "DMIC2", NULL, "DMIC2 Pin" }, 5810 { "DMIC3", NULL, "DMIC3 Pin" }, 5811 { "DMIC4", NULL, "DMIC4 Pin" }, 5812 { "DMIC5", NULL, "DMIC5 Pin" }, 5813 5814 {"ADC1", NULL, "AMIC1"}, 5815 {"ADC2", NULL, "AMIC2"}, 5816 {"ADC3", NULL, "AMIC3"}, 5817 {"ADC4", NULL, "AMIC4_5 SEL"}, 5818 5819 WCD934X_IIR_INP_MUX(0), 5820 WCD934X_IIR_INP_MUX(1), 5821 5822 {"SRC0", NULL, "IIR0"}, 5823 {"SRC1", NULL, "IIR1"}, 5824}; 5825 5826static int wcd934x_codec_set_jack(struct snd_soc_component *comp, 5827 struct snd_soc_jack *jack, void *data) 5828{ 5829 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 5830 int ret = 0; 5831 5832 if (!wcd->mbhc) 5833 return -ENOTSUPP; 5834 5835 if (jack && !wcd->mbhc_started) { 5836 ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack); 5837 wcd->mbhc_started = true; 5838 } else if (wcd->mbhc_started) { 5839 wcd_mbhc_stop(wcd->mbhc); 5840 wcd->mbhc_started = false; 5841 } 5842 5843 return ret; 5844} 5845 5846static const struct snd_soc_component_driver wcd934x_component_drv = { 5847 .probe = wcd934x_comp_probe, 5848 .remove = wcd934x_comp_remove, 5849 .set_sysclk = wcd934x_comp_set_sysclk, 5850 .controls = wcd934x_snd_controls, 5851 .num_controls = ARRAY_SIZE(wcd934x_snd_controls), 5852 .dapm_widgets = wcd934x_dapm_widgets, 5853 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets), 5854 .dapm_routes = wcd934x_audio_map, 5855 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map), 5856 .set_jack = wcd934x_codec_set_jack, 5857 .endianness = 1, 5858}; 5859 5860static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd) 5861{ 5862 struct device *dev = &wcd->sdev->dev; 5863 struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg; 5864 struct device_node *ifc_dev_np; 5865 5866 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5867 if (!ifc_dev_np) { 5868 dev_err(dev, "No Interface device found\n"); 5869 return -EINVAL; 5870 } 5871 5872 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np); 5873 of_node_put(ifc_dev_np); 5874 if (!wcd->sidev) { 5875 dev_err(dev, "Unable to get SLIM Interface device\n"); 5876 return -EINVAL; 5877 } 5878 5879 slim_get_logical_addr(wcd->sidev); 5880 wcd->if_regmap = regmap_init_slimbus(wcd->sidev, 5881 &wcd934x_ifc_regmap_config); 5882 if (IS_ERR(wcd->if_regmap)) 5883 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap), 5884 "Failed to allocate ifc register map\n"); 5885 5886 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate", 5887 &wcd->dmic_sample_rate); 5888 5889 cfg->mbhc_micbias = MIC_BIAS_2; 5890 cfg->anc_micbias = MIC_BIAS_2; 5891 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 5892 cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS; 5893 cfg->micb_mv = wcd->micb2_mv; 5894 cfg->linein_th = 5000; 5895 cfg->hs_thr = 1700; 5896 cfg->hph_thr = 50; 5897 5898 wcd_dt_parse_mbhc_data(dev, cfg); 5899 5900 5901 return 0; 5902} 5903 5904static int wcd934x_codec_probe(struct platform_device *pdev) 5905{ 5906 struct device *dev = &pdev->dev; 5907 struct wcd934x_ddata *data = dev_get_drvdata(dev->parent); 5908 struct wcd934x_codec *wcd; 5909 int ret, irq; 5910 5911 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5912 if (!wcd) 5913 return -ENOMEM; 5914 5915 wcd->dev = dev; 5916 wcd->regmap = data->regmap; 5917 wcd->extclk = data->extclk; 5918 wcd->sdev = to_slim_device(data->dev); 5919 mutex_init(&wcd->sysclk_mutex); 5920 mutex_init(&wcd->micb_lock); 5921 5922 ret = wcd934x_codec_parse_data(wcd); 5923 if (ret) { 5924 dev_err(wcd->dev, "Failed to get SLIM IRQ\n"); 5925 return ret; 5926 } 5927 5928 /* set default rate 9P6MHz */ 5929 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 5930 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 5931 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 5932 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs)); 5933 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs)); 5934 5935 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS); 5936 if (irq < 0) 5937 return dev_err_probe(wcd->dev, irq, "Failed to get SLIM IRQ\n"); 5938 5939 ret = devm_request_threaded_irq(dev, irq, NULL, 5940 wcd934x_slim_irq_handler, 5941 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5942 "slim", wcd); 5943 if (ret) 5944 return dev_err_probe(dev, ret, "Failed to request slimbus irq\n"); 5945 5946 wcd934x_register_mclk_output(wcd); 5947 platform_set_drvdata(pdev, wcd); 5948 5949 return devm_snd_soc_register_component(dev, &wcd934x_component_drv, 5950 wcd934x_slim_dais, 5951 ARRAY_SIZE(wcd934x_slim_dais)); 5952} 5953 5954static const struct platform_device_id wcd934x_driver_id[] = { 5955 { 5956 .name = "wcd934x-codec", 5957 }, 5958 {}, 5959}; 5960MODULE_DEVICE_TABLE(platform, wcd934x_driver_id); 5961 5962static struct platform_driver wcd934x_codec_driver = { 5963 .probe = &wcd934x_codec_probe, 5964 .id_table = wcd934x_driver_id, 5965 .driver = { 5966 .name = "wcd934x-codec", 5967 } 5968}; 5969 5970MODULE_ALIAS("platform:wcd934x-codec"); 5971module_platform_driver(wcd934x_codec_driver); 5972MODULE_DESCRIPTION("WCD934x codec driver"); 5973MODULE_LICENSE("GPL v2"); 5974