1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2020 Nuvoton Technology corporation. 3 4#include <linux/bits.h> 5#include <linux/device.h> 6#include <linux/gpio/driver.h> 7#include <linux/interrupt.h> 8#include <linux/irq.h> 9#include <linux/mfd/syscon.h> 10#include <linux/module.h> 11#include <linux/debugfs.h> 12#include <linux/seq_file.h> 13#include <linux/mod_devicetable.h> 14#include <linux/pinctrl/machine.h> 15#include <linux/pinctrl/pinconf.h> 16#include <linux/pinctrl/pinconf-generic.h> 17#include <linux/pinctrl/pinctrl.h> 18#include <linux/pinctrl/pinmux.h> 19#include <linux/pinctrl/consumer.h> 20#include <linux/platform_device.h> 21#include <linux/property.h> 22#include <linux/regmap.h> 23 24/* GCR registers */ 25#define NPCM8XX_GCR_SRCNT 0x068 26#define NPCM8XX_GCR_FLOCKR1 0x074 27#define NPCM8XX_GCR_DSCNT 0x078 28#define NPCM8XX_GCR_I2CSEGSEL 0x0e0 29#define NPCM8XX_GCR_MFSEL1 0x260 30#define NPCM8XX_GCR_MFSEL2 0x264 31#define NPCM8XX_GCR_MFSEL3 0x268 32#define NPCM8XX_GCR_MFSEL4 0x26c 33#define NPCM8XX_GCR_MFSEL5 0x270 34#define NPCM8XX_GCR_MFSEL6 0x274 35#define NPCM8XX_GCR_MFSEL7 0x278 36 37#define SRCNT_ESPI BIT(3) 38 39/* GPIO registers */ 40#define NPCM8XX_GP_N_TLOCK1 0x00 41#define NPCM8XX_GP_N_DIN 0x04 42#define NPCM8XX_GP_N_POL 0x08 43#define NPCM8XX_GP_N_DOUT 0x0c 44#define NPCM8XX_GP_N_OE 0x10 45#define NPCM8XX_GP_N_OTYP 0x14 46#define NPCM8XX_GP_N_MP 0x18 47#define NPCM8XX_GP_N_PU 0x1c 48#define NPCM8XX_GP_N_PD 0x20 49#define NPCM8XX_GP_N_DBNC 0x24 50#define NPCM8XX_GP_N_EVTYP 0x28 51#define NPCM8XX_GP_N_EVBE 0x2c 52#define NPCM8XX_GP_N_OBL0 0x30 53#define NPCM8XX_GP_N_OBL1 0x34 54#define NPCM8XX_GP_N_OBL2 0x38 55#define NPCM8XX_GP_N_OBL3 0x3c 56#define NPCM8XX_GP_N_EVEN 0x40 57#define NPCM8XX_GP_N_EVENS 0x44 58#define NPCM8XX_GP_N_EVENC 0x48 59#define NPCM8XX_GP_N_EVST 0x4c 60#define NPCM8XX_GP_N_SPLCK 0x50 61#define NPCM8XX_GP_N_MPLCK 0x54 62#define NPCM8XX_GP_N_IEM 0x58 63#define NPCM8XX_GP_N_OSRC 0x5c 64#define NPCM8XX_GP_N_ODSC 0x60 65#define NPCM8XX_GP_N_DOS 0x68 66#define NPCM8XX_GP_N_DOC 0x6c 67#define NPCM8XX_GP_N_OES 0x70 68#define NPCM8XX_GP_N_OEC 0x74 69#define NPCM8XX_GP_N_DBNCS0 0x80 70#define NPCM8XX_GP_N_DBNCS1 0x84 71#define NPCM8XX_GP_N_DBNCP0 0x88 72#define NPCM8XX_GP_N_DBNCP1 0x8c 73#define NPCM8XX_GP_N_DBNCP2 0x90 74#define NPCM8XX_GP_N_DBNCP3 0x94 75#define NPCM8XX_GP_N_TLOCK2 0xac 76 77#define NPCM8XX_GPIO_PER_BANK 32 78#define NPCM8XX_GPIO_BANK_NUM 8 79#define NPCM8XX_GCR_NONE 0 80 81#define NPCM8XX_DEBOUNCE_MAX 4 82#define NPCM8XX_DEBOUNCE_NSEC 40 83#define NPCM8XX_DEBOUNCE_VAL_MASK GENMASK(23, 4) 84#define NPCM8XX_DEBOUNCE_MAX_VAL 0xFFFFF7 85 86/* Structure for register banks */ 87struct debounce_time { 88 bool set_val[NPCM8XX_DEBOUNCE_MAX]; 89 u32 nanosec_val[NPCM8XX_DEBOUNCE_MAX]; 90}; 91 92struct npcm8xx_gpio { 93 struct gpio_chip gc; 94 void __iomem *base; 95 struct debounce_time debounce; 96 int irqbase; 97 int irq; 98 struct irq_chip irq_chip; 99 u32 pinctrl_id; 100 int (*direction_input)(struct gpio_chip *chip, unsigned int offset); 101 int (*direction_output)(struct gpio_chip *chip, unsigned int offset, 102 int value); 103 int (*request)(struct gpio_chip *chip, unsigned int offset); 104 void (*free)(struct gpio_chip *chip, unsigned int offset); 105}; 106 107struct npcm8xx_pinctrl { 108 struct pinctrl_dev *pctldev; 109 struct device *dev; 110 struct npcm8xx_gpio gpio_bank[NPCM8XX_GPIO_BANK_NUM]; 111 struct irq_domain *domain; 112 struct regmap *gcr_regmap; 113 void __iomem *regs; 114 u32 bank_num; 115}; 116 117/* GPIO handling in the pinctrl driver */ 118static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg, 119 unsigned int pinmask) 120{ 121 unsigned long flags; 122 123 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 124 iowrite32(ioread32(reg) | pinmask, reg); 125 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 126} 127 128static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg, 129 unsigned int pinmask) 130{ 131 unsigned long flags; 132 133 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 134 iowrite32(ioread32(reg) & ~pinmask, reg); 135 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 136} 137 138static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 139{ 140 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); 141 142 seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n", 143 ioread32(bank->base + NPCM8XX_GP_N_DIN), 144 ioread32(bank->base + NPCM8XX_GP_N_DOUT), 145 ioread32(bank->base + NPCM8XX_GP_N_IEM), 146 ioread32(bank->base + NPCM8XX_GP_N_OE)); 147 seq_printf(s, "PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n", 148 ioread32(bank->base + NPCM8XX_GP_N_PU), 149 ioread32(bank->base + NPCM8XX_GP_N_PD), 150 ioread32(bank->base + NPCM8XX_GP_N_DBNC), 151 ioread32(bank->base + NPCM8XX_GP_N_POL)); 152 seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n", 153 ioread32(bank->base + NPCM8XX_GP_N_EVTYP), 154 ioread32(bank->base + NPCM8XX_GP_N_EVBE), 155 ioread32(bank->base + NPCM8XX_GP_N_EVEN), 156 ioread32(bank->base + NPCM8XX_GP_N_EVST)); 157 seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n", 158 ioread32(bank->base + NPCM8XX_GP_N_OTYP), 159 ioread32(bank->base + NPCM8XX_GP_N_OSRC), 160 ioread32(bank->base + NPCM8XX_GP_N_ODSC)); 161 seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n", 162 ioread32(bank->base + NPCM8XX_GP_N_OBL0), 163 ioread32(bank->base + NPCM8XX_GP_N_OBL1), 164 ioread32(bank->base + NPCM8XX_GP_N_OBL2), 165 ioread32(bank->base + NPCM8XX_GP_N_OBL3)); 166 seq_printf(s, "SLCK:%.8x MLCK:%.8x\n", 167 ioread32(bank->base + NPCM8XX_GP_N_SPLCK), 168 ioread32(bank->base + NPCM8XX_GP_N_MPLCK)); 169} 170 171static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset) 172{ 173 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); 174 int ret; 175 176 ret = pinctrl_gpio_direction_input(chip, offset); 177 if (ret) 178 return ret; 179 180 return bank->direction_input(chip, offset); 181} 182 183static int npcmgpio_direction_output(struct gpio_chip *chip, 184 unsigned int offset, int value) 185{ 186 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); 187 int ret; 188 189 ret = pinctrl_gpio_direction_output(chip, offset); 190 if (ret) 191 return ret; 192 193 return bank->direction_output(chip, offset, value); 194} 195 196static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset) 197{ 198 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); 199 int ret; 200 201 ret = pinctrl_gpio_request(chip, offset); 202 if (ret) 203 return ret; 204 205 return bank->request(chip, offset); 206} 207 208static void npcmgpio_irq_handler(struct irq_desc *desc) 209{ 210 unsigned long sts, en, bit; 211 struct npcm8xx_gpio *bank; 212 struct irq_chip *chip; 213 struct gpio_chip *gc; 214 215 gc = irq_desc_get_handler_data(desc); 216 bank = gpiochip_get_data(gc); 217 chip = irq_desc_get_chip(desc); 218 219 chained_irq_enter(chip, desc); 220 sts = ioread32(bank->base + NPCM8XX_GP_N_EVST); 221 en = ioread32(bank->base + NPCM8XX_GP_N_EVEN); 222 sts &= en; 223 for_each_set_bit(bit, &sts, NPCM8XX_GPIO_PER_BANK) 224 generic_handle_domain_irq(gc->irq.domain, bit); 225 chained_irq_exit(chip, desc); 226} 227 228static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type) 229{ 230 struct npcm8xx_gpio *bank = 231 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 232 unsigned int gpio = BIT(irqd_to_hwirq(d)); 233 234 switch (type) { 235 case IRQ_TYPE_EDGE_RISING: 236 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); 237 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 238 break; 239 case IRQ_TYPE_EDGE_FALLING: 240 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); 241 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 242 break; 243 case IRQ_TYPE_EDGE_BOTH: 244 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); 245 break; 246 case IRQ_TYPE_LEVEL_LOW: 247 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 248 break; 249 case IRQ_TYPE_LEVEL_HIGH: 250 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 251 break; 252 default: 253 return -EINVAL; 254 } 255 256 if (type & IRQ_TYPE_LEVEL_MASK) { 257 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); 258 irq_set_handler_locked(d, handle_level_irq); 259 } else if (type & IRQ_TYPE_EDGE_BOTH) { 260 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); 261 irq_set_handler_locked(d, handle_edge_irq); 262 } 263 264 return 0; 265} 266 267static void npcmgpio_irq_ack(struct irq_data *d) 268{ 269 struct npcm8xx_gpio *bank = 270 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 271 unsigned int gpio = irqd_to_hwirq(d); 272 273 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVST); 274} 275 276static void npcmgpio_irq_mask(struct irq_data *d) 277{ 278 struct npcm8xx_gpio *bank = 279 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 280 unsigned int gpio = irqd_to_hwirq(d); 281 282 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENC); 283} 284 285static void npcmgpio_irq_unmask(struct irq_data *d) 286{ 287 struct npcm8xx_gpio *bank = 288 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 289 unsigned int gpio = irqd_to_hwirq(d); 290 291 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENS); 292} 293 294static unsigned int npcmgpio_irq_startup(struct irq_data *d) 295{ 296 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 297 unsigned int gpio = irqd_to_hwirq(d); 298 299 /* active-high, input, clear interrupt, enable interrupt */ 300 npcmgpio_direction_input(gc, gpio); 301 npcmgpio_irq_ack(d); 302 npcmgpio_irq_unmask(d); 303 304 return 0; 305} 306 307static struct irq_chip npcmgpio_irqchip = { 308 .name = "NPCM8XX-GPIO-IRQ", 309 .irq_ack = npcmgpio_irq_ack, 310 .irq_unmask = npcmgpio_irq_unmask, 311 .irq_mask = npcmgpio_irq_mask, 312 .irq_set_type = npcmgpio_set_irq_type, 313 .irq_startup = npcmgpio_irq_startup, 314 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 315 GPIOCHIP_IRQ_RESOURCE_HELPERS, 316}; 317 318static const int gpi36_pins[] = { 58 }; 319static const int gpi35_pins[] = { 58 }; 320 321static const int tp_jtag3_pins[] = { 44, 62, 45, 46 }; 322static const int tp_uart_pins[] = { 50, 51 }; 323 324static const int tp_smb2_pins[] = { 24, 25 }; 325static const int tp_smb1_pins[] = { 142, 143 }; 326 327static const int tp_gpio7_pins[] = { 96 }; 328static const int tp_gpio6_pins[] = { 97 }; 329static const int tp_gpio5_pins[] = { 98 }; 330static const int tp_gpio4_pins[] = { 99 }; 331static const int tp_gpio3_pins[] = { 100 }; 332static const int tp_gpio2_pins[] = { 16 }; 333static const int tp_gpio1_pins[] = { 9 }; 334static const int tp_gpio0_pins[] = { 8 }; 335 336static const int tp_gpio2b_pins[] = { 101 }; 337static const int tp_gpio1b_pins[] = { 92 }; 338static const int tp_gpio0b_pins[] = { 91 }; 339 340static const int vgadig_pins[] = { 102, 103, 104, 105 }; 341 342static const int nbu1crts_pins[] = { 44, 62 }; 343 344static const int fm2_pins[] = { 224, 225, 226, 227, 228, 229, 230 }; 345static const int fm1_pins[] = { 175, 176, 177, 203, 191, 192, 233 }; 346static const int fm0_pins[] = { 194, 195, 196, 202, 199, 198, 197 }; 347 348static const int gpio1836_pins[] = { 183, 184, 185, 186 }; 349static const int gpio1889_pins[] = { 188, 189 }; 350static const int gpo187_pins[] = { 187 }; 351 352static const int cp1urxd_pins[] = { 41 }; 353static const int r3rxer_pins[] = { 212 }; 354 355static const int cp1gpio2c_pins[] = { 101 }; 356static const int cp1gpio3c_pins[] = { 100 }; 357 358static const int cp1gpio0b_pins[] = { 127 }; 359static const int cp1gpio1b_pins[] = { 126 }; 360static const int cp1gpio2b_pins[] = { 125 }; 361static const int cp1gpio3b_pins[] = { 124 }; 362static const int cp1gpio4b_pins[] = { 99 }; 363static const int cp1gpio5b_pins[] = { 98 }; 364static const int cp1gpio6b_pins[] = { 97 }; 365static const int cp1gpio7b_pins[] = { 96 }; 366 367static const int cp1gpio0_pins[] = { }; 368static const int cp1gpio1_pins[] = { }; 369static const int cp1gpio2_pins[] = { }; 370static const int cp1gpio3_pins[] = { }; 371static const int cp1gpio4_pins[] = { }; 372static const int cp1gpio5_pins[] = { 17 }; 373static const int cp1gpio6_pins[] = { 91 }; 374static const int cp1gpio7_pins[] = { 92 }; 375 376static const int cp1utxd_pins[] = { 42 }; 377 378static const int spi1cs3_pins[] = { 192 }; 379static const int spi1cs2_pins[] = { 191 }; 380static const int spi1cs1_pins[] = { 233 }; 381static const int spi1cs0_pins[] = { 203 }; 382 383static const int spi1d23_pins[] = { 191, 192 }; 384 385static const int j2j3_pins[] = { 44, 62, 45, 46 }; 386 387static const int r3oen_pins[] = { 213 }; 388static const int r2oen_pins[] = { 90 }; 389static const int r1oen_pins[] = { 56 }; 390static const int bu4b_pins[] = { 98, 99 }; 391static const int bu4_pins[] = { 54, 55 }; 392static const int bu5b_pins[] = { 100, 101 }; 393static const int bu5_pins[] = { 52, 53 }; 394static const int bu6_pins[] = { 50, 51 }; 395static const int rmii3_pins[] = { 110, 111, 209, 211, 210, 214, 215 }; 396 397static const int jm1_pins[] = { 136, 137, 138, 139, 140 }; 398static const int jm2_pins[] = { 251 }; 399 400static const int tpgpio5b_pins[] = { 58 }; 401static const int tpgpio4b_pins[] = { 57 }; 402 403static const int clkrun_pins[] = { 162 }; 404 405static const int i3c5_pins[] = { 106, 107 }; 406static const int i3c4_pins[] = { 33, 34 }; 407static const int i3c3_pins[] = { 246, 247 }; 408static const int i3c2_pins[] = { 244, 245 }; 409static const int i3c1_pins[] = { 242, 243 }; 410static const int i3c0_pins[] = { 240, 241 }; 411 412static const int hsi1a_pins[] = { 43, 63 }; 413static const int hsi2a_pins[] = { 48, 49 }; 414static const int hsi1b_pins[] = { 44, 62 }; 415static const int hsi2b_pins[] = { 50, 51 }; 416static const int hsi1c_pins[] = { 45, 46, 47, 61 }; 417static const int hsi2c_pins[] = { 45, 46, 47, 61 }; 418 419static const int smb0_pins[] = { 115, 114 }; 420static const int smb0b_pins[] = { 195, 194 }; 421static const int smb0c_pins[] = { 202, 196 }; 422static const int smb0d_pins[] = { 198, 199 }; 423static const int smb0den_pins[] = { 197 }; 424static const int smb1_pins[] = { 117, 116 }; 425static const int smb1b_pins[] = { 126, 127 }; 426static const int smb1c_pins[] = { 124, 125 }; 427static const int smb1d_pins[] = { 4, 5 }; 428static const int smb2_pins[] = { 119, 118 }; 429static const int smb2b_pins[] = { 122, 123 }; 430static const int smb2c_pins[] = { 120, 121 }; 431static const int smb2d_pins[] = { 6, 7 }; 432static const int smb3_pins[] = { 30, 31 }; 433static const int smb3b_pins[] = { 39, 40 }; 434static const int smb3c_pins[] = { 37, 38 }; 435static const int smb3d_pins[] = { 59, 60 }; 436static const int smb4_pins[] = { 28, 29 }; 437static const int smb4b_pins[] = { 18, 19 }; 438static const int smb4c_pins[] = { 20, 21 }; 439static const int smb4d_pins[] = { 22, 23 }; 440static const int smb4den_pins[] = { 17 }; 441static const int smb5_pins[] = { 26, 27 }; 442static const int smb5b_pins[] = { 13, 12 }; 443static const int smb5c_pins[] = { 15, 14 }; 444static const int smb5d_pins[] = { 94, 93 }; 445static const int ga20kbc_pins[] = { 94, 93 }; 446 447static const int smb6_pins[] = { 172, 171 }; 448static const int smb6b_pins[] = { 2, 3 }; 449static const int smb6c_pins[] = { 0, 1 }; 450static const int smb6d_pins[] = { 10, 11 }; 451static const int smb7_pins[] = { 174, 173 }; 452static const int smb7b_pins[] = { 16, 141 }; 453static const int smb7c_pins[] = { 24, 25 }; 454static const int smb7d_pins[] = { 142, 143 }; 455static const int smb8_pins[] = { 129, 128 }; 456static const int smb9_pins[] = { 131, 130 }; 457static const int smb10_pins[] = { 133, 132 }; 458static const int smb11_pins[] = { 135, 134 }; 459static const int smb12_pins[] = { 221, 220 }; 460static const int smb13_pins[] = { 223, 222 }; 461static const int smb14_pins[] = { 22, 23 }; 462static const int smb14b_pins[] = { 32, 187 }; 463static const int smb15_pins[] = { 20, 21 }; 464static const int smb15b_pins[] = { 192, 191 }; 465 466static const int smb16_pins[] = { 10, 11 }; 467static const int smb16b_pins[] = { 218, 219 }; 468static const int smb17_pins[] = { 3, 2 }; 469static const int smb18_pins[] = { 0, 1 }; 470static const int smb19_pins[] = { 60, 59 }; 471static const int smb20_pins[] = { 234, 235 }; 472static const int smb21_pins[] = { 169, 170 }; 473static const int smb22_pins[] = { 40, 39 }; 474static const int smb23_pins[] = { 38, 37 }; 475static const int smb23b_pins[] = { 134, 135 }; 476 477static const int fanin0_pins[] = { 64 }; 478static const int fanin1_pins[] = { 65 }; 479static const int fanin2_pins[] = { 66 }; 480static const int fanin3_pins[] = { 67 }; 481static const int fanin4_pins[] = { 68 }; 482static const int fanin5_pins[] = { 69 }; 483static const int fanin6_pins[] = { 70 }; 484static const int fanin7_pins[] = { 71 }; 485static const int fanin8_pins[] = { 72 }; 486static const int fanin9_pins[] = { 73 }; 487static const int fanin10_pins[] = { 74 }; 488static const int fanin11_pins[] = { 75 }; 489static const int fanin12_pins[] = { 76 }; 490static const int fanin13_pins[] = { 77 }; 491static const int fanin14_pins[] = { 78 }; 492static const int fanin15_pins[] = { 79 }; 493static const int faninx_pins[] = { 175, 176, 177, 203 }; 494 495static const int pwm0_pins[] = { 80 }; 496static const int pwm1_pins[] = { 81 }; 497static const int pwm2_pins[] = { 82 }; 498static const int pwm3_pins[] = { 83 }; 499static const int pwm4_pins[] = { 144 }; 500static const int pwm5_pins[] = { 145 }; 501static const int pwm6_pins[] = { 146 }; 502static const int pwm7_pins[] = { 147 }; 503static const int pwm8_pins[] = { 220 }; 504static const int pwm9_pins[] = { 221 }; 505static const int pwm10_pins[] = { 234 }; 506static const int pwm11_pins[] = { 235 }; 507 508static const int uart1_pins[] = { 43, 45, 46, 47, 61, 62, 63 }; 509static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 }; 510 511static const int sg1mdio_pins[] = { 108, 109 }; 512 513static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, 514 213, 214, 215 }; 515static const int rg2mdio_pins[] = { 216, 217 }; 516 517static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, 518 213, 214, 215, 216, 217 }; 519 520static const int iox1_pins[] = { 0, 1, 2, 3 }; 521static const int iox2_pins[] = { 4, 5, 6, 7 }; 522static const int ioxh_pins[] = { 10, 11, 24, 25 }; 523 524static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 }; 525static const int mmcwp_pins[] = { 153 }; 526static const int mmccd_pins[] = { 155 }; 527static const int mmcrst_pins[] = { 155 }; 528static const int mmc8_pins[] = { 148, 149, 150, 151 }; 529 530static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 }; 531static const int r1err_pins[] = { 56 }; 532static const int r1md_pins[] = { 57, 58 }; 533static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 }; 534static const int r2err_pins[] = { 90 }; 535static const int r2md_pins[] = { 91, 92 }; 536static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 }; 537static const int sd1pwr_pins[] = { 143 }; 538 539static const int wdog1_pins[] = { 218 }; 540static const int wdog2_pins[] = { 219 }; 541 542static const int bmcuart0a_pins[] = { 41, 42 }; 543static const int bmcuart0b_pins[] = { 48, 49 }; 544static const int bmcuart1_pins[] = { 43, 44, 62, 63 }; 545 546static const int scipme_pins[] = { 169 }; 547static const int smi_pins[] = { 170 }; 548static const int serirq_pins[] = { 168 }; 549 550static const int clkout_pins[] = { 160 }; 551static const int clkreq_pins[] = { 231 }; 552 553static const int jtag2_pins[] = { 43, 44, 45, 46, 47 }; 554static const int gspi_pins[] = { 12, 13, 14, 15 }; 555 556static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 }; 557static const int spixcs1_pins[] = { 228 }; 558 559static const int spi1_pins[] = { 175, 176, 177 }; 560static const int pspi_pins[] = { 17, 18, 19 }; 561 562static const int spi0cs1_pins[] = { 32 }; 563 564static const int spi3_pins[] = { 183, 184, 185, 186 }; 565static const int spi3cs1_pins[] = { 187 }; 566static const int spi3quad_pins[] = { 188, 189 }; 567static const int spi3cs2_pins[] = { 188 }; 568static const int spi3cs3_pins[] = { 189 }; 569 570static const int ddc_pins[] = { 204, 205, 206, 207 }; 571 572static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 }; 573static const int lpcclk_pins[] = { 168 }; 574static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 }; 575 576static const int lkgpo0_pins[] = { 16 }; 577static const int lkgpo1_pins[] = { 8 }; 578static const int lkgpo2_pins[] = { 9 }; 579 580static const int nprd_smi_pins[] = { 190 }; 581 582static const int hgpio0_pins[] = { 20 }; 583static const int hgpio1_pins[] = { 21 }; 584static const int hgpio2_pins[] = { 22 }; 585static const int hgpio3_pins[] = { 23 }; 586static const int hgpio4_pins[] = { 24 }; 587static const int hgpio5_pins[] = { 25 }; 588static const int hgpio6_pins[] = { 59 }; 589static const int hgpio7_pins[] = { 60 }; 590 591/* 592 * pin: name, number 593 * group: name, npins, pins 594 * function: name, ngroups, groups 595 */ 596struct npcm8xx_pingroup { 597 const char *name; 598 const unsigned int *pins; 599 int npins; 600}; 601 602#define NPCM8XX_GRPS \ 603 NPCM8XX_GRP(gpi36), \ 604 NPCM8XX_GRP(gpi35), \ 605 NPCM8XX_GRP(tp_jtag3), \ 606 NPCM8XX_GRP(tp_uart), \ 607 NPCM8XX_GRP(tp_smb2), \ 608 NPCM8XX_GRP(tp_smb1), \ 609 NPCM8XX_GRP(tp_gpio7), \ 610 NPCM8XX_GRP(tp_gpio6), \ 611 NPCM8XX_GRP(tp_gpio5), \ 612 NPCM8XX_GRP(tp_gpio4), \ 613 NPCM8XX_GRP(tp_gpio3), \ 614 NPCM8XX_GRP(tp_gpio2), \ 615 NPCM8XX_GRP(tp_gpio1), \ 616 NPCM8XX_GRP(tp_gpio0), \ 617 NPCM8XX_GRP(tp_gpio2b), \ 618 NPCM8XX_GRP(tp_gpio1b), \ 619 NPCM8XX_GRP(tp_gpio0b), \ 620 NPCM8XX_GRP(vgadig), \ 621 NPCM8XX_GRP(nbu1crts), \ 622 NPCM8XX_GRP(fm2), \ 623 NPCM8XX_GRP(fm1), \ 624 NPCM8XX_GRP(fm0), \ 625 NPCM8XX_GRP(gpio1836), \ 626 NPCM8XX_GRP(gpio1889), \ 627 NPCM8XX_GRP(gpo187), \ 628 NPCM8XX_GRP(cp1urxd), \ 629 NPCM8XX_GRP(r3rxer), \ 630 NPCM8XX_GRP(cp1gpio2c), \ 631 NPCM8XX_GRP(cp1gpio3c), \ 632 NPCM8XX_GRP(cp1gpio0b), \ 633 NPCM8XX_GRP(cp1gpio1b), \ 634 NPCM8XX_GRP(cp1gpio2b), \ 635 NPCM8XX_GRP(cp1gpio3b), \ 636 NPCM8XX_GRP(cp1gpio4b), \ 637 NPCM8XX_GRP(cp1gpio5b), \ 638 NPCM8XX_GRP(cp1gpio6b), \ 639 NPCM8XX_GRP(cp1gpio7b), \ 640 NPCM8XX_GRP(cp1gpio0), \ 641 NPCM8XX_GRP(cp1gpio1), \ 642 NPCM8XX_GRP(cp1gpio2), \ 643 NPCM8XX_GRP(cp1gpio3), \ 644 NPCM8XX_GRP(cp1gpio4), \ 645 NPCM8XX_GRP(cp1gpio5), \ 646 NPCM8XX_GRP(cp1gpio6), \ 647 NPCM8XX_GRP(cp1gpio7), \ 648 NPCM8XX_GRP(cp1utxd), \ 649 NPCM8XX_GRP(spi1cs3), \ 650 NPCM8XX_GRP(spi1cs2), \ 651 NPCM8XX_GRP(spi1cs1), \ 652 NPCM8XX_GRP(spi1cs0), \ 653 NPCM8XX_GRP(spi1d23), \ 654 NPCM8XX_GRP(j2j3), \ 655 NPCM8XX_GRP(r3oen), \ 656 NPCM8XX_GRP(r2oen), \ 657 NPCM8XX_GRP(r1oen), \ 658 NPCM8XX_GRP(bu4b), \ 659 NPCM8XX_GRP(bu4), \ 660 NPCM8XX_GRP(bu5b), \ 661 NPCM8XX_GRP(bu5), \ 662 NPCM8XX_GRP(bu6), \ 663 NPCM8XX_GRP(rmii3), \ 664 NPCM8XX_GRP(jm1), \ 665 NPCM8XX_GRP(jm2), \ 666 NPCM8XX_GRP(tpgpio5b), \ 667 NPCM8XX_GRP(tpgpio4b), \ 668 NPCM8XX_GRP(clkrun), \ 669 NPCM8XX_GRP(i3c5), \ 670 NPCM8XX_GRP(i3c4), \ 671 NPCM8XX_GRP(i3c3), \ 672 NPCM8XX_GRP(i3c2), \ 673 NPCM8XX_GRP(i3c1), \ 674 NPCM8XX_GRP(i3c0), \ 675 NPCM8XX_GRP(hsi1a), \ 676 NPCM8XX_GRP(hsi2a), \ 677 NPCM8XX_GRP(hsi1b), \ 678 NPCM8XX_GRP(hsi2b), \ 679 NPCM8XX_GRP(hsi1c), \ 680 NPCM8XX_GRP(hsi2c), \ 681 NPCM8XX_GRP(smb0), \ 682 NPCM8XX_GRP(smb0b), \ 683 NPCM8XX_GRP(smb0c), \ 684 NPCM8XX_GRP(smb0d), \ 685 NPCM8XX_GRP(smb0den), \ 686 NPCM8XX_GRP(smb1), \ 687 NPCM8XX_GRP(smb1b), \ 688 NPCM8XX_GRP(smb1c), \ 689 NPCM8XX_GRP(smb1d), \ 690 NPCM8XX_GRP(smb2), \ 691 NPCM8XX_GRP(smb2b), \ 692 NPCM8XX_GRP(smb2c), \ 693 NPCM8XX_GRP(smb2d), \ 694 NPCM8XX_GRP(smb3), \ 695 NPCM8XX_GRP(smb3b), \ 696 NPCM8XX_GRP(smb3c), \ 697 NPCM8XX_GRP(smb3d), \ 698 NPCM8XX_GRP(smb4), \ 699 NPCM8XX_GRP(smb4b), \ 700 NPCM8XX_GRP(smb4c), \ 701 NPCM8XX_GRP(smb4d), \ 702 NPCM8XX_GRP(smb4den), \ 703 NPCM8XX_GRP(smb5), \ 704 NPCM8XX_GRP(smb5b), \ 705 NPCM8XX_GRP(smb5c), \ 706 NPCM8XX_GRP(smb5d), \ 707 NPCM8XX_GRP(ga20kbc), \ 708 NPCM8XX_GRP(smb6), \ 709 NPCM8XX_GRP(smb6b), \ 710 NPCM8XX_GRP(smb6c), \ 711 NPCM8XX_GRP(smb6d), \ 712 NPCM8XX_GRP(smb7), \ 713 NPCM8XX_GRP(smb7b), \ 714 NPCM8XX_GRP(smb7c), \ 715 NPCM8XX_GRP(smb7d), \ 716 NPCM8XX_GRP(smb8), \ 717 NPCM8XX_GRP(smb9), \ 718 NPCM8XX_GRP(smb10), \ 719 NPCM8XX_GRP(smb11), \ 720 NPCM8XX_GRP(smb12), \ 721 NPCM8XX_GRP(smb13), \ 722 NPCM8XX_GRP(smb14), \ 723 NPCM8XX_GRP(smb14b), \ 724 NPCM8XX_GRP(smb15), \ 725 NPCM8XX_GRP(smb15b), \ 726 NPCM8XX_GRP(smb16), \ 727 NPCM8XX_GRP(smb16b), \ 728 NPCM8XX_GRP(smb17), \ 729 NPCM8XX_GRP(smb18), \ 730 NPCM8XX_GRP(smb19), \ 731 NPCM8XX_GRP(smb20), \ 732 NPCM8XX_GRP(smb21), \ 733 NPCM8XX_GRP(smb22), \ 734 NPCM8XX_GRP(smb23), \ 735 NPCM8XX_GRP(smb23b), \ 736 NPCM8XX_GRP(fanin0), \ 737 NPCM8XX_GRP(fanin1), \ 738 NPCM8XX_GRP(fanin2), \ 739 NPCM8XX_GRP(fanin3), \ 740 NPCM8XX_GRP(fanin4), \ 741 NPCM8XX_GRP(fanin5), \ 742 NPCM8XX_GRP(fanin6), \ 743 NPCM8XX_GRP(fanin7), \ 744 NPCM8XX_GRP(fanin8), \ 745 NPCM8XX_GRP(fanin9), \ 746 NPCM8XX_GRP(fanin10), \ 747 NPCM8XX_GRP(fanin11), \ 748 NPCM8XX_GRP(fanin12), \ 749 NPCM8XX_GRP(fanin13), \ 750 NPCM8XX_GRP(fanin14), \ 751 NPCM8XX_GRP(fanin15), \ 752 NPCM8XX_GRP(faninx), \ 753 NPCM8XX_GRP(pwm0), \ 754 NPCM8XX_GRP(pwm1), \ 755 NPCM8XX_GRP(pwm2), \ 756 NPCM8XX_GRP(pwm3), \ 757 NPCM8XX_GRP(pwm4), \ 758 NPCM8XX_GRP(pwm5), \ 759 NPCM8XX_GRP(pwm6), \ 760 NPCM8XX_GRP(pwm7), \ 761 NPCM8XX_GRP(pwm8), \ 762 NPCM8XX_GRP(pwm9), \ 763 NPCM8XX_GRP(pwm10), \ 764 NPCM8XX_GRP(pwm11), \ 765 NPCM8XX_GRP(sg1mdio), \ 766 NPCM8XX_GRP(rg2), \ 767 NPCM8XX_GRP(rg2mdio), \ 768 NPCM8XX_GRP(ddr), \ 769 NPCM8XX_GRP(uart1), \ 770 NPCM8XX_GRP(uart2), \ 771 NPCM8XX_GRP(bmcuart0a), \ 772 NPCM8XX_GRP(bmcuart0b), \ 773 NPCM8XX_GRP(bmcuart1), \ 774 NPCM8XX_GRP(iox1), \ 775 NPCM8XX_GRP(iox2), \ 776 NPCM8XX_GRP(ioxh), \ 777 NPCM8XX_GRP(gspi), \ 778 NPCM8XX_GRP(mmc), \ 779 NPCM8XX_GRP(mmcwp), \ 780 NPCM8XX_GRP(mmccd), \ 781 NPCM8XX_GRP(mmcrst), \ 782 NPCM8XX_GRP(mmc8), \ 783 NPCM8XX_GRP(r1), \ 784 NPCM8XX_GRP(r1err), \ 785 NPCM8XX_GRP(r1md), \ 786 NPCM8XX_GRP(r2), \ 787 NPCM8XX_GRP(r2err), \ 788 NPCM8XX_GRP(r2md), \ 789 NPCM8XX_GRP(sd1), \ 790 NPCM8XX_GRP(sd1pwr), \ 791 NPCM8XX_GRP(wdog1), \ 792 NPCM8XX_GRP(wdog2), \ 793 NPCM8XX_GRP(scipme), \ 794 NPCM8XX_GRP(smi), \ 795 NPCM8XX_GRP(serirq), \ 796 NPCM8XX_GRP(jtag2), \ 797 NPCM8XX_GRP(spix), \ 798 NPCM8XX_GRP(spixcs1), \ 799 NPCM8XX_GRP(spi1), \ 800 NPCM8XX_GRP(pspi), \ 801 NPCM8XX_GRP(ddc), \ 802 NPCM8XX_GRP(clkreq), \ 803 NPCM8XX_GRP(clkout), \ 804 NPCM8XX_GRP(spi3), \ 805 NPCM8XX_GRP(spi3cs1), \ 806 NPCM8XX_GRP(spi3quad), \ 807 NPCM8XX_GRP(spi3cs2), \ 808 NPCM8XX_GRP(spi3cs3), \ 809 NPCM8XX_GRP(spi0cs1), \ 810 NPCM8XX_GRP(lpc), \ 811 NPCM8XX_GRP(lpcclk), \ 812 NPCM8XX_GRP(espi), \ 813 NPCM8XX_GRP(lkgpo0), \ 814 NPCM8XX_GRP(lkgpo1), \ 815 NPCM8XX_GRP(lkgpo2), \ 816 NPCM8XX_GRP(nprd_smi), \ 817 NPCM8XX_GRP(hgpio0), \ 818 NPCM8XX_GRP(hgpio1), \ 819 NPCM8XX_GRP(hgpio2), \ 820 NPCM8XX_GRP(hgpio3), \ 821 NPCM8XX_GRP(hgpio4), \ 822 NPCM8XX_GRP(hgpio5), \ 823 NPCM8XX_GRP(hgpio6), \ 824 NPCM8XX_GRP(hgpio7), \ 825 \ 826 827enum { 828#define NPCM8XX_GRP(x) fn_ ## x 829 NPCM8XX_GRPS 830 NPCM8XX_GRP(none), 831 NPCM8XX_GRP(gpio), 832#undef NPCM8XX_GRP 833}; 834 835static struct npcm8xx_pingroup npcm8xx_pingroups[] = { 836#define NPCM8XX_GRP(x) { .name = #x, .pins = x ## _pins, \ 837 .npins = ARRAY_SIZE(x ## _pins) } 838 NPCM8XX_GRPS 839#undef NPCM8XX_GRP 840}; 841 842#define NPCM8XX_SFUNC(a) NPCM8XX_FUNC(a, #a) 843#define NPCM8XX_FUNC(a, b...) static const char *a ## _grp[] = { b } 844#define NPCM8XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \ 845 .groups = nm ## _grp } 846struct npcm8xx_func { 847 const char *name; 848 const unsigned int ngroups; 849 const char *const *groups; 850}; 851 852NPCM8XX_SFUNC(gpi36); 853NPCM8XX_SFUNC(gpi35); 854NPCM8XX_SFUNC(tp_jtag3); 855NPCM8XX_SFUNC(tp_uart); 856NPCM8XX_SFUNC(tp_smb2); 857NPCM8XX_SFUNC(tp_smb1); 858NPCM8XX_SFUNC(tp_gpio7); 859NPCM8XX_SFUNC(tp_gpio6); 860NPCM8XX_SFUNC(tp_gpio5); 861NPCM8XX_SFUNC(tp_gpio4); 862NPCM8XX_SFUNC(tp_gpio3); 863NPCM8XX_SFUNC(tp_gpio2); 864NPCM8XX_SFUNC(tp_gpio1); 865NPCM8XX_SFUNC(tp_gpio0); 866NPCM8XX_SFUNC(tp_gpio2b); 867NPCM8XX_SFUNC(tp_gpio1b); 868NPCM8XX_SFUNC(tp_gpio0b); 869NPCM8XX_SFUNC(vgadig); 870NPCM8XX_SFUNC(nbu1crts); 871NPCM8XX_SFUNC(fm2); 872NPCM8XX_SFUNC(fm1); 873NPCM8XX_SFUNC(fm0); 874NPCM8XX_SFUNC(gpio1836); 875NPCM8XX_SFUNC(gpio1889); 876NPCM8XX_SFUNC(gpo187); 877NPCM8XX_SFUNC(cp1urxd); 878NPCM8XX_SFUNC(r3rxer); 879NPCM8XX_SFUNC(cp1gpio2c); 880NPCM8XX_SFUNC(cp1gpio3c); 881NPCM8XX_SFUNC(cp1gpio0b); 882NPCM8XX_SFUNC(cp1gpio1b); 883NPCM8XX_SFUNC(cp1gpio2b); 884NPCM8XX_SFUNC(cp1gpio3b); 885NPCM8XX_SFUNC(cp1gpio4b); 886NPCM8XX_SFUNC(cp1gpio5b); 887NPCM8XX_SFUNC(cp1gpio6b); 888NPCM8XX_SFUNC(cp1gpio7b); 889NPCM8XX_SFUNC(cp1gpio0); 890NPCM8XX_SFUNC(cp1gpio1); 891NPCM8XX_SFUNC(cp1gpio2); 892NPCM8XX_SFUNC(cp1gpio3); 893NPCM8XX_SFUNC(cp1gpio4); 894NPCM8XX_SFUNC(cp1gpio5); 895NPCM8XX_SFUNC(cp1gpio6); 896NPCM8XX_SFUNC(cp1gpio7); 897NPCM8XX_SFUNC(cp1utxd); 898NPCM8XX_SFUNC(spi1cs3); 899NPCM8XX_SFUNC(spi1cs2); 900NPCM8XX_SFUNC(spi1cs1); 901NPCM8XX_SFUNC(spi1cs0); 902NPCM8XX_SFUNC(spi1d23); 903NPCM8XX_SFUNC(j2j3); 904NPCM8XX_SFUNC(r3oen); 905NPCM8XX_SFUNC(r2oen); 906NPCM8XX_SFUNC(r1oen); 907NPCM8XX_SFUNC(bu4b); 908NPCM8XX_SFUNC(bu4); 909NPCM8XX_SFUNC(bu5b); 910NPCM8XX_SFUNC(bu5); 911NPCM8XX_SFUNC(bu6); 912NPCM8XX_SFUNC(rmii3); 913NPCM8XX_SFUNC(jm1); 914NPCM8XX_SFUNC(jm2); 915NPCM8XX_SFUNC(tpgpio5b); 916NPCM8XX_SFUNC(tpgpio4b); 917NPCM8XX_SFUNC(clkrun); 918NPCM8XX_SFUNC(i3c5); 919NPCM8XX_SFUNC(i3c4); 920NPCM8XX_SFUNC(i3c3); 921NPCM8XX_SFUNC(i3c2); 922NPCM8XX_SFUNC(i3c1); 923NPCM8XX_SFUNC(i3c0); 924NPCM8XX_SFUNC(hsi1a); 925NPCM8XX_SFUNC(hsi2a); 926NPCM8XX_SFUNC(hsi1b); 927NPCM8XX_SFUNC(hsi2b); 928NPCM8XX_SFUNC(hsi1c); 929NPCM8XX_SFUNC(hsi2c); 930NPCM8XX_SFUNC(smb0); 931NPCM8XX_SFUNC(smb0b); 932NPCM8XX_SFUNC(smb0c); 933NPCM8XX_SFUNC(smb0d); 934NPCM8XX_SFUNC(smb0den); 935NPCM8XX_SFUNC(smb1); 936NPCM8XX_SFUNC(smb1b); 937NPCM8XX_SFUNC(smb1c); 938NPCM8XX_SFUNC(smb1d); 939NPCM8XX_SFUNC(smb2); 940NPCM8XX_SFUNC(smb2b); 941NPCM8XX_SFUNC(smb2c); 942NPCM8XX_SFUNC(smb2d); 943NPCM8XX_SFUNC(smb3); 944NPCM8XX_SFUNC(smb3b); 945NPCM8XX_SFUNC(smb3c); 946NPCM8XX_SFUNC(smb3d); 947NPCM8XX_SFUNC(smb4); 948NPCM8XX_SFUNC(smb4b); 949NPCM8XX_SFUNC(smb4c); 950NPCM8XX_SFUNC(smb4d); 951NPCM8XX_SFUNC(smb4den); 952NPCM8XX_SFUNC(smb5); 953NPCM8XX_SFUNC(smb5b); 954NPCM8XX_SFUNC(smb5c); 955NPCM8XX_SFUNC(smb5d); 956NPCM8XX_SFUNC(ga20kbc); 957NPCM8XX_SFUNC(smb6); 958NPCM8XX_SFUNC(smb6b); 959NPCM8XX_SFUNC(smb6c); 960NPCM8XX_SFUNC(smb6d); 961NPCM8XX_SFUNC(smb7); 962NPCM8XX_SFUNC(smb7b); 963NPCM8XX_SFUNC(smb7c); 964NPCM8XX_SFUNC(smb7d); 965NPCM8XX_SFUNC(smb8); 966NPCM8XX_SFUNC(smb9); 967NPCM8XX_SFUNC(smb10); 968NPCM8XX_SFUNC(smb11); 969NPCM8XX_SFUNC(smb12); 970NPCM8XX_SFUNC(smb13); 971NPCM8XX_SFUNC(smb14); 972NPCM8XX_SFUNC(smb14b); 973NPCM8XX_SFUNC(smb15); 974NPCM8XX_SFUNC(smb16); 975NPCM8XX_SFUNC(smb16b); 976NPCM8XX_SFUNC(smb17); 977NPCM8XX_SFUNC(smb18); 978NPCM8XX_SFUNC(smb19); 979NPCM8XX_SFUNC(smb20); 980NPCM8XX_SFUNC(smb21); 981NPCM8XX_SFUNC(smb22); 982NPCM8XX_SFUNC(smb23); 983NPCM8XX_SFUNC(smb23b); 984NPCM8XX_SFUNC(fanin0); 985NPCM8XX_SFUNC(fanin1); 986NPCM8XX_SFUNC(fanin2); 987NPCM8XX_SFUNC(fanin3); 988NPCM8XX_SFUNC(fanin4); 989NPCM8XX_SFUNC(fanin5); 990NPCM8XX_SFUNC(fanin6); 991NPCM8XX_SFUNC(fanin7); 992NPCM8XX_SFUNC(fanin8); 993NPCM8XX_SFUNC(fanin9); 994NPCM8XX_SFUNC(fanin10); 995NPCM8XX_SFUNC(fanin11); 996NPCM8XX_SFUNC(fanin12); 997NPCM8XX_SFUNC(fanin13); 998NPCM8XX_SFUNC(fanin14); 999NPCM8XX_SFUNC(fanin15); 1000NPCM8XX_SFUNC(faninx); 1001NPCM8XX_SFUNC(pwm0); 1002NPCM8XX_SFUNC(pwm1); 1003NPCM8XX_SFUNC(pwm2); 1004NPCM8XX_SFUNC(pwm3); 1005NPCM8XX_SFUNC(pwm4); 1006NPCM8XX_SFUNC(pwm5); 1007NPCM8XX_SFUNC(pwm6); 1008NPCM8XX_SFUNC(pwm7); 1009NPCM8XX_SFUNC(pwm8); 1010NPCM8XX_SFUNC(pwm9); 1011NPCM8XX_SFUNC(pwm10); 1012NPCM8XX_SFUNC(pwm11); 1013NPCM8XX_SFUNC(sg1mdio); 1014NPCM8XX_SFUNC(rg2); 1015NPCM8XX_SFUNC(rg2mdio); 1016NPCM8XX_SFUNC(ddr); 1017NPCM8XX_SFUNC(uart1); 1018NPCM8XX_SFUNC(uart2); 1019NPCM8XX_SFUNC(bmcuart0a); 1020NPCM8XX_SFUNC(bmcuart0b); 1021NPCM8XX_SFUNC(bmcuart1); 1022NPCM8XX_SFUNC(iox1); 1023NPCM8XX_SFUNC(iox2); 1024NPCM8XX_SFUNC(ioxh); 1025NPCM8XX_SFUNC(gspi); 1026NPCM8XX_SFUNC(mmc); 1027NPCM8XX_SFUNC(mmcwp); 1028NPCM8XX_SFUNC(mmccd); 1029NPCM8XX_SFUNC(mmcrst); 1030NPCM8XX_SFUNC(mmc8); 1031NPCM8XX_SFUNC(r1); 1032NPCM8XX_SFUNC(r1err); 1033NPCM8XX_SFUNC(r1md); 1034NPCM8XX_SFUNC(r2); 1035NPCM8XX_SFUNC(r2err); 1036NPCM8XX_SFUNC(r2md); 1037NPCM8XX_SFUNC(sd1); 1038NPCM8XX_SFUNC(sd1pwr); 1039NPCM8XX_SFUNC(wdog1); 1040NPCM8XX_SFUNC(wdog2); 1041NPCM8XX_SFUNC(scipme); 1042NPCM8XX_SFUNC(smi); 1043NPCM8XX_SFUNC(serirq); 1044NPCM8XX_SFUNC(jtag2); 1045NPCM8XX_SFUNC(spix); 1046NPCM8XX_SFUNC(spixcs1); 1047NPCM8XX_SFUNC(spi1); 1048NPCM8XX_SFUNC(pspi); 1049NPCM8XX_SFUNC(ddc); 1050NPCM8XX_SFUNC(clkreq); 1051NPCM8XX_SFUNC(clkout); 1052NPCM8XX_SFUNC(spi3); 1053NPCM8XX_SFUNC(spi3cs1); 1054NPCM8XX_SFUNC(spi3quad); 1055NPCM8XX_SFUNC(spi3cs2); 1056NPCM8XX_SFUNC(spi3cs3); 1057NPCM8XX_SFUNC(spi0cs1); 1058NPCM8XX_SFUNC(lpc); 1059NPCM8XX_SFUNC(lpcclk); 1060NPCM8XX_SFUNC(espi); 1061NPCM8XX_SFUNC(lkgpo0); 1062NPCM8XX_SFUNC(lkgpo1); 1063NPCM8XX_SFUNC(lkgpo2); 1064NPCM8XX_SFUNC(nprd_smi); 1065NPCM8XX_SFUNC(hgpio0); 1066NPCM8XX_SFUNC(hgpio1); 1067NPCM8XX_SFUNC(hgpio2); 1068NPCM8XX_SFUNC(hgpio3); 1069NPCM8XX_SFUNC(hgpio4); 1070NPCM8XX_SFUNC(hgpio5); 1071NPCM8XX_SFUNC(hgpio6); 1072NPCM8XX_SFUNC(hgpio7); 1073 1074/* Function names */ 1075static struct npcm8xx_func npcm8xx_funcs[] = { 1076 NPCM8XX_MKFUNC(gpi36), 1077 NPCM8XX_MKFUNC(gpi35), 1078 NPCM8XX_MKFUNC(tp_jtag3), 1079 NPCM8XX_MKFUNC(tp_uart), 1080 NPCM8XX_MKFUNC(tp_smb2), 1081 NPCM8XX_MKFUNC(tp_smb1), 1082 NPCM8XX_MKFUNC(tp_gpio7), 1083 NPCM8XX_MKFUNC(tp_gpio6), 1084 NPCM8XX_MKFUNC(tp_gpio5), 1085 NPCM8XX_MKFUNC(tp_gpio4), 1086 NPCM8XX_MKFUNC(tp_gpio3), 1087 NPCM8XX_MKFUNC(tp_gpio2), 1088 NPCM8XX_MKFUNC(tp_gpio1), 1089 NPCM8XX_MKFUNC(tp_gpio0), 1090 NPCM8XX_MKFUNC(tp_gpio2b), 1091 NPCM8XX_MKFUNC(tp_gpio1b), 1092 NPCM8XX_MKFUNC(tp_gpio0b), 1093 NPCM8XX_MKFUNC(vgadig), 1094 NPCM8XX_MKFUNC(nbu1crts), 1095 NPCM8XX_MKFUNC(fm2), 1096 NPCM8XX_MKFUNC(fm1), 1097 NPCM8XX_MKFUNC(fm0), 1098 NPCM8XX_MKFUNC(gpio1836), 1099 NPCM8XX_MKFUNC(gpio1889), 1100 NPCM8XX_MKFUNC(gpo187), 1101 NPCM8XX_MKFUNC(cp1urxd), 1102 NPCM8XX_MKFUNC(r3rxer), 1103 NPCM8XX_MKFUNC(cp1gpio2c), 1104 NPCM8XX_MKFUNC(cp1gpio3c), 1105 NPCM8XX_MKFUNC(cp1gpio0b), 1106 NPCM8XX_MKFUNC(cp1gpio1b), 1107 NPCM8XX_MKFUNC(cp1gpio2b), 1108 NPCM8XX_MKFUNC(cp1gpio3b), 1109 NPCM8XX_MKFUNC(cp1gpio4b), 1110 NPCM8XX_MKFUNC(cp1gpio5b), 1111 NPCM8XX_MKFUNC(cp1gpio6b), 1112 NPCM8XX_MKFUNC(cp1gpio7b), 1113 NPCM8XX_MKFUNC(cp1gpio0), 1114 NPCM8XX_MKFUNC(cp1gpio1), 1115 NPCM8XX_MKFUNC(cp1gpio2), 1116 NPCM8XX_MKFUNC(cp1gpio3), 1117 NPCM8XX_MKFUNC(cp1gpio4), 1118 NPCM8XX_MKFUNC(cp1gpio5), 1119 NPCM8XX_MKFUNC(cp1gpio6), 1120 NPCM8XX_MKFUNC(cp1gpio7), 1121 NPCM8XX_MKFUNC(cp1utxd), 1122 NPCM8XX_MKFUNC(spi1cs3), 1123 NPCM8XX_MKFUNC(spi1cs2), 1124 NPCM8XX_MKFUNC(spi1cs1), 1125 NPCM8XX_MKFUNC(spi1cs0), 1126 NPCM8XX_MKFUNC(spi1d23), 1127 NPCM8XX_MKFUNC(j2j3), 1128 NPCM8XX_MKFUNC(r3oen), 1129 NPCM8XX_MKFUNC(r2oen), 1130 NPCM8XX_MKFUNC(r1oen), 1131 NPCM8XX_MKFUNC(bu4b), 1132 NPCM8XX_MKFUNC(bu4), 1133 NPCM8XX_MKFUNC(bu5b), 1134 NPCM8XX_MKFUNC(bu5), 1135 NPCM8XX_MKFUNC(bu6), 1136 NPCM8XX_MKFUNC(rmii3), 1137 NPCM8XX_MKFUNC(jm1), 1138 NPCM8XX_MKFUNC(jm2), 1139 NPCM8XX_MKFUNC(tpgpio5b), 1140 NPCM8XX_MKFUNC(tpgpio4b), 1141 NPCM8XX_MKFUNC(clkrun), 1142 NPCM8XX_MKFUNC(i3c5), 1143 NPCM8XX_MKFUNC(i3c4), 1144 NPCM8XX_MKFUNC(i3c3), 1145 NPCM8XX_MKFUNC(i3c2), 1146 NPCM8XX_MKFUNC(i3c1), 1147 NPCM8XX_MKFUNC(i3c0), 1148 NPCM8XX_MKFUNC(hsi1a), 1149 NPCM8XX_MKFUNC(hsi2a), 1150 NPCM8XX_MKFUNC(hsi1b), 1151 NPCM8XX_MKFUNC(hsi2b), 1152 NPCM8XX_MKFUNC(hsi1c), 1153 NPCM8XX_MKFUNC(hsi2c), 1154 NPCM8XX_MKFUNC(smb0), 1155 NPCM8XX_MKFUNC(smb0b), 1156 NPCM8XX_MKFUNC(smb0c), 1157 NPCM8XX_MKFUNC(smb0d), 1158 NPCM8XX_MKFUNC(smb0den), 1159 NPCM8XX_MKFUNC(smb1), 1160 NPCM8XX_MKFUNC(smb1b), 1161 NPCM8XX_MKFUNC(smb1c), 1162 NPCM8XX_MKFUNC(smb1d), 1163 NPCM8XX_MKFUNC(smb2), 1164 NPCM8XX_MKFUNC(smb2b), 1165 NPCM8XX_MKFUNC(smb2c), 1166 NPCM8XX_MKFUNC(smb2d), 1167 NPCM8XX_MKFUNC(smb3), 1168 NPCM8XX_MKFUNC(smb3b), 1169 NPCM8XX_MKFUNC(smb3c), 1170 NPCM8XX_MKFUNC(smb3d), 1171 NPCM8XX_MKFUNC(smb4), 1172 NPCM8XX_MKFUNC(smb4b), 1173 NPCM8XX_MKFUNC(smb4c), 1174 NPCM8XX_MKFUNC(smb4d), 1175 NPCM8XX_MKFUNC(smb4den), 1176 NPCM8XX_MKFUNC(smb5), 1177 NPCM8XX_MKFUNC(smb5b), 1178 NPCM8XX_MKFUNC(smb5c), 1179 NPCM8XX_MKFUNC(smb5d), 1180 NPCM8XX_MKFUNC(ga20kbc), 1181 NPCM8XX_MKFUNC(smb6), 1182 NPCM8XX_MKFUNC(smb6b), 1183 NPCM8XX_MKFUNC(smb6c), 1184 NPCM8XX_MKFUNC(smb6d), 1185 NPCM8XX_MKFUNC(smb7), 1186 NPCM8XX_MKFUNC(smb7b), 1187 NPCM8XX_MKFUNC(smb7c), 1188 NPCM8XX_MKFUNC(smb7d), 1189 NPCM8XX_MKFUNC(smb8), 1190 NPCM8XX_MKFUNC(smb9), 1191 NPCM8XX_MKFUNC(smb10), 1192 NPCM8XX_MKFUNC(smb11), 1193 NPCM8XX_MKFUNC(smb12), 1194 NPCM8XX_MKFUNC(smb13), 1195 NPCM8XX_MKFUNC(smb14), 1196 NPCM8XX_MKFUNC(smb14b), 1197 NPCM8XX_MKFUNC(smb15), 1198 NPCM8XX_MKFUNC(smb16), 1199 NPCM8XX_MKFUNC(smb16b), 1200 NPCM8XX_MKFUNC(smb17), 1201 NPCM8XX_MKFUNC(smb18), 1202 NPCM8XX_MKFUNC(smb19), 1203 NPCM8XX_MKFUNC(smb20), 1204 NPCM8XX_MKFUNC(smb21), 1205 NPCM8XX_MKFUNC(smb22), 1206 NPCM8XX_MKFUNC(smb23), 1207 NPCM8XX_MKFUNC(smb23b), 1208 NPCM8XX_MKFUNC(fanin0), 1209 NPCM8XX_MKFUNC(fanin1), 1210 NPCM8XX_MKFUNC(fanin2), 1211 NPCM8XX_MKFUNC(fanin3), 1212 NPCM8XX_MKFUNC(fanin4), 1213 NPCM8XX_MKFUNC(fanin5), 1214 NPCM8XX_MKFUNC(fanin6), 1215 NPCM8XX_MKFUNC(fanin7), 1216 NPCM8XX_MKFUNC(fanin8), 1217 NPCM8XX_MKFUNC(fanin9), 1218 NPCM8XX_MKFUNC(fanin10), 1219 NPCM8XX_MKFUNC(fanin11), 1220 NPCM8XX_MKFUNC(fanin12), 1221 NPCM8XX_MKFUNC(fanin13), 1222 NPCM8XX_MKFUNC(fanin14), 1223 NPCM8XX_MKFUNC(fanin15), 1224 NPCM8XX_MKFUNC(faninx), 1225 NPCM8XX_MKFUNC(pwm0), 1226 NPCM8XX_MKFUNC(pwm1), 1227 NPCM8XX_MKFUNC(pwm2), 1228 NPCM8XX_MKFUNC(pwm3), 1229 NPCM8XX_MKFUNC(pwm4), 1230 NPCM8XX_MKFUNC(pwm5), 1231 NPCM8XX_MKFUNC(pwm6), 1232 NPCM8XX_MKFUNC(pwm7), 1233 NPCM8XX_MKFUNC(pwm8), 1234 NPCM8XX_MKFUNC(pwm9), 1235 NPCM8XX_MKFUNC(pwm10), 1236 NPCM8XX_MKFUNC(pwm11), 1237 NPCM8XX_MKFUNC(sg1mdio), 1238 NPCM8XX_MKFUNC(rg2), 1239 NPCM8XX_MKFUNC(rg2mdio), 1240 NPCM8XX_MKFUNC(ddr), 1241 NPCM8XX_MKFUNC(uart1), 1242 NPCM8XX_MKFUNC(uart2), 1243 NPCM8XX_MKFUNC(bmcuart0a), 1244 NPCM8XX_MKFUNC(bmcuart0b), 1245 NPCM8XX_MKFUNC(bmcuart1), 1246 NPCM8XX_MKFUNC(iox1), 1247 NPCM8XX_MKFUNC(iox2), 1248 NPCM8XX_MKFUNC(ioxh), 1249 NPCM8XX_MKFUNC(gspi), 1250 NPCM8XX_MKFUNC(mmc), 1251 NPCM8XX_MKFUNC(mmcwp), 1252 NPCM8XX_MKFUNC(mmccd), 1253 NPCM8XX_MKFUNC(mmcrst), 1254 NPCM8XX_MKFUNC(mmc8), 1255 NPCM8XX_MKFUNC(r1), 1256 NPCM8XX_MKFUNC(r1err), 1257 NPCM8XX_MKFUNC(r1md), 1258 NPCM8XX_MKFUNC(r2), 1259 NPCM8XX_MKFUNC(r2err), 1260 NPCM8XX_MKFUNC(r2md), 1261 NPCM8XX_MKFUNC(sd1), 1262 NPCM8XX_MKFUNC(sd1pwr), 1263 NPCM8XX_MKFUNC(wdog1), 1264 NPCM8XX_MKFUNC(wdog2), 1265 NPCM8XX_MKFUNC(scipme), 1266 NPCM8XX_MKFUNC(smi), 1267 NPCM8XX_MKFUNC(serirq), 1268 NPCM8XX_MKFUNC(jtag2), 1269 NPCM8XX_MKFUNC(spix), 1270 NPCM8XX_MKFUNC(spixcs1), 1271 NPCM8XX_MKFUNC(spi1), 1272 NPCM8XX_MKFUNC(pspi), 1273 NPCM8XX_MKFUNC(ddc), 1274 NPCM8XX_MKFUNC(clkreq), 1275 NPCM8XX_MKFUNC(clkout), 1276 NPCM8XX_MKFUNC(spi3), 1277 NPCM8XX_MKFUNC(spi3cs1), 1278 NPCM8XX_MKFUNC(spi3quad), 1279 NPCM8XX_MKFUNC(spi3cs2), 1280 NPCM8XX_MKFUNC(spi3cs3), 1281 NPCM8XX_MKFUNC(spi0cs1), 1282 NPCM8XX_MKFUNC(lpc), 1283 NPCM8XX_MKFUNC(lpcclk), 1284 NPCM8XX_MKFUNC(espi), 1285 NPCM8XX_MKFUNC(lkgpo0), 1286 NPCM8XX_MKFUNC(lkgpo1), 1287 NPCM8XX_MKFUNC(lkgpo2), 1288 NPCM8XX_MKFUNC(nprd_smi), 1289 NPCM8XX_MKFUNC(hgpio0), 1290 NPCM8XX_MKFUNC(hgpio1), 1291 NPCM8XX_MKFUNC(hgpio2), 1292 NPCM8XX_MKFUNC(hgpio3), 1293 NPCM8XX_MKFUNC(hgpio4), 1294 NPCM8XX_MKFUNC(hgpio5), 1295 NPCM8XX_MKFUNC(hgpio6), 1296 NPCM8XX_MKFUNC(hgpio7), 1297}; 1298 1299#define NPCM8XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q) \ 1300 [a] { .fn0 = fn_ ## b, .reg0 = NPCM8XX_GCR_ ## c, .bit0 = d, \ 1301 .fn1 = fn_ ## e, .reg1 = NPCM8XX_GCR_ ## f, .bit1 = g, \ 1302 .fn2 = fn_ ## h, .reg2 = NPCM8XX_GCR_ ## i, .bit2 = j, \ 1303 .fn3 = fn_ ## k, .reg3 = NPCM8XX_GCR_ ## l, .bit3 = m, \ 1304 .fn4 = fn_ ## n, .reg4 = NPCM8XX_GCR_ ## o, .bit4 = p, \ 1305 .flag = q } 1306 1307/* Drive strength controlled by NPCM8XX_GP_N_ODSC */ 1308#define DRIVE_STRENGTH_LO_SHIFT 8 1309#define DRIVE_STRENGTH_HI_SHIFT 12 1310#define DRIVE_STRENGTH_MASK GENMASK(15, 8) 1311 1312#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ 1313 ((hi) << DRIVE_STRENGTH_HI_SHIFT)) 1314#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & GENMASK(3, 0)) 1315#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & GENMASK(3, 0)) 1316 1317#define GPI BIT(0) /* Not GPO */ 1318#define GPO BIT(1) /* Not GPI */ 1319#define SLEW BIT(2) /* Has Slew Control, NPCM8XX_GP_N_OSRC */ 1320#define SLEWLPC BIT(3) /* Has Slew Control, SRCNT.3 */ 1321 1322struct npcm8xx_pincfg { 1323 int flag; 1324 int fn0, reg0, bit0; 1325 int fn1, reg1, bit1; 1326 int fn2, reg2, bit2; 1327 int fn3, reg3, bit3; 1328 int fn4, reg4, bit4; 1329}; 1330 1331static const struct npcm8xx_pincfg pincfg[] = { 1332 /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FUNCTION 4 FUNCTION 5 FLAGS */ 1333 NPCM8XX_PINCFG(0, iox1, MFSEL1, 30, smb6c, I2CSEGSEL, 25, smb18, MFSEL5, 26, none, NONE, 0, none, NONE, 0, SLEW), 1334 NPCM8XX_PINCFG(1, iox1, MFSEL1, 30, smb6c, I2CSEGSEL, 25, smb18, MFSEL5, 26, none, NONE, 0, none, NONE, 0, SLEW), 1335 NPCM8XX_PINCFG(2, iox1, MFSEL1, 30, smb6b, I2CSEGSEL, 24, smb17, MFSEL5, 25, none, NONE, 0, none, NONE, 0, SLEW), 1336 NPCM8XX_PINCFG(3, iox1, MFSEL1, 30, smb6b, I2CSEGSEL, 24, smb17, MFSEL5, 25, none, NONE, 0, none, NONE, 0, SLEW), 1337 NPCM8XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1338 NPCM8XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1339 NPCM8XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1340 NPCM8XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1341 NPCM8XX_PINCFG(8, lkgpo1, FLOCKR1, 4, tp_gpio0b, MFSEL7, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1342 NPCM8XX_PINCFG(9, lkgpo2, FLOCKR1, 8, tp_gpio1b, MFSEL7, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1343 NPCM8XX_PINCFG(10, ioxh, MFSEL3, 18, smb6d, I2CSEGSEL, 26, smb16, MFSEL5, 24, none, NONE, 0, none, NONE, 0, SLEW), 1344 NPCM8XX_PINCFG(11, ioxh, MFSEL3, 18, smb6d, I2CSEGSEL, 26, smb16, MFSEL5, 24, none, NONE, 0, none, NONE, 0, SLEW), 1345 NPCM8XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1346 NPCM8XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1347 NPCM8XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1348 NPCM8XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1349 NPCM8XX_PINCFG(16, lkgpo0, FLOCKR1, 0, smb7b, I2CSEGSEL, 27, tp_gpio2b, MFSEL7, 10, none, NONE, 0, none, NONE, 0, SLEW), 1350 NPCM8XX_PINCFG(17, pspi, MFSEL3, 13, cp1gpio5, MFSEL6, 7, smb4den, I2CSEGSEL, 23, none, NONE, 0, none, NONE, 0, SLEW), 1351 NPCM8XX_PINCFG(18, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1352 NPCM8XX_PINCFG(19, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1353 NPCM8XX_PINCFG(20, hgpio0, MFSEL2, 24, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW), 1354 NPCM8XX_PINCFG(21, hgpio1, MFSEL2, 25, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW), 1355 NPCM8XX_PINCFG(22, hgpio2, MFSEL2, 26, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, none, NONE, 0, none, NONE, 0, SLEW), 1356 NPCM8XX_PINCFG(23, hgpio3, MFSEL2, 27, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, none, NONE, 0, none, NONE, 0, SLEW), 1357 NPCM8XX_PINCFG(24, hgpio4, MFSEL2, 28, ioxh, MFSEL3, 18, smb7c, I2CSEGSEL, 28, tp_smb2, MFSEL7, 28, none, NONE, 0, SLEW), 1358 NPCM8XX_PINCFG(25, hgpio5, MFSEL2, 29, ioxh, MFSEL3, 18, smb7c, I2CSEGSEL, 28, tp_smb2, MFSEL7, 28, none, NONE, 0, SLEW), 1359 NPCM8XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1360 NPCM8XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1361 NPCM8XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1362 NPCM8XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1363 NPCM8XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1364 NPCM8XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1365 NPCM8XX_PINCFG(32, spi0cs1, MFSEL1, 3, smb14b, MFSEL7, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1366 NPCM8XX_PINCFG(33, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1367 NPCM8XX_PINCFG(34, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1368 NPCM8XX_PINCFG(37, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1369 NPCM8XX_PINCFG(38, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1370 NPCM8XX_PINCFG(39, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1371 NPCM8XX_PINCFG(40, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1372 NPCM8XX_PINCFG(41, bmcuart0a, MFSEL1, 9, cp1urxd, MFSEL6, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1373 NPCM8XX_PINCFG(42, bmcuart0a, MFSEL1, 9, cp1utxd, MFSEL6, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO), 1374 NPCM8XX_PINCFG(43, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1375 NPCM8XX_PINCFG(44, hsi1b, MFSEL1, 28, nbu1crts, MFSEL6, 15, jtag2, MFSEL4, 0, tp_jtag3, MFSEL7, 13, j2j3, MFSEL5, 2, GPO), 1376 NPCM8XX_PINCFG(45, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO), 1377 NPCM8XX_PINCFG(46, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO), 1378 NPCM8XX_PINCFG(47, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 8)), 1379 NPCM8XX_PINCFG(48, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1380 NPCM8XX_PINCFG(49, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1381 NPCM8XX_PINCFG(50, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO), 1382 NPCM8XX_PINCFG(51, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO), 1383 NPCM8XX_PINCFG(52, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1384 NPCM8XX_PINCFG(53, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1385 NPCM8XX_PINCFG(54, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1386 NPCM8XX_PINCFG(55, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1387 NPCM8XX_PINCFG(56, r1err, MFSEL1, 12, r1oen, MFSEL5, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1388 NPCM8XX_PINCFG(57, r1md, MFSEL1, 13, tpgpio4b, MFSEL5, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 1389 NPCM8XX_PINCFG(58, r1md, MFSEL1, 13, tpgpio5b, MFSEL5, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 1390 NPCM8XX_PINCFG(59, hgpio6, MFSEL2, 30, smb3d, I2CSEGSEL, 13, smb19, MFSEL5, 27, none, NONE, 0, none, NONE, 0, 0), 1391 NPCM8XX_PINCFG(60, hgpio7, MFSEL2, 31, smb3d, I2CSEGSEL, 13, smb19, MFSEL5, 27, none, NONE, 0, none, NONE, 0, 0), 1392 NPCM8XX_PINCFG(61, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1393 NPCM8XX_PINCFG(62, hsi1b, MFSEL1, 28, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, nbu1crts, MFSEL6, 15, tp_jtag3, MFSEL7, 13, GPO), 1394 NPCM8XX_PINCFG(63, hsi1a, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1395 NPCM8XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1396 NPCM8XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1397 NPCM8XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1398 NPCM8XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1399 NPCM8XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1400 NPCM8XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1401 NPCM8XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1402 NPCM8XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1403 NPCM8XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1404 NPCM8XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1405 NPCM8XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1406 NPCM8XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1407 NPCM8XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1408 NPCM8XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1409 NPCM8XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1410 NPCM8XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1411 NPCM8XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1412 NPCM8XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1413 NPCM8XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1414 NPCM8XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1415 NPCM8XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1416 NPCM8XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1417 NPCM8XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1418 NPCM8XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1419 NPCM8XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1420 NPCM8XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1421 NPCM8XX_PINCFG(90, r2err, MFSEL1, 15, r2oen, MFSEL5, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1422 NPCM8XX_PINCFG(91, r2md, MFSEL1, 16, cp1gpio6, MFSEL6, 8, tp_gpio0, MFSEL7, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 1423 NPCM8XX_PINCFG(92, r2md, MFSEL1, 16, cp1gpio7, MFSEL6, 9, tp_gpio1, MFSEL7, 1, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 1424 NPCM8XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1425 NPCM8XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1426 NPCM8XX_PINCFG(95, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1427 NPCM8XX_PINCFG(96, cp1gpio7b, MFSEL6, 24, tp_gpio7, MFSEL7, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1428 NPCM8XX_PINCFG(97, cp1gpio6b, MFSEL6, 25, tp_gpio6, MFSEL7, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1429 NPCM8XX_PINCFG(98, bu4b, MFSEL5, 13, cp1gpio5b, MFSEL6, 26, tp_gpio5, MFSEL7, 5, none, NONE, 0, none, NONE, 0, SLEW), 1430 NPCM8XX_PINCFG(99, bu4b, MFSEL5, 13, cp1gpio4b, MFSEL6, 27, tp_gpio4, MFSEL7, 4, none, NONE, 0, none, NONE, 0, SLEW), 1431 NPCM8XX_PINCFG(100, bu5b, MFSEL5, 12, cp1gpio3c, MFSEL6, 28, tp_gpio3, MFSEL7, 3, none, NONE, 0, none, NONE, 0, SLEW), 1432 NPCM8XX_PINCFG(101, bu5b, MFSEL5, 12, cp1gpio2c, MFSEL6, 29, tp_gpio2, MFSEL7, 2, none, NONE, 0, none, NONE, 0, SLEW), 1433 NPCM8XX_PINCFG(102, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1434 NPCM8XX_PINCFG(103, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1435 NPCM8XX_PINCFG(104, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1436 NPCM8XX_PINCFG(105, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1437 NPCM8XX_PINCFG(106, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1438 NPCM8XX_PINCFG(107, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1439 NPCM8XX_PINCFG(108, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1440 NPCM8XX_PINCFG(109, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1441 NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0), 1442 NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0), 1443 NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1444 NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1445 NPCM8XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1446 NPCM8XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1447 NPCM8XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1448 NPCM8XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1449 NPCM8XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1450 NPCM8XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1451 NPCM8XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1452 NPCM8XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1453 NPCM8XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1454 NPCM8XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1455 NPCM8XX_PINCFG(124, smb1c, I2CSEGSEL, 6, cp1gpio3b, MFSEL6, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1456 NPCM8XX_PINCFG(125, smb1c, I2CSEGSEL, 6, cp1gpio2b, MFSEL6, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1457 NPCM8XX_PINCFG(126, smb1b, I2CSEGSEL, 5, cp1gpio1b, MFSEL6, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1458 NPCM8XX_PINCFG(127, smb1b, I2CSEGSEL, 5, cp1gpio0b, MFSEL6, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1459 NPCM8XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1460 NPCM8XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1461 NPCM8XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1462 NPCM8XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1463 NPCM8XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1464 NPCM8XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1465 NPCM8XX_PINCFG(134, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1466 NPCM8XX_PINCFG(135, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1467 NPCM8XX_PINCFG(136, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1468 NPCM8XX_PINCFG(137, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1469 NPCM8XX_PINCFG(138, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1470 NPCM8XX_PINCFG(139, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1471 NPCM8XX_PINCFG(140, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1472 NPCM8XX_PINCFG(141, smb7b, I2CSEGSEL, 27, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1473 NPCM8XX_PINCFG(142, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1474 NPCM8XX_PINCFG(143, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1475 NPCM8XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1476 NPCM8XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1477 NPCM8XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1478 NPCM8XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1479 NPCM8XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1480 NPCM8XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1481 NPCM8XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1482 NPCM8XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1483 NPCM8XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1484 NPCM8XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1485 NPCM8XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1486 NPCM8XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1487 NPCM8XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1488 NPCM8XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1489 NPCM8XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1490 NPCM8XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1491 NPCM8XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1492 NPCM8XX_PINCFG(161, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1493 NPCM8XX_PINCFG(162, serirq, MFSEL1, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1494 NPCM8XX_PINCFG(163, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1495 NPCM8XX_PINCFG(164, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1496 NPCM8XX_PINCFG(165, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1497 NPCM8XX_PINCFG(166, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1498 NPCM8XX_PINCFG(167, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1499 NPCM8XX_PINCFG(168, lpcclk, MFSEL1, 31, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1500 NPCM8XX_PINCFG(169, scipme, MFSEL3, 0, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1501 NPCM8XX_PINCFG(170, smi, MFSEL1, 22, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1502 NPCM8XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1503 NPCM8XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1504 NPCM8XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1505 NPCM8XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1506 NPCM8XX_PINCFG(175, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1507 NPCM8XX_PINCFG(176, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1508 NPCM8XX_PINCFG(177, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1509 NPCM8XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1510 NPCM8XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1511 NPCM8XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1512 NPCM8XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1513 NPCM8XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1514 NPCM8XX_PINCFG(183, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1515 NPCM8XX_PINCFG(184, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1516 NPCM8XX_PINCFG(185, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1517 NPCM8XX_PINCFG(186, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1518 NPCM8XX_PINCFG(187, gpo187, MFSEL7, 24, smb14b, MFSEL7, 26, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, 0), 1519 NPCM8XX_PINCFG(188, gpio1889, MFSEL7, 25, spi3cs2, MFSEL4, 18, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1520 NPCM8XX_PINCFG(189, gpio1889, MFSEL7, 25, spi3cs3, MFSEL4, 19, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1521 NPCM8XX_PINCFG(190, nprd_smi, FLOCKR1, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 1522 NPCM8XX_PINCFG(191, spi1d23, MFSEL5, 3, spi1cs2, MFSEL5, 4, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DSTR(0, 2)), /* XX */ 1523 NPCM8XX_PINCFG(192, spi1d23, MFSEL5, 3, spi1cs3, MFSEL5, 5, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DSTR(0, 2)), /* XX */ 1524 NPCM8XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1525 NPCM8XX_PINCFG(194, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), 1526 NPCM8XX_PINCFG(195, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), 1527 NPCM8XX_PINCFG(196, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), 1528 NPCM8XX_PINCFG(197, smb0den, I2CSEGSEL, 22, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), 1529 NPCM8XX_PINCFG(198, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), 1530 NPCM8XX_PINCFG(199, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), 1531 NPCM8XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1532 NPCM8XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), 1533 NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), 1534 NPCM8XX_PINCFG(203, faninx, MFSEL3, 3, spi1cs0, MFSEL3, 4, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1535 NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */ 1536 NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */ 1537 NPCM8XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1538 NPCM8XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1539 NPCM8XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3rxer, MFSEL6, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1540 NPCM8XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3oen, MFSEL5, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1541 NPCM8XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1542 NPCM8XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1543 NPCM8XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1544 NPCM8XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1545 NPCM8XX_PINCFG(218, wdog1, MFSEL3, 19, smb16b, MFSEL7, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1546 NPCM8XX_PINCFG(219, wdog2, MFSEL3, 20, smb16b, MFSEL7, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1547 NPCM8XX_PINCFG(220, smb12, MFSEL3, 5, pwm8, MFSEL6, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1548 NPCM8XX_PINCFG(221, smb12, MFSEL3, 5, pwm9, MFSEL6, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1549 NPCM8XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1550 NPCM8XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1551 NPCM8XX_PINCFG(224, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1552 NPCM8XX_PINCFG(225, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1553 NPCM8XX_PINCFG(226, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW), 1554 NPCM8XX_PINCFG(227, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1555 NPCM8XX_PINCFG(228, spixcs1, MFSEL4, 28, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1556 NPCM8XX_PINCFG(229, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1557 NPCM8XX_PINCFG(230, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1558 NPCM8XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 12) | SLEW), 1559 NPCM8XX_PINCFG(233, spi1cs1, MFSEL5, 0, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEWLPC), /* slewlpc ? */ 1560 NPCM8XX_PINCFG(234, pwm10, MFSEL6, 13, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), 1561 NPCM8XX_PINCFG(235, pwm11, MFSEL6, 14, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1562 NPCM8XX_PINCFG(240, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1563 NPCM8XX_PINCFG(241, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1564 NPCM8XX_PINCFG(242, i3c1, MFSEL5, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1565 NPCM8XX_PINCFG(243, i3c1, MFSEL5, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1566 NPCM8XX_PINCFG(244, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1567 NPCM8XX_PINCFG(245, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1568 NPCM8XX_PINCFG(246, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1569 NPCM8XX_PINCFG(247, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1570 NPCM8XX_PINCFG(251, jm2, MFSEL5, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 1571 NPCM8XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */ 1572 NPCM8XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */ 1573 NPCM8XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */ 1574}; 1575 1576/* number, name, drv_data */ 1577static const struct pinctrl_pin_desc npcm8xx_pins[] = { 1578 PINCTRL_PIN(0, "GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA"), 1579 PINCTRL_PIN(1, "GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL"), 1580 PINCTRL_PIN(2, "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"), 1581 PINCTRL_PIN(3, "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL"), 1582 PINCTRL_PIN(4, "GPIO4/IOX2_DI/SMB1D_SDA"), 1583 PINCTRL_PIN(5, "GPIO5/IOX2_LD/SMB1D_SCL"), 1584 PINCTRL_PIN(6, "GPIO6/IOX2_CK/SMB2D_SDA"), 1585 PINCTRL_PIN(7, "GPIO7/IOX2_D0/SMB2D_SCL"), 1586 PINCTRL_PIN(8, "GPIO8/LKGPO1/TP_GPIO0"), 1587 PINCTRL_PIN(9, "GPIO9/LKGPO2/TP_GPIO1"), 1588 PINCTRL_PIN(10, "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"), 1589 PINCTRL_PIN(11, "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"), 1590 PINCTRL_PIN(12, "GPIO12/GSPI_CK/SMB5B_SCL"), 1591 PINCTRL_PIN(13, "GPIO13/GSPI_DO/SMB5B_SDA"), 1592 PINCTRL_PIN(14, "GPIO14/GSPI_DI/SMB5C_SCL"), 1593 PINCTRL_PIN(15, "GPIO15/GSPI_CS/SMB5C_SDA"), 1594 PINCTRL_PIN(16, "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"), 1595 PINCTRL_PIN(17, "GPIO17/PSPI_DI/CP1_GPIO5"), 1596 PINCTRL_PIN(18, "GPIO18/PSPI_D0/SMB4B_SDA"), 1597 PINCTRL_PIN(19, "GPIO19/PSPI_CK/SMB4B_SCL"), 1598 PINCTRL_PIN(20, "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"), 1599 PINCTRL_PIN(21, "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL"), 1600 PINCTRL_PIN(22, "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA"), 1601 PINCTRL_PIN(23, "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL"), 1602 PINCTRL_PIN(24, "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"), 1603 PINCTRL_PIN(25, "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"), 1604 PINCTRL_PIN(26, "GPIO26/SMB5_SDA"), 1605 PINCTRL_PIN(27, "GPIO27/SMB5_SCL"), 1606 PINCTRL_PIN(28, "GPIO28/SMB4_SDA"), 1607 PINCTRL_PIN(29, "GPIO29/SMB4_SCL"), 1608 PINCTRL_PIN(30, "GPIO30/SMB3_SDA"), 1609 PINCTRL_PIN(31, "GPIO31/SMB3_SCL"), 1610 PINCTRL_PIN(32, "GPIO32/SMB14B_SCL/SPI0_nCS1"), 1611 PINCTRL_PIN(33, "GPIO33/I3C4_SCL"), 1612 PINCTRL_PIN(34, "GPIO34/I3C4_SDA"), 1613 PINCTRL_PIN(37, "GPIO37/SMB3C_SDA/SMB23_SDA"), 1614 PINCTRL_PIN(38, "GPIO38/SMB3C_SCL/SMB23_SCL"), 1615 PINCTRL_PIN(39, "GPIO39/SMB3B_SDA/SMB22_SDA"), 1616 PINCTRL_PIN(40, "GPIO40/SMB3B_SCL/SMB22_SCL"), 1617 PINCTRL_PIN(41, "GPIO41/BU0_RXD/CP1U_RXD"), 1618 PINCTRL_PIN(42, "GPIO42/BU0_TXD/CP1U_TXD"), 1619 PINCTRL_PIN(43, "GPIO43/SI1_RXD/BU1_RXD"), 1620 PINCTRL_PIN(44, "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI"), 1621 PINCTRL_PIN(45, "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO"), 1622 PINCTRL_PIN(46, "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK"), 1623 PINCTRL_PIN(47, "GPIO47/SI1n_RI1"), 1624 PINCTRL_PIN(48, "GPIO48/SI2_TXD/BU0_TXD/STRAP5"), 1625 PINCTRL_PIN(49, "GPIO49/SI2_RXD/BU0_RXD"), 1626 PINCTRL_PIN(50, "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD"), 1627 PINCTRL_PIN(51, "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD"), 1628 PINCTRL_PIN(52, "GPIO52/SI2_nDCD/BU5_RXD"), 1629 PINCTRL_PIN(53, "GPIO53/SI2_nDTR_BOUT2/BU5_TXD"), 1630 PINCTRL_PIN(54, "GPIO54/SI2_nDSR/BU4_TXD"), 1631 PINCTRL_PIN(55, "GPIO55/SI2_RI2/BU4_RXD"), 1632 PINCTRL_PIN(56, "GPIO56/R1_RXERR/R1_OEN"), 1633 PINCTRL_PIN(57, "GPIO57/R1_MDC/TP_GPIO4"), 1634 PINCTRL_PIN(58, "GPIO58/R1_MDIO/TP_GPIO5"), 1635 PINCTRL_PIN(59, "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"), 1636 PINCTRL_PIN(60, "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"), 1637 PINCTRL_PIN(61, "GPIO61/SI1_nDTR_BOUT"), 1638 PINCTRL_PIN(62, "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"), 1639 PINCTRL_PIN(63, "GPIO63/BU1_TXD1/SI1_TXD"), 1640 PINCTRL_PIN(64, "GPIO64/FANIN0"), 1641 PINCTRL_PIN(65, "GPIO65/FANIN1"), 1642 PINCTRL_PIN(66, "GPIO66/FANIN2"), 1643 PINCTRL_PIN(67, "GPIO67/FANIN3"), 1644 PINCTRL_PIN(68, "GPIO68/FANIN4"), 1645 PINCTRL_PIN(69, "GPIO69/FANIN5"), 1646 PINCTRL_PIN(70, "GPIO70/FANIN6"), 1647 PINCTRL_PIN(71, "GPIO71/FANIN7"), 1648 PINCTRL_PIN(72, "GPIO72/FANIN8"), 1649 PINCTRL_PIN(73, "GPIO73/FANIN9"), 1650 PINCTRL_PIN(74, "GPIO74/FANIN10"), 1651 PINCTRL_PIN(75, "GPIO75/FANIN11"), 1652 PINCTRL_PIN(76, "GPIO76/FANIN12"), 1653 PINCTRL_PIN(77, "GPIO77/FANIN13"), 1654 PINCTRL_PIN(78, "GPIO78/FANIN14"), 1655 PINCTRL_PIN(79, "GPIO79/FANIN15"), 1656 PINCTRL_PIN(80, "GPIO80/PWM0"), 1657 PINCTRL_PIN(81, "GPIO81/PWM1"), 1658 PINCTRL_PIN(82, "GPIO82/PWM2"), 1659 PINCTRL_PIN(83, "GPIO83/PWM3"), 1660 PINCTRL_PIN(84, "GPIO84/R2_TXD0"), 1661 PINCTRL_PIN(85, "GPIO85/R2_TXD1"), 1662 PINCTRL_PIN(86, "GPIO86/R2_TXEN"), 1663 PINCTRL_PIN(87, "GPIO87/R2_RXD0"), 1664 PINCTRL_PIN(88, "GPIO88/R2_RXD1"), 1665 PINCTRL_PIN(89, "GPIO89/R2_CRSDV"), 1666 PINCTRL_PIN(90, "GPIO90/R2_RXERR/R2_OEN"), 1667 PINCTRL_PIN(91, "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"), 1668 PINCTRL_PIN(92, "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"), 1669 PINCTRL_PIN(93, "GPIO93/GA20/SMB5D_SCL"), 1670 PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5D_SDA"), 1671 PINCTRL_PIN(95, "GPIO95/nESPIRST/LPC_nLRESET"), 1672 PINCTRL_PIN(96, "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7"), 1673 PINCTRL_PIN(97, "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6"), 1674 PINCTRL_PIN(98, "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5"), 1675 PINCTRL_PIN(99, "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4"), 1676 PINCTRL_PIN(100, "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3"), 1677 PINCTRL_PIN(101, "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2"), 1678 PINCTRL_PIN(102, "GPIO102/HSYNC"), 1679 PINCTRL_PIN(103, "GPIO103/VSYNC"), 1680 PINCTRL_PIN(104, "GPIO104/DDC_SCL"), 1681 PINCTRL_PIN(105, "GPIO105/DDC_SDA"), 1682 PINCTRL_PIN(106, "GPIO106/I3C5_SCL"), 1683 PINCTRL_PIN(107, "GPIO107/I3C5_SDA"), 1684 PINCTRL_PIN(108, "GPIO108/SG1_MDC"), 1685 PINCTRL_PIN(109, "GPIO109/SG1_MDIO"), 1686 PINCTRL_PIN(110, "GPIO110/RG2_TXD0/DDRV0/R3_TXD0"), 1687 PINCTRL_PIN(111, "GPIO111/RG2_TXD1/DDRV1/R3_TXD1"), 1688 PINCTRL_PIN(112, "GPIO112/RG2_TXD2/DDRV2"), 1689 PINCTRL_PIN(113, "GPIO113/RG2_TXD3/DDRV3"), 1690 PINCTRL_PIN(114, "GPIO114/SMB0_SCL"), 1691 PINCTRL_PIN(115, "GPIO115/SMB0_SDA"), 1692 PINCTRL_PIN(116, "GPIO116/SMB1_SCL"), 1693 PINCTRL_PIN(117, "GPIO117/SMB1_SDA"), 1694 PINCTRL_PIN(118, "GPIO118/SMB2_SCL"), 1695 PINCTRL_PIN(119, "GPIO119/SMB2_SDA"), 1696 PINCTRL_PIN(120, "GPIO120/SMB2C_SDA"), 1697 PINCTRL_PIN(121, "GPIO121/SMB2C_SCL"), 1698 PINCTRL_PIN(122, "GPIO122/SMB2B_SDA"), 1699 PINCTRL_PIN(123, "GPIO123/SMB2B_SCL"), 1700 PINCTRL_PIN(124, "GPIO124/SMB1C_SDA/CP1_GPIO3"), 1701 PINCTRL_PIN(125, "GPIO125/SMB1C_SCL/CP1_GPIO2"), 1702 PINCTRL_PIN(126, "GPIO126/SMB1B_SDA/CP1_GPIO1"), 1703 PINCTRL_PIN(127, "GPIO127/SMB1B_SCL/CP1_GPIO0"), 1704 PINCTRL_PIN(128, "GPIO128/SMB824_SCL"), 1705 PINCTRL_PIN(129, "GPIO129/SMB824_SDA"), 1706 PINCTRL_PIN(130, "GPIO130/SMB925_SCL"), 1707 PINCTRL_PIN(131, "GPIO131/SMB925_SDA"), 1708 PINCTRL_PIN(132, "GPIO132/SMB1026_SCL"), 1709 PINCTRL_PIN(133, "GPIO133/SMB1026_SDA"), 1710 PINCTRL_PIN(134, "GPIO134/SMB11_SCL/SMB23B_SCL"), 1711 PINCTRL_PIN(135, "GPIO135/SMB11_SDA/SMB23B_SDA"), 1712 PINCTRL_PIN(136, "GPIO136/JM1_TCK"), 1713 PINCTRL_PIN(137, "GPIO137/JM1_TDO"), 1714 PINCTRL_PIN(138, "GPIO138/JM1_TMS"), 1715 PINCTRL_PIN(139, "GPIO139/JM1_TDI"), 1716 PINCTRL_PIN(140, "GPIO140/JM1_nTRST"), 1717 PINCTRL_PIN(141, "GPIO141/SMB7B_SCL"), 1718 PINCTRL_PIN(142, "GPIO142/SMB7D_SCL/TPSMB1_SCL"), 1719 PINCTRL_PIN(143, "GPIO143/SMB7D_SDA/TPSMB1_SDA"), 1720 PINCTRL_PIN(144, "GPIO144/PWM4"), 1721 PINCTRL_PIN(145, "GPIO145/PWM5"), 1722 PINCTRL_PIN(146, "GPIO146/PWM6"), 1723 PINCTRL_PIN(147, "GPIO147/PWM7"), 1724 PINCTRL_PIN(148, "GPIO148/MMC_DT4"), 1725 PINCTRL_PIN(149, "GPIO149/MMC_DT5"), 1726 PINCTRL_PIN(150, "GPIO150/MMC_DT6"), 1727 PINCTRL_PIN(151, "GPIO151/MMC_DT7"), 1728 PINCTRL_PIN(152, "GPIO152/MMC_CLK"), 1729 PINCTRL_PIN(153, "GPIO153/MMC_WP"), 1730 PINCTRL_PIN(154, "GPIO154/MMC_CMD"), 1731 PINCTRL_PIN(155, "GPIO155/MMC_nCD/MMC_nRSTLK"), 1732 PINCTRL_PIN(156, "GPIO156/MMC_DT0"), 1733 PINCTRL_PIN(157, "GPIO157/MMC_DT1"), 1734 PINCTRL_PIN(158, "GPIO158/MMC_DT2"), 1735 PINCTRL_PIN(159, "GPIO159/MMC_DT3"), 1736 PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"), 1737 PINCTRL_PIN(161, "GPIO161/ESPI_nCS/LPC_nLFRAME"), 1738 PINCTRL_PIN(162, "GPIO162/SERIRQ"), 1739 PINCTRL_PIN(163, "GPIO163/ESPI_CK/LPC_LCLK"), 1740 PINCTRL_PIN(164, "GPIO164/ESPI_IO0/LPC_LAD0"), 1741 PINCTRL_PIN(165, "GPIO165/ESPI_IO1/LPC_LAD1"), 1742 PINCTRL_PIN(166, "GPIO166/ESPI_IO2/LPC_LAD2"), 1743 PINCTRL_PIN(167, "GPIO167/ESPI_IO3/LPC_LAD3"), 1744 PINCTRL_PIN(168, "GPIO168/ESPI_nALERT/LPC_nCLKRUN"), 1745 PINCTRL_PIN(169, "GPIO169/nSCIPME/SMB21_SCL"), 1746 PINCTRL_PIN(170, "GPIO170/nSMI/SMB21_SDA"), 1747 PINCTRL_PIN(171, "GPIO171/SMB6_SCL"), 1748 PINCTRL_PIN(172, "GPIO172/SMB6_SDA"), 1749 PINCTRL_PIN(173, "GPIO173/SMB7_SCL"), 1750 PINCTRL_PIN(174, "GPIO174/SMB7_SDA"), 1751 PINCTRL_PIN(175, "GPIO175/SPI1_CK/FANIN19/FM1_CK"), 1752 PINCTRL_PIN(176, "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"), 1753 PINCTRL_PIN(177, "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"), 1754 PINCTRL_PIN(178, "GPIO178/R1_TXD0"), 1755 PINCTRL_PIN(179, "GPIO179/R1_TXD1"), 1756 PINCTRL_PIN(180, "GPIO180/R1_TXEN"), 1757 PINCTRL_PIN(181, "GPIO181/R1_RXD0"), 1758 PINCTRL_PIN(182, "GPIO182/R1_RXD1"), 1759 PINCTRL_PIN(183, "GPIO183/SPI3_SEL"), 1760 PINCTRL_PIN(184, "GPIO184/SPI3_D0/STRAP13"), 1761 PINCTRL_PIN(185, "GPIO185/SPI3_D1"), 1762 PINCTRL_PIN(186, "GPIO186/SPI3_nCS0"), 1763 PINCTRL_PIN(187, "GPO187/SPI3_nCS1_SMB14B_SDA"), 1764 PINCTRL_PIN(188, "GPIO188/SPI3_D2/SPI3_nCS2"), 1765 PINCTRL_PIN(189, "GPIO189/SPI3_D3/SPI3_nCS3"), 1766 PINCTRL_PIN(190, "GPIO190/nPRD_SMI"), 1767 PINCTRL_PIN(191, "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10"), 1768 PINCTRL_PIN(192, "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"), 1769 PINCTRL_PIN(193, "GPIO193/R1_CRSDV"), 1770 PINCTRL_PIN(194, "GPIO194/SMB0B_SCL/FM0_CK"), 1771 PINCTRL_PIN(195, "GPIO195/SMB0B_SDA/FM0_D0"), 1772 PINCTRL_PIN(196, "GPIO196/SMB0C_SCL/FM0_D1"), 1773 PINCTRL_PIN(197, "GPIO197/SMB0DEN/FM0_D3"), 1774 PINCTRL_PIN(198, "GPIO198/SMB0D_SDA/FM0_D2"), 1775 PINCTRL_PIN(199, "GPIO199/SMB0D_SCL/FM0_CSO"), 1776 PINCTRL_PIN(200, "GPIO200/R2_CK"), 1777 PINCTRL_PIN(201, "GPIO201/R1_CK"), 1778 PINCTRL_PIN(202, "GPIO202/SMB0C_SDA/FM0_CSI"), 1779 PINCTRL_PIN(203, "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"), 1780 PINCTRL_PIN(208, "GPIO208/RG2_TXC/DVCK"), 1781 PINCTRL_PIN(209, "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN"), 1782 PINCTRL_PIN(210, "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"), 1783 PINCTRL_PIN(211, "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"), 1784 PINCTRL_PIN(212, "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"), 1785 PINCTRL_PIN(213, "GPIO213/RG2_RXD3/DDRV8/R3_OEN"), 1786 PINCTRL_PIN(214, "GPIO214/RG2_RXC/DDRV9/R3_CK"), 1787 PINCTRL_PIN(215, "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV"), 1788 PINCTRL_PIN(216, "GPIO216/RG2_MDC/DDRV11"), 1789 PINCTRL_PIN(217, "GPIO217/RG2_MDIO/DVHSYNC"), 1790 PINCTRL_PIN(218, "GPIO218/nWDO1/SMB16_SCL"), 1791 PINCTRL_PIN(219, "GPIO219/nWDO2/SMB16_SDA"), 1792 PINCTRL_PIN(220, "GPIO220/SMB12_SCL/PWM8"), 1793 PINCTRL_PIN(221, "GPIO221/SMB12_SDA/PWM9"), 1794 PINCTRL_PIN(222, "GPIO222/SMB13_SCL"), 1795 PINCTRL_PIN(223, "GPIO223/SMB13_SDA"), 1796 PINCTRL_PIN(224, "GPIO224/SPIX_CK/FM2_CK"), 1797 PINCTRL_PIN(225, "GPO225/SPIX_D0/FM2_D0/STRAP1"), 1798 PINCTRL_PIN(226, "GPO226/SPIX_D1/FM2_D1/STRAP2"), 1799 PINCTRL_PIN(227, "GPIO227/SPIX_nCS0/FM2_CSI"), 1800 PINCTRL_PIN(228, "GPIO228/SPIX_nCS1/FM2_CSO"), 1801 PINCTRL_PIN(229, "GPO229/SPIX_D2/FM2_D2/STRAP3"), 1802 PINCTRL_PIN(230, "GPO230/SPIX_D3/FM2_D3/STRAP6"), 1803 PINCTRL_PIN(231, "GPIO231/EP_nCLKREQ"), 1804 PINCTRL_PIN(233, "GPIO233/SPI1_nCS1/FM1_CSO"), 1805 PINCTRL_PIN(234, "GPIO234/PWM10/SMB20_SCL"), 1806 PINCTRL_PIN(235, "GPIO235/PWM11/SMB20_SDA"), 1807 PINCTRL_PIN(240, "GPIO240/I3C0_SCL"), 1808 PINCTRL_PIN(241, "GPIO241/I3C0_SDA"), 1809 PINCTRL_PIN(242, "GPIO242/I3C1_SCL"), 1810 PINCTRL_PIN(243, "GPIO243/I3C1_SDA"), 1811 PINCTRL_PIN(244, "GPIO244/I3C2_SCL"), 1812 PINCTRL_PIN(245, "GPIO245/I3C2_SDA"), 1813 PINCTRL_PIN(246, "GPIO246/I3C3_SCL"), 1814 PINCTRL_PIN(247, "GPIO247/I3C3_SDA"), 1815 PINCTRL_PIN(250, "GPIO250/RG2_REFCK/DVVSYNC"), 1816 PINCTRL_PIN(251, "JM2/CP1_GPIO"), 1817 }; 1818 1819/* Enable mode in pin group */ 1820static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, 1821 int pin_number, int mode) 1822{ 1823 const struct npcm8xx_pincfg *cfg; 1824 int i; 1825 1826 for (i = 0 ; i < pin_number ; i++) { 1827 cfg = &pincfg[pin[i]]; 1828 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || 1829 cfg->fn2 == mode || cfg->fn3 == mode || cfg->fn4 == mode) { 1830 if (cfg->reg0) 1831 regmap_update_bits(gcr_regmap, cfg->reg0, 1832 BIT(cfg->bit0), 1833 (cfg->fn0 == mode) ? 1834 BIT(cfg->bit0) : 0); 1835 if (cfg->reg1) 1836 regmap_update_bits(gcr_regmap, cfg->reg1, 1837 BIT(cfg->bit1), 1838 (cfg->fn1 == mode) ? 1839 BIT(cfg->bit1) : 0); 1840 if (cfg->reg2) 1841 regmap_update_bits(gcr_regmap, cfg->reg2, 1842 BIT(cfg->bit2), 1843 (cfg->fn2 == mode) ? 1844 BIT(cfg->bit2) : 0); 1845 if (cfg->reg3) 1846 regmap_update_bits(gcr_regmap, cfg->reg3, 1847 BIT(cfg->bit3), 1848 (cfg->fn3 == mode) ? 1849 BIT(cfg->bit3) : 0); 1850 if (cfg->reg4) 1851 regmap_update_bits(gcr_regmap, cfg->reg4, 1852 BIT(cfg->bit4), 1853 (cfg->fn4 == mode) ? 1854 BIT(cfg->bit4) : 0); 1855 } 1856 } 1857} 1858 1859static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank, 1860 struct regmap *gcr_regmap, unsigned int pin) 1861{ 1862 int gpio = pin % bank->gc.ngpio; 1863 unsigned long pinmask = BIT(gpio); 1864 u32 val; 1865 1866 if (pincfg[pin].flag & SLEW) 1867 return ioread32(bank->base + NPCM8XX_GP_N_OSRC) & pinmask; 1868 /* LPC Slew rate in SRCNT register */ 1869 if (pincfg[pin].flag & SLEWLPC) { 1870 regmap_read(gcr_regmap, NPCM8XX_GCR_SRCNT, &val); 1871 return !!(val & SRCNT_ESPI); 1872 } 1873 1874 return -EINVAL; 1875} 1876 1877static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank, 1878 struct regmap *gcr_regmap, unsigned int pin, 1879 int arg) 1880{ 1881 void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC; 1882 int gpio = BIT(pin % bank->gc.ngpio); 1883 1884 if (pincfg[pin].flag & SLEW) { 1885 switch (arg) { 1886 case 0: 1887 npcm_gpio_clr(&bank->gc, OSRC_Offset, gpio); 1888 return 0; 1889 case 1: 1890 npcm_gpio_set(&bank->gc, OSRC_Offset, gpio); 1891 return 0; 1892 default: 1893 return -EINVAL; 1894 } 1895 } 1896 1897 if (!(pincfg[pin].flag & SLEWLPC)) 1898 return -EINVAL; 1899 1900 switch (arg) { 1901 case 0: 1902 regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT, 1903 SRCNT_ESPI, 0); 1904 break; 1905 case 1: 1906 regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT, 1907 SRCNT_ESPI, SRCNT_ESPI); 1908 break; 1909 default: 1910 return -EINVAL; 1911 } 1912 1913 return 0; 1914} 1915 1916static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev, 1917 unsigned int pin) 1918{ 1919 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1920 struct npcm8xx_gpio *bank = 1921 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 1922 int gpio = pin % bank->gc.ngpio; 1923 unsigned long pinmask = BIT(gpio); 1924 int flg, val; 1925 u32 ds = 0; 1926 1927 flg = pincfg[pin].flag; 1928 if (!(flg & DRIVE_STRENGTH_MASK)) 1929 return -EINVAL; 1930 1931 val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask; 1932 ds = val ? DSHI(flg) : DSLO(flg); 1933 dev_dbg(bank->gc.parent, "pin %d strength %d = %d\n", pin, val, ds); 1934 1935 return ds; 1936} 1937 1938static int npcm8xx_set_drive_strength(struct npcm8xx_pinctrl *npcm, 1939 unsigned int pin, int nval) 1940{ 1941 struct npcm8xx_gpio *bank = 1942 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 1943 int gpio = BIT(pin % bank->gc.ngpio); 1944 int v; 1945 1946 v = pincfg[pin].flag & DRIVE_STRENGTH_MASK; 1947 1948 if (DSLO(v) == nval) 1949 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); 1950 else if (DSHI(v) == nval) 1951 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); 1952 else 1953 return -ENOTSUPP; 1954 1955 return 0; 1956} 1957 1958/* pinctrl_ops */ 1959static int npcm8xx_get_groups_count(struct pinctrl_dev *pctldev) 1960{ 1961 return ARRAY_SIZE(npcm8xx_pingroups); 1962} 1963 1964static const char *npcm8xx_get_group_name(struct pinctrl_dev *pctldev, 1965 unsigned int selector) 1966{ 1967 return npcm8xx_pingroups[selector].name; 1968} 1969 1970static int npcm8xx_get_group_pins(struct pinctrl_dev *pctldev, 1971 unsigned int selector, 1972 const unsigned int **pins, 1973 unsigned int *npins) 1974{ 1975 *npins = npcm8xx_pingroups[selector].npins; 1976 *pins = npcm8xx_pingroups[selector].pins; 1977 1978 return 0; 1979} 1980 1981static int npcm8xx_dt_node_to_map(struct pinctrl_dev *pctldev, 1982 struct device_node *np_config, 1983 struct pinctrl_map **map, 1984 u32 *num_maps) 1985{ 1986 return pinconf_generic_dt_node_to_map(pctldev, np_config, 1987 map, num_maps, 1988 PIN_MAP_TYPE_INVALID); 1989} 1990 1991static void npcm8xx_dt_free_map(struct pinctrl_dev *pctldev, 1992 struct pinctrl_map *map, u32 num_maps) 1993{ 1994 kfree(map); 1995} 1996 1997static const struct pinctrl_ops npcm8xx_pinctrl_ops = { 1998 .get_groups_count = npcm8xx_get_groups_count, 1999 .get_group_name = npcm8xx_get_group_name, 2000 .get_group_pins = npcm8xx_get_group_pins, 2001 .dt_node_to_map = npcm8xx_dt_node_to_map, 2002 .dt_free_map = npcm8xx_dt_free_map, 2003}; 2004 2005static int npcm8xx_get_functions_count(struct pinctrl_dev *pctldev) 2006{ 2007 return ARRAY_SIZE(npcm8xx_funcs); 2008} 2009 2010static const char *npcm8xx_get_function_name(struct pinctrl_dev *pctldev, 2011 unsigned int function) 2012{ 2013 return npcm8xx_funcs[function].name; 2014} 2015 2016static int npcm8xx_get_function_groups(struct pinctrl_dev *pctldev, 2017 unsigned int function, 2018 const char * const **groups, 2019 unsigned int * const ngroups) 2020{ 2021 *ngroups = npcm8xx_funcs[function].ngroups; 2022 *groups = npcm8xx_funcs[function].groups; 2023 2024 return 0; 2025} 2026 2027static int npcm8xx_pinmux_set_mux(struct pinctrl_dev *pctldev, 2028 unsigned int function, 2029 unsigned int group) 2030{ 2031 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 2032 2033 npcm8xx_setfunc(npcm->gcr_regmap, npcm8xx_pingroups[group].pins, 2034 npcm8xx_pingroups[group].npins, group); 2035 2036 return 0; 2037} 2038 2039static int npcm8xx_gpio_request_enable(struct pinctrl_dev *pctldev, 2040 struct pinctrl_gpio_range *range, 2041 unsigned int offset) 2042{ 2043 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 2044 const unsigned int *pin = &offset; 2045 int mode = fn_gpio; 2046 2047 if (pin[0] >= 183 && pin[0] <= 189) 2048 mode = pincfg[pin[0]].fn0; 2049 2050 npcm8xx_setfunc(npcm->gcr_regmap, &offset, 1, mode); 2051 2052 return 0; 2053} 2054 2055static void npcm8xx_gpio_request_free(struct pinctrl_dev *pctldev, 2056 struct pinctrl_gpio_range *range, 2057 unsigned int offset) 2058{ 2059 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 2060 int virq; 2061 2062 virq = irq_find_mapping(npcm->domain, offset); 2063 if (virq) 2064 irq_dispose_mapping(virq); 2065} 2066 2067static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev, 2068 struct pinctrl_gpio_range *range, 2069 unsigned int offset, bool input) 2070{ 2071 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 2072 struct npcm8xx_gpio *bank = 2073 &npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK]; 2074 int gpio = BIT(offset % bank->gc.ngpio); 2075 2076 if (input) 2077 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); 2078 else 2079 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES); 2080 2081 return 0; 2082} 2083 2084static const struct pinmux_ops npcm8xx_pinmux_ops = { 2085 .get_functions_count = npcm8xx_get_functions_count, 2086 .get_function_name = npcm8xx_get_function_name, 2087 .get_function_groups = npcm8xx_get_function_groups, 2088 .set_mux = npcm8xx_pinmux_set_mux, 2089 .gpio_request_enable = npcm8xx_gpio_request_enable, 2090 .gpio_disable_free = npcm8xx_gpio_request_free, 2091 .gpio_set_direction = npcm_gpio_set_direction, 2092}; 2093 2094static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio, 2095 u32 nanosecs) 2096{ 2097 void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4); 2098 int gpio_debounce = (gpio % 16) * 2, debounce_select, i; 2099 u32 dbncp_val, dbncp_val_mod; 2100 2101 for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++) { 2102 if (bank->debounce.set_val[i]) { 2103 if (bank->debounce.nanosec_val[i] == nanosecs) { 2104 debounce_select = i << gpio_debounce; 2105 npcm_gpio_set(&bank->gc, DBNCS_offset, 2106 debounce_select); 2107 break; 2108 } 2109 } else { 2110 bank->debounce.set_val[i] = true; 2111 bank->debounce.nanosec_val[i] = nanosecs; 2112 debounce_select = i << gpio_debounce; 2113 npcm_gpio_set(&bank->gc, DBNCS_offset, debounce_select); 2114 switch (nanosecs) { 2115 case 1 ... 1040: 2116 iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); 2117 break; 2118 case 1041 ... 1640: 2119 iowrite32(0x10, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); 2120 break; 2121 case 1641 ... 2280: 2122 iowrite32(0x20, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); 2123 break; 2124 case 2281 ... 2700: 2125 iowrite32(0x30, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); 2126 break; 2127 case 2701 ... 2856: 2128 iowrite32(0x40, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); 2129 break; 2130 case 2857 ... 3496: 2131 iowrite32(0x50, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); 2132 break; 2133 case 3497 ... 4136: 2134 iowrite32(0x60, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); 2135 break; 2136 case 4137 ... 5025: 2137 iowrite32(0x70, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); 2138 break; 2139 default: 2140 dbncp_val = DIV_ROUND_CLOSEST(nanosecs, NPCM8XX_DEBOUNCE_NSEC); 2141 if (dbncp_val > NPCM8XX_DEBOUNCE_MAX_VAL) 2142 return -ENOTSUPP; 2143 dbncp_val_mod = dbncp_val & GENMASK(3, 0); 2144 if (dbncp_val_mod > GENMASK(2, 0)) 2145 dbncp_val += 0x10; 2146 iowrite32(dbncp_val & NPCM8XX_DEBOUNCE_VAL_MASK, 2147 bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); 2148 break; 2149 } 2150 break; 2151 } 2152 } 2153 2154 if (i == 4) 2155 return -ENOTSUPP; 2156 2157 return 0; 2158} 2159 2160static int npcm_set_debounce(struct npcm8xx_pinctrl *npcm, unsigned int pin, 2161 u32 nanosecs) 2162{ 2163 struct npcm8xx_gpio *bank = 2164 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 2165 int gpio = BIT(pin % bank->gc.ngpio); 2166 int ret; 2167 2168 if (nanosecs) { 2169 ret = debounce_timing_setting(bank, pin % bank->gc.ngpio, 2170 nanosecs); 2171 if (ret) 2172 dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, please use one of exist debounce values\n", pin); 2173 else 2174 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, 2175 gpio); 2176 return ret; 2177 } 2178 2179 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, gpio); 2180 2181 return 0; 2182} 2183 2184/* pinconf_ops */ 2185static int npcm8xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 2186 unsigned long *config) 2187{ 2188 enum pin_config_param param = pinconf_to_config_param(*config); 2189 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 2190 struct npcm8xx_gpio *bank = 2191 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 2192 int gpio = pin % bank->gc.ngpio; 2193 unsigned long pinmask = BIT(gpio); 2194 u32 ie, oe, pu, pd; 2195 int rc = 0; 2196 2197 switch (param) { 2198 case PIN_CONFIG_BIAS_DISABLE: 2199 case PIN_CONFIG_BIAS_PULL_UP: 2200 case PIN_CONFIG_BIAS_PULL_DOWN: 2201 pu = ioread32(bank->base + NPCM8XX_GP_N_PU) & pinmask; 2202 pd = ioread32(bank->base + NPCM8XX_GP_N_PD) & pinmask; 2203 if (param == PIN_CONFIG_BIAS_DISABLE) 2204 rc = !pu && !pd; 2205 else if (param == PIN_CONFIG_BIAS_PULL_UP) 2206 rc = pu && !pd; 2207 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 2208 rc = !pu && pd; 2209 break; 2210 case PIN_CONFIG_OUTPUT: 2211 case PIN_CONFIG_INPUT_ENABLE: 2212 ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask; 2213 oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask; 2214 if (param == PIN_CONFIG_INPUT_ENABLE) 2215 rc = (ie && !oe); 2216 else if (param == PIN_CONFIG_OUTPUT) 2217 rc = (!ie && oe); 2218 break; 2219 case PIN_CONFIG_DRIVE_PUSH_PULL: 2220 rc = !(ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask); 2221 break; 2222 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 2223 rc = ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask; 2224 break; 2225 case PIN_CONFIG_INPUT_DEBOUNCE: 2226 rc = ioread32(bank->base + NPCM8XX_GP_N_DBNC) & pinmask; 2227 break; 2228 case PIN_CONFIG_DRIVE_STRENGTH: 2229 rc = npcm8xx_get_drive_strength(pctldev, pin); 2230 if (rc) 2231 *config = pinconf_to_config_packed(param, rc); 2232 break; 2233 case PIN_CONFIG_SLEW_RATE: 2234 rc = npcm8xx_get_slew_rate(bank, npcm->gcr_regmap, pin); 2235 if (rc >= 0) 2236 *config = pinconf_to_config_packed(param, rc); 2237 break; 2238 default: 2239 return -ENOTSUPP; 2240 } 2241 2242 if (!rc) 2243 return -EINVAL; 2244 2245 return 0; 2246} 2247 2248static int npcm8xx_config_set_one(struct npcm8xx_pinctrl *npcm, 2249 unsigned int pin, unsigned long config) 2250{ 2251 enum pin_config_param param = pinconf_to_config_param(config); 2252 struct npcm8xx_gpio *bank = 2253 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 2254 u32 arg = pinconf_to_config_argument(config); 2255 int gpio = BIT(pin % bank->gc.ngpio); 2256 2257 switch (param) { 2258 case PIN_CONFIG_BIAS_DISABLE: 2259 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); 2260 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); 2261 break; 2262 case PIN_CONFIG_BIAS_PULL_DOWN: 2263 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); 2264 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); 2265 break; 2266 case PIN_CONFIG_BIAS_PULL_UP: 2267 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); 2268 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); 2269 break; 2270 case PIN_CONFIG_INPUT_ENABLE: 2271 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); 2272 bank->direction_input(&bank->gc, pin % bank->gc.ngpio); 2273 break; 2274 case PIN_CONFIG_OUTPUT: 2275 bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); 2276 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES); 2277 break; 2278 case PIN_CONFIG_DRIVE_PUSH_PULL: 2279 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); 2280 break; 2281 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 2282 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); 2283 break; 2284 case PIN_CONFIG_INPUT_DEBOUNCE: 2285 return npcm_set_debounce(npcm, pin, arg * 1000); 2286 case PIN_CONFIG_SLEW_RATE: 2287 return npcm8xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); 2288 case PIN_CONFIG_DRIVE_STRENGTH: 2289 return npcm8xx_set_drive_strength(npcm, pin, arg); 2290 default: 2291 return -ENOTSUPP; 2292 } 2293 2294 return 0; 2295} 2296 2297static int npcm8xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 2298 unsigned long *configs, unsigned int num_configs) 2299{ 2300 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 2301 int rc; 2302 2303 while (num_configs--) { 2304 rc = npcm8xx_config_set_one(npcm, pin, *configs++); 2305 if (rc) 2306 return rc; 2307 } 2308 2309 return 0; 2310} 2311 2312static const struct pinconf_ops npcm8xx_pinconf_ops = { 2313 .is_generic = true, 2314 .pin_config_get = npcm8xx_config_get, 2315 .pin_config_set = npcm8xx_config_set, 2316}; 2317 2318/* pinctrl_desc */ 2319static struct pinctrl_desc npcm8xx_pinctrl_desc = { 2320 .name = "npcm8xx-pinctrl", 2321 .pins = npcm8xx_pins, 2322 .npins = ARRAY_SIZE(npcm8xx_pins), 2323 .pctlops = &npcm8xx_pinctrl_ops, 2324 .pmxops = &npcm8xx_pinmux_ops, 2325 .confops = &npcm8xx_pinconf_ops, 2326 .owner = THIS_MODULE, 2327}; 2328 2329static int npcmgpio_add_pin_ranges(struct gpio_chip *chip) 2330{ 2331 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); 2332 2333 return gpiochip_add_pin_range(&bank->gc, dev_name(chip->parent), 2334 bank->pinctrl_id, bank->gc.base, 2335 bank->gc.ngpio); 2336} 2337 2338static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl) 2339{ 2340 struct fwnode_reference_args args; 2341 struct device *dev = pctrl->dev; 2342 struct fwnode_handle *child; 2343 int ret = -ENXIO; 2344 int id = 0, i; 2345 2346 for_each_gpiochip_node(dev, child) { 2347 pctrl->gpio_bank[id].base = fwnode_iomap(child, 0); 2348 if (!pctrl->gpio_bank[id].base) 2349 return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id); 2350 2351 ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4, 2352 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN, 2353 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT, 2354 NULL, 2355 NULL, 2356 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM, 2357 BGPIOF_READ_OUTPUT_REG_SET); 2358 if (ret) 2359 return dev_err_probe(dev, ret, "bgpio_init() failed\n"); 2360 2361 ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args); 2362 if (ret < 0) 2363 return dev_err_probe(dev, ret, "gpio-ranges fail for GPIO bank %u\n", id); 2364 2365 ret = fwnode_irq_get(child, 0); 2366 if (!ret) 2367 return dev_err_probe(dev, ret, "No IRQ for GPIO bank %u\n", id); 2368 2369 pctrl->gpio_bank[id].irq = ret; 2370 pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; 2371 pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK; 2372 pctrl->gpio_bank[id].pinctrl_id = args.args[0]; 2373 pctrl->gpio_bank[id].gc.base = -1; 2374 pctrl->gpio_bank[id].gc.ngpio = args.args[2]; 2375 pctrl->gpio_bank[id].gc.owner = THIS_MODULE; 2376 pctrl->gpio_bank[id].gc.parent = dev; 2377 pctrl->gpio_bank[id].gc.fwnode = child; 2378 pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); 2379 pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; 2380 pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input; 2381 pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input; 2382 pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output; 2383 pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output; 2384 pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request; 2385 pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; 2386 pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free; 2387 for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++) 2388 pctrl->gpio_bank[id].debounce.set_val[i] = false; 2389 pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges; 2390 id++; 2391 } 2392 2393 pctrl->bank_num = id; 2394 return ret; 2395} 2396 2397static int npcm8xx_gpio_register(struct npcm8xx_pinctrl *pctrl) 2398{ 2399 int ret, id; 2400 2401 for (id = 0 ; id < pctrl->bank_num ; id++) { 2402 struct gpio_irq_chip *girq; 2403 2404 girq = &pctrl->gpio_bank[id].gc.irq; 2405 girq->chip = &pctrl->gpio_bank[id].irq_chip; 2406 girq->parent_handler = npcmgpio_irq_handler; 2407 girq->num_parents = 1; 2408 girq->parents = devm_kcalloc(pctrl->dev, girq->num_parents, 2409 sizeof(*girq->parents), 2410 GFP_KERNEL); 2411 if (!girq->parents) 2412 return -ENOMEM; 2413 2414 girq->parents[0] = pctrl->gpio_bank[id].irq; 2415 girq->default_type = IRQ_TYPE_NONE; 2416 girq->handler = handle_level_irq; 2417 ret = devm_gpiochip_add_data(pctrl->dev, 2418 &pctrl->gpio_bank[id].gc, 2419 &pctrl->gpio_bank[id]); 2420 if (ret) 2421 return dev_err_probe(pctrl->dev, ret, "Failed to add GPIO chip %u\n", id); 2422 } 2423 2424 return 0; 2425} 2426 2427static int npcm8xx_pinctrl_probe(struct platform_device *pdev) 2428{ 2429 struct device *dev = &pdev->dev; 2430 struct npcm8xx_pinctrl *pctrl; 2431 int ret; 2432 2433 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 2434 if (!pctrl) 2435 return -ENOMEM; 2436 2437 pctrl->dev = dev; 2438 platform_set_drvdata(pdev, pctrl); 2439 2440 pctrl->gcr_regmap = 2441 syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr"); 2442 if (IS_ERR(pctrl->gcr_regmap)) 2443 return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap), 2444 "Failed to find nuvoton,sysgcr property\n"); 2445 2446 ret = npcm8xx_gpio_fw(pctrl); 2447 if (ret < 0) 2448 return dev_err_probe(dev, ret, 2449 "Failed to gpio dt-binding\n"); 2450 2451 pctrl->pctldev = devm_pinctrl_register(dev, &npcm8xx_pinctrl_desc, pctrl); 2452 if (IS_ERR(pctrl->pctldev)) 2453 return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), 2454 "Failed to register pinctrl device\n"); 2455 2456 ret = npcm8xx_gpio_register(pctrl); 2457 if (ret < 0) 2458 dev_err_probe(dev, ret, "Failed to register gpio\n"); 2459 2460 return 0; 2461} 2462 2463static const struct of_device_id npcm8xx_pinctrl_match[] = { 2464 { .compatible = "nuvoton,npcm845-pinctrl" }, 2465 { } 2466}; 2467MODULE_DEVICE_TABLE(of, npcm8xx_pinctrl_match); 2468 2469static struct platform_driver npcm8xx_pinctrl_driver = { 2470 .probe = npcm8xx_pinctrl_probe, 2471 .driver = { 2472 .name = "npcm8xx-pinctrl", 2473 .of_match_table = npcm8xx_pinctrl_match, 2474 .suppress_bind_attrs = true, 2475 }, 2476}; 2477 2478static int __init npcm8xx_pinctrl_register(void) 2479{ 2480 return platform_driver_register(&npcm8xx_pinctrl_driver); 2481} 2482arch_initcall(npcm8xx_pinctrl_register); 2483 2484MODULE_LICENSE("GPL v2"); 2485MODULE_AUTHOR("tomer.maimon@nuvoton.com"); 2486MODULE_DESCRIPTION("Nuvoton NPCM8XX Pinctrl and GPIO driver"); 2487