#
10ce59c6 |
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11-Dec-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: ingenic: Convert to use grp member Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-9-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b0f24e02 |
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11-Dec-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: ingenic: Use C99 initializers in PINCTRL_PIN_GROUP() For the better flexibility use C99 initializers in PINCTRL_PIN_GROUP(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-4-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
22c7203d |
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10-Oct-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
pinctrl: ingenic: drop the wrapper around pinctrl_gpio_direction_input() pinctrl_gpio_direction_input() now has the same signature as the wrapper around it so we can drop them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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#
b679d6c0 |
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03-Oct-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
treewide: rename pinctrl_gpio_direction_output_new() Now that pinctrl_gpio_direction_output() is no longer used, let's drop the '_new' suffix from its improved variant. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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#
315c46f9 |
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03-Oct-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
treewide: rename pinctrl_gpio_direction_input_new() Now that pinctrl_gpio_direction_input() is no longer used, let's drop the '_new' suffix from its improved variant. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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#
78329866 |
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03-Oct-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
pinctrl: ingenic: use new pinctrl GPIO helpers Replace the pinctrl helpers taking the global GPIO number as argument with the improved variants that instead take a pointer to the GPIO chip and the controller-relative offset. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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#
9b69b7d7 |
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07-Oct-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: ingenic: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Paul Cercueil <paul@crapouillou.net>
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#
17747577 |
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16-Oct-2022 |
Siarhei Volkau <lis8215@gmail.com> |
pinctrl: Ingenic: JZ4755 bug fixes Fixes UART1 function bits and MMC groups typo. For pins 0x97,0x99 function 0 is designated to PWM3/PWM5 respectively, function is 1 designated to the UART1. Diff from v1: - sent separately - added tag Fixes Cc: stable@vger.kernel.org Fixes: b582b5a434d3 ("pinctrl: Ingenic: Add pinctrl driver for JZ4755.") Tested-by: Siarhei Volkau <lis8215@gmail.com> Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Link: https://lore.kernel.org/r/20221016153548.3024209-1-lis8215@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
8c943137 |
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05-Sep-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: ingenic: Switch to use fwnode instead of of_node GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220905185102.74056-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
71f5e7b3 |
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22-Jun-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
pinctrl: ingenic: Convert to immutable irq chip Update the driver to use an immutable IRQ chip to fix this warning: "not an immutable chip, please consider fixing it!" Preserve per-chip labels by adding an ->irq_print_chip() callback. Acked-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220622185010.2022515-3-aidanmacdonald.0x0@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
4c76a7fc |
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22-Jun-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
pinctrl: ingenic: Use irqd_to_hwirq() Instead of accessing ->hwirq directly, use irqd_to_hwirq(). Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220622185010.2022515-2-aidanmacdonald.0x0@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
8d2d607c |
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12-Apr-2022 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Garbage-collect code paths for SoCs disabled by config By being a bit smarter about how the SoC version checks are performed, it is possible to have all the code paths that correspond to SoCs disabled in the kernel config automatically marked as dead code by the compiler, and therefore garbage-collected. With this patch, when compiling a kernel that only targets the JZ4760 for instance, the driver is now about 4.5 KiB smaller. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220412162218.32509-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
9279c00f |
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16-Mar-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
pinctrl: ingenic: Fix regmap on X series SoCs The X series Ingenic SoCs have a shadow GPIO group which is at a higher offset than the other groups, and is used for all GPIO configuration. The regmap did not take this offset into account and set max_register too low, so the regmap API blocked writes to the shadow group, which made the pinctrl driver unable to configure any pins. Fix this by adding regmap access tables to the chip info. The way that max_register was computed was also off by one, since max_register is an inclusive bound, not an exclusive bound; this has been fixed. Cc: stable@vger.kernel.org Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Fixes: 6626a76ef857 ("pinctrl: ingenic: Add .max_register in regmap_config") Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220317000740.1045204-1-aidanmacdonald.0x0@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
6626a76e |
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17-Jul-2021 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Add .max_register in regmap_config Compute the max register from the GPIO chip offset and number of GPIO chips. This permits to read all registers from debugfs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20210717174836.14776-3-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
7261851e |
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17-Jul-2021 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Fix bias config for X2000(E) The ingenic_set_bias() function's "bias" argument is not a "enum pin_config_param", so its value should not be compared against values of that enum. This should fix the bias config not working on the X2000(E) SoCs. Fixes: 943e0da15370 ("pinctrl: Ingenic: Add pinctrl driver for X2000.") Cc: <stable@vger.kernel.org> # v5.12 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20210717174836.14776-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
d5e93140 |
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17-Jul-2021 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Fix incorrect pull up/down info Fix the pull up/down info for both the JZ4760 and JZ4770 SoCs, as the previous values sometimes contradicted what's written in the programming manual. Fixes: b5c23aa46537 ("pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs") Cc: <stable@vger.kernel.org> # v4.12 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20210717174836.14776-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
2a18211b |
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24-Jul-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add pinctrl driver for X2100. Add support for probing the pinctrl-ingenic driver on the X2100 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1627108604-91304-5-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b638e0f1 |
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24-Jul-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760. Add SSI pins support for the JZ4755 SoC and the JZ4760 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1627108604-91304-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
28c1caaf |
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24-Jul-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Improve the code. 1.Rename the original "dmicx" ABIs to "dmic-ifx", since these devices have only one DMIC module which has multiple input interfaces. The original naming is easy to make users mistakenly think that the device has multiple dmic modules. Currently, in the mainline, no other devicetree out there is using the "sfc" ABI, so we should be able to replace it safely. 2.Rename the original "ssix-ce0" ABIs to "ssix-ce", since the X2000 have only one ce pin. The original naming is easy to make users mistakenly think that the device has multiple ce pins. Currently, in the mainline, no other devicetree out there is using the "ssix-ce0" ABIs, so we should be able to replace it safely. 3.Split the original "sfc" ABI into "sfc-data", "sfc-ce", "sfc-clk" to increase the flexibility when configuring the pins. Currently, in the mainline, no other devicetree out there is using the "sfc" ABI, so we should be able to replace it safely. 4.There is more than one compatible string in the match table, so renaming "ingenic_xxxx_of_match[]" to "ingenic_xxxx_of_matches" is more reasonable, and remove the unnecessary commas in "ingenic_gpio_of_matches[]" to reduce code size as much as possible. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1627108604-91304-2-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
a9cb09b7 |
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04-May-2021 |
Marc Zyngier <maz@kernel.org> |
pinctrl: Bulk conversion to generic_handle_domain_irq() Wherever possible, replace constructs that match either generic_handle_irq(irq_find_mapping()) or generic_handle_irq(irq_linear_revmap()) to a single call to generic_handle_domain_irq(). Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org>
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#
0ab1438b |
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05-May-2021 |
Masahiro Yamada <masahiroy@kernel.org> |
linux/kconfig.h: replace IF_ENABLED() with PTR_IF() in <linux/kernel.h> <linux/kconfig.h> is included from all the kernel-space source files, including C, assembly, linker scripts. It is intended to contain a minimal set of macros to evaluate CONFIG options. IF_ENABLED() is an intruder here because (x ? y : z) is C code, which should not be included from assembly files or linker scripts. Also, <linux/kconfig.h> is no longer self-contained because NULL is defined in <linux/stddef.h>. Move IF_ENABLED() out to <linux/kernel.h> as PTR_IF(). PTF_IF() takes the general boolean expression instead of a CONFIG option so that it fits better in <linux/kernel.h>. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org>
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#
943e0da1 |
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18-Apr-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add pinctrl driver for X2000. Add support for probing the pinctrl-ingenic driver on the X2000 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-13-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
0c990740 |
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18-Apr-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add pinctrl driver for JZ4775. Add support for probing the pinctrl-ingenic driver on the JZ4775 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-12-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b582b5a4 |
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18-Apr-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add pinctrl driver for JZ4755. Add support for probing the pinctrl-ingenic driver on the JZ4755 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-11-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
215c81a3 |
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18-Apr-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add pinctrl driver for JZ4750. Add support for probing the pinctrl-ingenic driver on the JZ4750 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-10-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
424f3969 |
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18-Apr-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add pinctrl driver for JZ4730. Add support for probing the pinctrl-ingenic driver on the JZ4730 SoC from Ingenic. This driver is derived from Paul Boddie. It is worth to noting that the JZ4730 SoC is special in having two control registers (upper/lower), so add code to handle the JZ4730 specific register offsets and some register pairs which have 2 bits for each GPIO pin. Tested-by: H. Nikolaus Schaller <hns@goldelico.com> # on Letux400 Co-developed-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-9-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
863becff |
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18-Apr-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Reformat the code. 1.Move the "INGENIC_PIN_GROUP_FUNCS" to the macro definition section. 2.Add tabs before values to align the code in the macro definition section. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-7-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
6adf2c56 |
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18-Apr-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs. 1.Add DMIC pins support for the JZ4780 SoC. 2.Add DMIC pins support for the X1000 SoC. 3.Add DMIC pins support for the X1500 SoC. 4.Add DMIC pins support for the X1830 SoC. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-6-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5e6332a7 |
|
18-Apr-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Improve LCD pins related code. 1.In the JZ4740 part, remove pointless "lcd-no-pins", use "lcd-special" and "lcd-generic" instead "lcd-18bit-tft". Currently, in the mainline, no other devicetree out there is using the "lcd-18bit-tft" ABI, so we should be able to replace it safely. 2.In the JZ4725B part, adjust the location of the LCD pins related code to keep them consistent with the style of other parts. 3.In the JZ4760 part, add the missing comma and adjust element order in "jz4760_lcd_special_pins[]", keep them in the order of CLS/SPL/PS/REV like other "lcd_special_pins" arrays. And adjust the location of the "jz4760_lcd_generic" related code to keep them consistent with the style of other parts. 4.In the JZ4770 part, remove pointless "lcd-no-pins", add the missing "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic". 5.In the X1000 part and the X1500 part, remove pointless "lcd-no-pins". 6.In the X1830 part, replace "lcd-rgb-18bit" with "lcd-tft-8bit" and "lcd-tft-24bit", because of the description of the TRANS_CONFIG.MODE register bits in the PM manual of the X1830, shows that the X1830 only supppots 24bit mode and 8bit mode for tft interface, only 18 pins in the GPIO table are because of the data[17:16], the data[9:8], and the data[1:0] has not been connected. And according to the description, the two interfaces supported by X1830 are respectively referred to as "TFT interface" and "SLCD interface", so the "lcd-rgb-xxx" is replaced with "lcd-tft-xxx" to avoid confusion. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-5-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
11015196 |
|
18-Apr-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Adjust the sequence of X1830 SSI pin groups. Adjust the sequence of X1830's SSI related codes to make it consistent with other Ingenic SoCs. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-4-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
1d0bd580 |
|
18-Apr-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add support for read the pin configuration of X1830. Add X1830 support in "ingenic_pinconf_get()", so that it can read the configuration of X1830 SoC correctly. Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl driver for X1830.") Cc: <stable@vger.kernel.org> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
65afd976 |
|
18-Apr-2021 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group. The MII group of JZ4770's MAC should have 7 pins, add missing pins to the MII group. Fixes: 5de1a73e78ed ("Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.") Cc: <stable@vger.kernel.org> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-2-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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d2cd54c2 |
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25-Feb-2021 |
Yang Li <yang.lee@linux.alibaba.com> |
pinctrl: ingenic: add missing call to of_node_put() In one of the error paths of the for_each_child_of_node() loop in ingenic_gpio_probe, add missing call to of_node_put(). Fix the following coccicheck warning: ./drivers/pinctrl/pinctrl-ingenic.c:2485:1-23: WARNING: Function "for_each_child_of_node" should have of_node_put() before return around line 2489. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1614303297-24178-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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dd1ccfd6 |
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20-Jan-2021 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Improve JZ4760 support - Add otg function and otg-vbus group. - Add lcd-8bit, lcd-16bit, lcd-18bit, lcd-generic and lcd-special groups. Change the lcd-24bit group so that it only selects the pins that aren't in the lcd-18bit and lcd-generic groups (which breaks Device Tree in theory, but there is none out there for any JZ4760 based board, yet). Remove the lcd-no-pins group which is just useless. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210120110722.20133-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9aa35178 |
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13-Dec-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Only support SoCs enabled in config Tested on a JZ4740 system (ARCH=mips make qi_lb60_defconfig), this saves about 14 KiB, by allowing the compiler to garbage-collect all the functions and tables that correspond to SoCs that were disabled in the config. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201213235447.138271-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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b4aa4876 |
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11-Dec-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Rename registers from JZ4760_GPIO_* to JZ4770_GPIO_* Now that JZ4760 support has been fixed, it looks wrong to have JZ4760_GPIO_* registers being written if the SoC is a JZ4770 or later. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201211232810.261565-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9a85c09a |
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11-Dec-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Fix JZ4760 support - JZ4760 and JZ4760B have a similar register layout as the JZ4740, and don't use the new register layout, which was introduced with the JZ4770 SoC and not the JZ4760 or JZ4760B SoCs. - The JZ4740 code path only expected two function modes to be configurable for each pin, and wouldn't work with more than two. Fix it for the JZ4760, which has four configurable function modes. Fixes: 0257595a5cf4 ("pinctrl: Ingenic: Add pinctrl driver for JZ4760 and JZ4760B.") Cc: <stable@vger.kernel.org> # 5.3 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201211232810.261565-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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016e054d |
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01-Nov-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Add lcd-8bit group for JZ4770 Add the "lcd-8bit" group to the "lcd" function. As "lcd-24bit" is a superset of "lcd-8bit", in theory the former could be modified to only contain the pins not already included in "lcd-8bit", just like how it's done for the JZ4740 and JZ4725B platforms. However, we can't do that without breaking Device Tree ABI, so in that case we have no choice but to have two groups containing the same pins. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20201101090104.5088-3-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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bb42b593 |
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01-Nov-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Get rid of repetitive data Abuse the pin function pointer to store the pin function value directly, when all the pins of a group have the same function value. Now when the pointer value is <= 3 (unsigned), the pointer value is used as the pin function; otherwise it is used as a regular pointer. This drastically reduces the number of pin function tables needed, and drops .data usage by about 2 KiB. Additionally, the few pin function tables that are still around now contain u8 instead of int, since the largest number that will be stored is 3. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20201101090104.5088-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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f83c2609 |
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10-Oct-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Fix invalid SSI pins The values for the SSI pins on GPIO chips D and E were off by 0x20. Fixes: d3ef8c6b2286 ("pinctrl: Ingenic: Add SSI pins support for JZ4770 and JZ4780.") Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reported-by: Artur Rojek <contact@artur-rojek.eu> Link: https://lore.kernel.org/r/20201010192509.9098-1-paul@crapouillou.net Reviewed-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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f4b5c348 |
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13-Sep-2020 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs. 1.Add I2S pins support for the JZ4780 SoC. 2.Add I2S pins support for the X1000 SoC. 3.Add I2S pins support for the X1500 SoC. 4.Add I2S pins support for the X1830 SoC. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200913065836.12156-4-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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d9f5dc49 |
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13-Sep-2020 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Correct the pullup and pulldown parameters of JZ4780. Correct the pullup and pulldown parameters of JZ4780 to make them consistent with the parameters on the datasheet. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200913065836.12156-3-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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d3ef8c6b |
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13-Sep-2020 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add SSI pins support for JZ4770 and JZ4780. Add SSI pins support for the JZ4770 SoC and the JZ4780 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200913065836.12156-2-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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84e7a946 |
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22-Jun-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Properly detect GPIO direction when configured for IRQ The PAT1 register contains information about the IRQ type (edge/level) for input GPIOs with IRQ enabled, and the direction for non-IRQ GPIOs. So it makes sense to read it only if the GPIO has no interrupt configured, otherwise input GPIOs configured for level IRQs are misdetected as output GPIOs. Fixes: ebd6651418b6 ("pinctrl: ingenic: Implement .get_direction for GPIO chips") Reported-by: João Henrique <johnnyonflame@hotmail.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200622214548.265417-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1c95348b |
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22-Jun-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Enhance support for IRQ_TYPE_EDGE_BOTH Ingenic SoCs don't natively support registering an interrupt for both rising and falling edges. This has to be emulated in software. Until now, this was emulated by switching back and forth between IRQ_TYPE_EDGE_RISING and IRQ_TYPE_EDGE_FALLING according to the level of the GPIO. While this worked most of the time, when used with GPIOs that need debouncing, some events would be lost. For instance, between the time a falling-edge interrupt happens and the interrupt handler configures the hardware for rising-edge, the level of the pin may have already risen, and the rising-edge event is lost. To address that issue, instead of switching back and forth between IRQ_TYPE_EDGE_RISING and IRQ_TYPE_EDGE_FALLING, we now switch back and forth between IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_LEVEL_HIGH. Since we always switch in the interrupt handler, they actually permit to detect level changes. In the example above, if the pin level rises before switching the IRQ type from IRQ_TYPE_LEVEL_LOW to IRQ_TYPE_LEVEL_HIGH, a new interrupt will raise as soon as the handler exits, and the rising-edge event will be properly detected. Fixes: e72394e2ea19 ("pinctrl: ingenic: Merge GPIO functionality") Reported-by: João Henrique <johnnyonflame@hotmail.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: João Henrique <johnnyonflame@hotmail.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200622214548.265417-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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b5fc06a1 |
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12-Jun-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Add ingenic,jz4725b-gpio compatible string Add a compatible string to support the GPIO chips on the JZ4725B SoC. There was already a compatible string for the pinctrl node, but not for the individual GPIO chip nodes. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200612120609.12730-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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bcad94d7 |
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07-Jun-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Add NAND FRE/FWE pins for JZ4740 Add the FRE/FWE pins for the JZ4740. These pins must be in function #0 for the NAND to work. The reason it worked before was because the bootloader did set these pins to the correct function beforehand. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200607174243.2361664-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9a0f1341 |
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03-May-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Add irq_{request,release}_resources callbacks These are called when a GPIO is to be used as IRQ. Without these custom callbacks, when an interrupt is requested directly and not through gpiod_to_irq(), the request fails because the GPIO is not necesarily in input mode. These callbacks simply enforce that the requested GPIO is in input mode. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200503164549.163884-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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d6471d6e |
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01-Apr-2020 |
Thierry Reding <treding@nvidia.com> |
pinctrl: Unconditionally assign .request()/.free() The gpiochip_generic_request() and gpiochip_generic_free() functions can now deal properly with chips that don't have any pin-ranges defined, so they can be assigned unconditionally. Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200401200527.2982450-2-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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a0bb89e8 |
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28-Feb-2020 |
Paul Boddie <paul@boddie.org.uk> |
pinctrl: ingenic: add hdmi-ddc pin control group Signed-off-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/r/010d6ad3473fb4b1f1041888a071796180cdd838.1582913973.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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d6d43a92 |
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20-Feb-2020 |
Josh Poimboeuf <jpoimboe@redhat.com> |
pinctrl: ingenic: Improve unreachable code generation In the second loop of ingenic_pinconf_set(), it annotates the switch default case as unreachable(). The annotation is technically correct, because that same case would have resulted in an early function return in the previous loop. However, the compiled code is suboptimal. GCC seems to work extra hard to ensure that the unreachable code path triggers undefined behavior. The function would fall through to start executing whatever function happens to be next in the compilation unit. This is problematic because: a) it adds unnecessary 'ensure undefined behavior' logic, and corresponding i-cache footprint; and b) it's less robust -- if a bug were to be introduced, falling through to the next function would be catastrophic. Yet another issue is that, while objtool normally understands unreachable() annotations, there's one special case where it doesn't: when the annotation occurs immediately after a 'ret' instruction. That happens to be the case here because unreachable() is immediately before the return. Remove the unreachable() annotation and replace it with a comment. This simplifies the code generation and changes the unreachable error path to just silently return instead of corrupting execution. This fixes the following objtool warning: drivers/pinctrl/pinctrl-ingenic.o: warning: objtool: ingenic_pinconf_set() falls through to next function ingenic_pinconf_group_set() Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lore.kernel.org/r/bc20fdbcb826512cf76b7dfd0972740875931b19.1582212881.git.jpoimboe@redhat.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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b2954743 |
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16-Feb-2020 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add missing parts for X1830. Add lcd pinctrl driver for X1830. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1581851828-3493-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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3c827873 |
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14-Feb-2020 |
Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> |
pinctrl: Use new GPIO_LINE_DIRECTION Use newly added GPIO defines GPIO_LINE_DIRECTION_IN and GPIO_LINE_DIRECTION_OUT instead of using hard-coded 1 and 0. Main benefit is to make it easier to see which values mean IN and which OUT. As a side effect this helps GPIO framework to change the direction defines to something else if ever needed. Please note that return value from get_direction call on pinctrl-axp209 driver was changed. Previously pinctrl-axp209 might have returned value 2 for direction INPUT. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Reported-by: kbuild test robot <lkp@intel.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20200214135712.GA14557@localhost.localdomain Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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94f7a2cb |
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06-Jan-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Use devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() instead of platform_get_resource + devm_ioremap_resource. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200106232711.559727-6-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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f831f93a |
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06-Jan-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Factorize irq_set_type function Simplify the code of the driver's irq_set_type() function by doing some factorization. The behaviour is unchanged. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200106232711.559727-5-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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5ffdbb7e |
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06-Jan-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Remove duplicated ingenic_chip_info structures Until there is the need to handle the JZ4760B and X1000E differently there is no reason to use a separate ingenic_chip_info since the data it contains is the same than for the JZ4760 and X1000 respectively. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200106232711.559727-4-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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baf15647 |
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06-Jan-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Put ingenic_chip_info pointer in match data Instead of passing a numeric ID as match data, and retrieve a pointer to the ingenic_chip_info structure in an ugly succession of if/else in the probe function, get the pointer to the ingenic_chip_info structure directly from the match data, and store the numeric ID inside the ingenic_chip_info structure. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200106232711.559727-3-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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5ec008bf |
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06-Jan-2020 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Remove platform ID table We enforce devicetree support in the Kconfig and all Ingenic boards without exception probe their drivers from devicetree. The code path to probe the driver from arch code can then be considered as dead code and removed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200106232711.559727-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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d7da2a1e |
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15-Dec-2019 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add pinctrl driver for X1830. Add support for probing the pinctrl-ingenic driver on the X1830 Soc from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1576426864-35348-7-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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f742e5eb |
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15-Dec-2019 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Introduce reg_offset and use it instead hard code. Introduce "reg_offset", use it instead hard code "0x100", it will also be used for subsequent X1830 pinctrl driver. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1576426864-35348-5-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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3b31e9b0 |
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15-Dec-2019 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Add missing parts for X1000 and X1500. 1.Add pinctrl drivers for the SPI flash controller (SFC) of X1000 and X1500. 2.Add pinctrl driver for the synchronous serial interface (SSI) of X1000. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1576426864-35348-4-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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b4a9372a |
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15-Dec-2019 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
pinctrl: Ingenic: Fix bugs in X1000 and X1500. 1.Fix the pullup parameter of X1000. 2.X1000 and X1500 have only one set of uart1 hwflow pin mapping, so modify "uart1_hwflow_d" to "uart1_hwflow". 3.X1000 has only one set of mmc1 pin mapping, so modify "mmc1-1bit-e/mmc1-4bit-e" to "mmc1-1bit/mmc1-4bit". 4.X1000 has only one regular externel memory controller that does not support nand flash, so change "nemc_" to "emc_". 5.X1500 has only one set of mmc, so modify "mmc0_" to "mmc_". Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1576426864-35348-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9e65527a |
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10-Dec-2019 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Fixup PIN_CONFIG_OUTPUT config JZ4760 support was added in parallel of the previous patch so this one slipped through. The first SoC to use the new register is the JZ4760 and not the JZ4770, fix it here. Fixes: 7009d046a601 ("pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT config") Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20191210164446.53912-1-paul@crapouillou.net [Folded into OF dependency] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ae75b53e |
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19-Nov-2019 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Add OTG VBUS pin for the JZ4770 Add pin mux configuration for the OTG VBUS pin of the JZ4770. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20191119155211.102527-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
7009d046 |
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19-Nov-2019 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT config This makes the driver support the 'output-low' and 'output-high' devicetree properties in gpio-hog sub-nodes. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20191119155211.102527-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
142b8767 |
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01-Oct-2019 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: ingenic: Pass irqchip when adding gpiochip We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Thierry Reding <thierry.reding@gmail.com> Acked-by: Zhou Yanjie <zhouyanjie@zoho.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191001133209.17164-1-linus.walleij@linaro.org
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#
5d21595b |
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13-Jul-2019 |
Zhou Yanjie <zhouyanjie@zoho.com> |
pinctrl: Ingenic: Add pinctrl driver for X1500. Add support for probing the pinctrl-ingenic driver on the X1500 Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lore.kernel.org/r/1563076436-5338-7-git-send-email-zhouyanjie@zoho.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
fe1ad5ee |
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13-Jul-2019 |
Zhou Yanjie <zhouyanjie@zoho.com> |
pinctrl: Ingenic: Add pinctrl driver for X1000 and X1000E. Add support for probing the pinctrl-ingenic driver on the X1000 Soc and the X1000E Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lore.kernel.org/r/1563076436-5338-5-git-send-email-zhouyanjie@zoho.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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0257595a |
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13-Jul-2019 |
Zhou Yanjie <zhouyanjie@zoho.com> |
pinctrl: Ingenic: Add pinctrl driver for JZ4760 and JZ4760B. Add support for probing the pinctrl-ingenic driver on the JZ4760 Soc and the JZ4760B Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lore.kernel.org/r/1563076436-5338-3-git-send-email-zhouyanjie@zoho.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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af873fce |
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28-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194 Based on 1 normalized pattern(s): license terms gnu general public license gpl version 2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170027.447718015@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
a3240f09 |
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07-Feb-2019 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Add LCD pins for the JZ4725B SoC Add the pins and groups for the "lcd" pin function in the JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b71c1844 |
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28-Jan-2019 |
Zhou Yanjie <zhouyanjie@cduestc.edu.cn> |
Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_". In the original code, some function names begin with "ingenic_gpio_", and some with "gpio_ingenic_". For the sake of uniform style, all of them are changed to the beginning of "ingenic_gpio_". Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5de1a73e |
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28-Jan-2019 |
Zhou Yanjie <zhouyanjie@cduestc.edu.cn> |
Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780. Add mmc2 for JZ4770 and JZ4780: According to the datasheet, both JZ4770 and JZ4780 have mmc2. But this part of the original code is missing. It is worth noting that JZ4770's mmc2 supports 8bit mode while JZ4780's does not, so we added the corresponding code for both models. Add nemc-wait for JZ4770 and JZ4780: Both JZ4770 and JZ4780 have a nemc-wait pin. But this part of the original code is missing. Add mac for JZ4770: JZ4770 have a mac. But this part of the original code is missing. Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
ff656e47 |
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28-Jan-2019 |
Zhou Yanjie <zhouyanjie@cduestc.edu.cn> |
Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780. Delete uart4 and i2c3/4 from JZ4770: According to the datasheet, only JZ4780 have uart4 and i2c3/4. So we remove it from the JZ4770 code and add a section corresponding the JZ4780. Fix bugs in i2c0/1: The pin number was wrong in the original code. Fix bugs in uart2: JZ4770 and JZ4780 have different uart2 pins. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in mmc0: JZ4770 and JZ4780 assigned different pins to mmc0's 4~7 data lines. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in mmc1: JZ4770's mmc1 has 8bit mode, while JZ4780 doesn't. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in nemc: JZ4770's nemc has 16bit mode, while JZ4780 doesn't. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. And add missing cs2~5 groups for JZ4770 and JZ4780. Fix bugs in cim: JZ4770's cim has 12bit mode, while JZ4780 doesn't. So the original section JZ4770 has been modified and the corresponding section of JZ4780 has been added. Fix bugs in lcd: Both JZ4770 and JZ4780 lcd should be 24bit instead of 32bit. Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
823dd71f |
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25-Aug-2018 |
Paul Burton <paulburton@kernel.org> |
pinctrl: ingenic: Fix group & function error checking Commit a203728ac6bb ("pinctrl: core: Return selector to the pinctrl driver") and commit f913cfce4ee4 ("pinctrl: pinmux: Return selector to the pinctrl driver") modified the return values of pinctrl_generic_add_group() and pinmux_generic_add_function() respectively, but did so without updating their callers. This broke the pinctrl-ingenic driver, which treats non-zero return values from these functions as errors & fails to probe. For example on a MIPS Ci20: pinctrl-ingenic 10010000.pin-controller: Failed to register group uart0-hwflow pinctrl-ingenic: probe of 10010000.pin-controller failed with error 1 Without the pinctrl driver probed, other drivers go on to fail to probe too & the system is unusable. Fix this by modifying the error checks to treat only negative values as errors, matching the commits that introduced the breakage & similar changes made to other drivers. Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: a203728ac6bb ("pinctrl: core: Return selector to the pinctrl driver") Fixes: f913cfce4ee4 ("pinctrl: pinmux: Return selector to the pinctrl driver") Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Tony Lindgren <tony@atomide.com> Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
28d6eeb4 |
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29-Aug-2018 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: ingenic: Include the right header This is a GPIO driver so only include <linux/gpio/driver.h> Cc: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f2a96765 |
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21-Aug-2018 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Add support for the JZ4725B Add support for the JZ4725B and compatible SoCs from Ingenic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
ebd66514 |
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21-Aug-2018 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Implement .get_direction for GPIO chips This allows to read from debugfs whether the GPIOs requested are set as input or output. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e72394e2 |
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21-Aug-2018 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Merge GPIO functionality Merge the code of the gpio-ingenic driver into the pinctrl-ingenic driver. The reason behind this, is that the same hardware block handles both pin config / muxing and GPIO. ingenic_gpio_probe() have been marked as __init, but for the most part, the code is the exact same as what it was in the gpio-ingenic driver. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
4717b11f |
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21-Aug-2018 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Mark probe function as __init By using platform_driver_probe() instead of platform_driver_register(), we can mark the ingenic_pinctrl_probe() function as __init. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
556a36a7 |
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21-Aug-2018 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Probe driver at subsys_initcall Using postcore_initcall() makes the driver try to initialize way too early. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
0084a786 |
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27-Jun-2018 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: ingenic: Fix inverted direction for < JZ4770 The .gpio_set_direction() callback was setting inverted direction for SoCs older than the JZ4770, this restores the correct behaviour. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
a86854d0 |
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12-Jun-2018 |
Kees Cook <keescook@chromium.org> |
treewide: devm_kzalloc() -> devm_kcalloc() The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc(). This patch replaces cases of: devm_kzalloc(handle, a * b, gfp) with: devm_kcalloc(handle, a * b, gfp) as well as handling cases of: devm_kzalloc(handle, a * b * c, gfp) with: devm_kzalloc(handle, array3_size(a, b, c), gfp) as it's slightly less ugly than: devm_kcalloc(handle, array_size(a, b), c, gfp) This does, however, attempt to ignore constant size factors like: devm_kzalloc(handle, 4 * 1024, gfp) though any constants defined via macros get caught up in the conversion. Any factors with a sizeof() of "unsigned char", "char", and "u8" were dropped, since they're redundant. Some manual whitespace fixes were needed in this patch, as Coccinelle really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...". The Coccinelle script used for this was: // Fix redundant parens around sizeof(). @@ expression HANDLE; type TYPE; expression THING, E; @@ ( devm_kzalloc(HANDLE, - (sizeof(TYPE)) * E + sizeof(TYPE) * E , ...) | devm_kzalloc(HANDLE, - (sizeof(THING)) * E + sizeof(THING) * E , ...) ) // Drop single-byte sizes and redundant parens. @@ expression HANDLE; expression COUNT; typedef u8; typedef __u8; @@ ( devm_kzalloc(HANDLE, - sizeof(u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * COUNT + COUNT , ...) ) // 2-factor product with sizeof(type/expression) and identifier or constant. @@ expression HANDLE; type TYPE; expression THING; identifier COUNT_ID; constant COUNT_CONST; @@ ( - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_ID) + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_ID + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_CONST) + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_CONST + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_ID) + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_ID + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_CONST) + COUNT_CONST, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_CONST + COUNT_CONST, sizeof(THING) , ...) ) // 2-factor product, only identifiers. @@ expression HANDLE; identifier SIZE, COUNT; @@ - devm_kzalloc + devm_kcalloc (HANDLE, - SIZE * COUNT + COUNT, SIZE , ...) // 3-factor product with 1 sizeof(type) or sizeof(expression), with // redundant parens removed. @@ expression HANDLE; expression THING; identifier STRIDE, COUNT; type TYPE; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) ) // 3-factor product with 2 sizeof(variable), with redundant parens removed. @@ expression HANDLE; expression THING1, THING2; identifier COUNT; type TYPE1, TYPE2; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(TYPE2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) ) // 3-factor product, only identifiers, with redundant parens removed. @@ expression HANDLE; identifier STRIDE, SIZE, COUNT; @@ ( devm_kzalloc(HANDLE, - (COUNT) * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) ) // Any remaining multi-factor products, first at least 3-factor products, // when they're not all constants... @@ expression HANDLE; expression E1, E2, E3; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, - (E1) * E2 * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * (E3) + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - E1 * E2 * E3 + array3_size(E1, E2, E3) , ...) ) // And then all remaining 2 factors products when they're not all constants, // keeping sizeof() as the second factor argument. @@ expression HANDLE; expression THING, E1, E2; type TYPE; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, sizeof(THING) * C2, ...) | devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...) | devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, C1 * C2, ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (E2) + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * E2 + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (E2) + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * E2 + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * E2 + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * (E2) + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - E1 * E2 + E1, E2 , ...) ) Signed-off-by: Kees Cook <keescook@chromium.org>
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#
119fcf47 |
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17-Jan-2018 |
Wei Yongjun <weiyongjun1@huawei.com> |
pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe() There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
161ef8b3 |
|
05-Oct-2017 |
Colin Ian King <colin.king@canonical.com> |
pinctrl: ingenic: make function ingenic_pinctrl_probe static The function ingenic_pinctrl_probe is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warnings symbol 'ingenic_pinctrl_probe' was not declared. Should it be static? Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5bf7b849 |
|
09-Aug-2017 |
Julia Lawall <Julia.Lawall@lip6.fr> |
pinctrl: ingenic: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e7f4c4bf |
|
13-Jun-2017 |
Dan Carpenter <dan.carpenter@oracle.com> |
pinctrl: ingenic: checking for NULL instead of IS_ERR() devm_pinctrl_register() returns error pointers, it doesn't return NULL. Fixes: b5c23aa46537 ("pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b5c23aa4 |
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12-May-2017 |
Paul Cercueil <paul@crapouillou.net> |
pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs This driver handles pin configuration and pin muxing for the JZ4740 and JZ4780 SoCs from Ingenic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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