Searched refs:intr (Results 151 - 175 of 528) sorted by relevance

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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Dbase.c94 i2c->func->aux_mask(i2c, type, aux->intr, 0);
103 i2c->func->aux_mask(i2c, type, aux->intr, aux->intr);
128 if (hi & aux->intr) mask |= NVKM_I2C_PLUG;
129 if (lo & aux->intr) mask |= NVKM_I2C_UNPLUG;
130 if (rq & aux->intr) mask |= NVKM_I2C_IRQ;
131 if (tx & aux->intr) mask |= NVKM_I2C_DONE;
242 .intr = nvkm_i2c_intr,
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/top/
H A Dgk104.c62 info->intr = (data & 0x000f8000) >> 15;
100 "engine %2d runlist %2d intr %2d "
104 info->intr, info->reset);
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/engine/
H A Dfalcon.h73 int (*bind_stat)(struct nvkm_falcon *, bool intr);
103 void (*intr)(struct nvkm_falcon *, struct nvkm_chan *); member in struct:nvkm_falcon_func
/linux-master/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_devlink.c62 u64 intr; local
70 intr = rvu_read64(rvu, blkaddr, NIX_AF_RVU_INT);
71 nix_event_context->nix_af_rvu_int = intr;
74 rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT, intr);
97 u64 intr; local
105 intr = rvu_read64(rvu, blkaddr, NIX_AF_GEN_INT);
106 nix_event_context->nix_af_rvu_gen = intr;
109 rvu_write64(rvu, blkaddr, NIX_AF_GEN_INT, intr);
132 u64 intr; local
140 intr
167 u64 intr; local
609 u64 intr; local
644 u64 intr; local
679 u64 intr; local
713 u64 intr; local
[all...]
/linux-master/drivers/gpu/drm/vmwgfx/
H A Dttm_object.h311 static inline int ttm_bo_wait(struct ttm_buffer_object *bo, bool intr, argument
314 struct ttm_operation_ctx ctx = { intr, no_wait };
/linux-master/drivers/scsi/bfa/
H A Dbfa_core.c765 u32 intr, qintr; local
768 intr = readl(bfa->iocfc.bfa_regs.intr_status);
769 if (!intr)
775 qintr = intr & __HFN_INT_RME_MASK;
781 intr &= ~qintr;
782 if (!intr)
788 qintr = intr & __HFN_INT_CPE_MASK;
793 intr &= ~qintr;
794 if (!intr)
797 bfa_msix_lpu_err(bfa, intr);
803 u32 intr, qintr; local
908 u32 intr, curr_value; local
[all...]
/linux-master/drivers/net/vmxnet3/
H A Dvmxnet3_drv.c53 * Enable/Disable the given intr
77 for (i = 0; i < adapter->intr.num_intrs; i++)
103 for (i = 0; i < adapter->intr.num_intrs; i++)
2286 * Returns whether or not the intr is handled
2295 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2316 * intr is handled
2325 /* disable intr if needed */
2326 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2338 * vmxnet3 msix event intr handler
2341 * whether or not the intr i
2420 struct vmxnet3_intr *intr = &adapter->intr; local
2541 struct vmxnet3_intr *intr = &adapter->intr; local
[all...]
/linux-master/drivers/crypto/cavium/cpt/
H A Dcptpf_mbox.c148 u64 intr; local
151 intr = cpt_read_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0));
152 dev_dbg(&cpt->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr);
154 if (intr & (1ULL << vf)) {
/linux-master/drivers/net/wireless/ti/wl18xx/
H A Dwl18xx.h123 __le32 intr; member in struct:wl18xx_fw_status
/linux-master/drivers/net/wireless/ti/wl12xx/
H A Dwl12xx.h117 __le32 intr; member in struct:wl12xx_fw_status
/linux-master/arch/x86/events/intel/
H A Dpt.h30 u64 intr : 1; member in struct:topa_entry
/linux-master/drivers/crypto/marvell/octeontx/
H A Dotx_cptpf_mbox.c242 u64 intr; local
245 intr = readq(cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0));
246 pr_debug("PF interrupt mbox%d mask 0x%llx\n", mbx, intr);
248 if (intr & (1ULL << vf)) {
/linux-master/arch/sparc/kernel/
H A Dprom_32.c140 unsigned int *intr; local
159 intr = &interrupt; /* IRQ0 does not exist */
161 intr = prop->value;
163 sprintf(tmp_buf, "%s@%x,%x", name, *intr, reg0);
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/privring/
H A Dgk20a.c77 .intr = gk20a_privring_intr,
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/timer/
H A Dnv40.c77 .intr = nv04_timer_intr,
H A Dnv41.c74 .intr = nv04_timer_intr,
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
H A Dnv04.c51 nvkm_error(subdev, "intr %08x\n", stat);
67 .intr = nv04_bus_intr,
H A Dnv31.c65 nvkm_error(subdev, "intr %08x\n", stat);
81 .intr = nv31_bus_intr,
/linux-master/drivers/iio/accel/
H A Dbmc150-accel.h41 int intr; member in struct:bmc150_accel_trigger
/linux-master/arch/arm/mach-pxa/
H A Dpxa27x-udc.h43 #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
52 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dg98.c54 .intr = nv04_fifo_intr,
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
H A Dgf100.c70 .intr = &gt215_mc_intr,
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dintr.h59 struct nvkm_intr *intr; member in struct:nvkm_inth
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgt215.c70 .intr = gt215_ce_intr,
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dmcp77.c49 .intr = nv50_disp_intr,

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