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06db7fde |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/fifo: add new channel classes Exposes a bunch of the new features that became possible as a result of the earlier commits. DRM will build on this in the future to add support for features such as SCG ("async compute") and multi-device rendering, as part of the work necessary to be able to write a half- decent vulkan driver - finally. For the moment, this just crudely ports DRM to the API changes. - channel class interfaces now the same for all HW classes - channel group class exposed (SCG) - channel runqueue selector exposed (SCG) - channel sub-device id control exposed (multi-device rendering) - channel names in logging will reflect creating process, not fd owner - explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer - drm is smarter about determining the appropriate channel class to use Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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8ab849d6 |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/fifo: add new engine context handling Builds on the context tracking that was added earlier. - marks engine context PTEs as 'priv' where possible Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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b084fff2 |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/fifo: add common runlist control - less dependence on waiting for runlist updates, on GPUs that allow it - supports runqueue selector in RAMRL entries - completes switch to common runl/cgrp/chan topology info Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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d67f3b96 |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/fifo: tidy up non-stall intr handling - removes a layer of indirection in the intr handling - prevents non-stall ctrl racing with unknown intrs Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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0fc72ee9 |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/fifo: use runlist engine info to lookup engine classes Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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d94470e9 |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/fifo: add common runlist/engine topology Creates an nvkm_runl for each runlist on the GPU, and an nvkm_engn for each engine that is reachable from a runlist. - basically what gk104- already does, but extended to all chips - adds per-runlist CHID allocators (Ampere) - splits g98/gt2xx out from g84 (different target engines) Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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