1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25
26static const struct nvkm_mc_map
27gf100_mc_reset[] = {
28	{ 0x00020000, NVKM_ENGINE_MSPDEC },
29	{ 0x00008000, NVKM_ENGINE_MSVLD },
30	{ 0x00002000, NVKM_SUBDEV_PMU, 0, true },
31	{ 0x00001000, NVKM_ENGINE_GR },
32	{ 0x00000100, NVKM_ENGINE_FIFO },
33	{ 0x00000080, NVKM_ENGINE_CE, 1 },
34	{ 0x00000040, NVKM_ENGINE_CE, 0 },
35	{ 0x00000002, NVKM_ENGINE_MSPPP },
36	{}
37};
38
39static const struct nvkm_intr_data
40gf100_mc_intrs[] = {
41	{ NVKM_ENGINE_DISP    , 0, 0, 0x04000000, true },
42	{ NVKM_ENGINE_MSPDEC  , 0, 0, 0x00020000, true },
43	{ NVKM_ENGINE_MSVLD   , 0, 0, 0x00008000, true },
44	{ NVKM_ENGINE_GR      , 0, 0, 0x00001000 },
45	{ NVKM_ENGINE_FIFO    , 0, 0, 0x00000100 },
46	{ NVKM_ENGINE_CE      , 1, 0, 0x00000040, true },
47	{ NVKM_ENGINE_CE      , 0, 0, 0x00000020, true },
48	{ NVKM_ENGINE_MSPPP   , 0, 0, 0x00000001, true },
49	{ NVKM_SUBDEV_PRIVRING, 0, 0, 0x40000000, true },
50	{ NVKM_SUBDEV_BUS     , 0, 0, 0x10000000, true },
51	{ NVKM_SUBDEV_FB      , 0, 0, 0x08002000, true },
52	{ NVKM_SUBDEV_LTC     , 0, 0, 0x02000000, true },
53	{ NVKM_SUBDEV_PMU     , 0, 0, 0x01000000, true },
54	{ NVKM_SUBDEV_GPIO    , 0, 0, 0x00200000, true },
55	{ NVKM_SUBDEV_I2C     , 0, 0, 0x00200000, true },
56	{ NVKM_SUBDEV_TIMER   , 0, 0, 0x00100000, true },
57	{ NVKM_SUBDEV_THERM   , 0, 0, 0x00040000, true },
58	{},
59};
60
61void
62gf100_mc_unk260(struct nvkm_mc *mc, u32 data)
63{
64	nvkm_wr32(mc->subdev.device, 0x000260, data);
65}
66
67static const struct nvkm_mc_func
68gf100_mc = {
69	.init = nv50_mc_init,
70	.intr = &gt215_mc_intr,
71	.intrs = gf100_mc_intrs,
72	.intr_nonstall = true,
73	.reset = gf100_mc_reset,
74	.device = &nv04_mc_device,
75	.unk260 = gf100_mc_unk260,
76};
77
78int
79gf100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
80{
81	return nvkm_mc_new_(&gf100_mc, device, type, inst, pmc);
82}
83