1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * This file is part of wl12xx
4 *
5 * Copyright (C) 2011 Texas Instruments Inc.
6 */
7
8#ifndef __WL12XX_PRIV_H__
9#define __WL12XX_PRIV_H__
10
11#include "conf.h"
12
13/* WiLink 6/7 chip IDs */
14#define CHIP_ID_127X_PG10              (0x04030101)
15#define CHIP_ID_127X_PG20              (0x04030111)
16#define CHIP_ID_128X_PG10              (0x05030101)
17#define CHIP_ID_128X_PG20              (0x05030111)
18
19/* FW chip version for wl127x */
20#define WL127X_CHIP_VER		6
21/* minimum single-role FW version for wl127x */
22#define WL127X_IFTYPE_SR_VER	3
23#define WL127X_MAJOR_SR_VER	10
24#define WL127X_SUBTYPE_SR_VER	WLCORE_FW_VER_IGNORE
25#define WL127X_MINOR_SR_VER	133
26/* minimum multi-role FW version for wl127x */
27#define WL127X_IFTYPE_MR_VER	5
28#define WL127X_MAJOR_MR_VER	7
29#define WL127X_SUBTYPE_MR_VER	WLCORE_FW_VER_IGNORE
30#define WL127X_MINOR_MR_VER	42
31
32/* FW chip version for wl128x */
33#define WL128X_CHIP_VER		7
34/* minimum single-role FW version for wl128x */
35#define WL128X_IFTYPE_SR_VER	3
36#define WL128X_MAJOR_SR_VER	10
37#define WL128X_SUBTYPE_SR_VER	WLCORE_FW_VER_IGNORE
38#define WL128X_MINOR_SR_VER	133
39/* minimum multi-role FW version for wl128x */
40#define WL128X_IFTYPE_MR_VER	5
41#define WL128X_MAJOR_MR_VER	7
42#define WL128X_SUBTYPE_MR_VER	WLCORE_FW_VER_IGNORE
43#define WL128X_MINOR_MR_VER	42
44
45#define WL12XX_AGGR_BUFFER_SIZE	(4 * PAGE_SIZE)
46
47#define WL12XX_NUM_TX_DESCRIPTORS 16
48#define WL12XX_NUM_RX_DESCRIPTORS 8
49
50#define WL12XX_NUM_MAC_ADDRESSES 2
51
52#define WL12XX_RX_BA_MAX_SESSIONS 3
53
54#define WL12XX_MAX_AP_STATIONS 8
55#define WL12XX_MAX_LINKS 12
56
57struct wl127x_rx_mem_pool_addr {
58	u32 addr;
59	u32 addr_extra;
60};
61
62struct wl12xx_priv {
63	struct wl12xx_priv_conf conf;
64
65	int ref_clock;
66	int tcxo_clock;
67
68	struct wl127x_rx_mem_pool_addr *rx_mem_addr;
69};
70
71/* Reference clock values */
72enum {
73	WL12XX_REFCLOCK_19	= 0, /* 19.2 MHz */
74	WL12XX_REFCLOCK_26	= 1, /* 26 MHz */
75	WL12XX_REFCLOCK_38	= 2, /* 38.4 MHz */
76	WL12XX_REFCLOCK_52	= 3, /* 52 MHz */
77	WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
78	WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
79};
80
81/* TCXO clock values */
82enum {
83	WL12XX_TCXOCLOCK_19_2	= 0, /* 19.2MHz */
84	WL12XX_TCXOCLOCK_26	= 1, /* 26 MHz */
85	WL12XX_TCXOCLOCK_38_4	= 2, /* 38.4MHz */
86	WL12XX_TCXOCLOCK_52	= 3, /* 52 MHz */
87	WL12XX_TCXOCLOCK_16_368	= 4, /* 16.368 MHz */
88	WL12XX_TCXOCLOCK_32_736	= 5, /* 32.736 MHz */
89	WL12XX_TCXOCLOCK_16_8	= 6, /* 16.8 MHz */
90	WL12XX_TCXOCLOCK_33_6	= 7, /* 33.6 MHz */
91};
92
93struct wl12xx_clock {
94	u32	freq;
95	bool	xtal;
96	u8	hw_idx;
97};
98
99struct wl12xx_fw_packet_counters {
100	/* Cumulative counter of released packets per AC */
101	u8 tx_released_pkts[NUM_TX_QUEUES];
102
103	/* Cumulative counter of freed packets per HLID */
104	u8 tx_lnk_free_pkts[WL12XX_MAX_LINKS];
105
106	/* Cumulative counter of released Voice memory blocks */
107	u8 tx_voice_released_blks;
108
109	/* Tx rate of the last transmitted packet */
110	u8 tx_last_rate;
111
112	u8 padding[2];
113} __packed;
114
115/* FW status registers */
116struct wl12xx_fw_status {
117	__le32 intr;
118	u8  fw_rx_counter;
119	u8  drv_rx_counter;
120	u8  reserved;
121	u8  tx_results_counter;
122	__le32 rx_pkt_descs[WL12XX_NUM_RX_DESCRIPTORS];
123
124	__le32 fw_localtime;
125
126	/*
127	 * A bitmap (where each bit represents a single HLID)
128	 * to indicate if the station is in PS mode.
129	 */
130	__le32 link_ps_bitmap;
131
132	/*
133	 * A bitmap (where each bit represents a single HLID) to indicate
134	 * if the station is in Fast mode
135	 */
136	__le32 link_fast_bitmap;
137
138	/* Cumulative counter of total released mem blocks since FW-reset */
139	__le32 total_released_blks;
140
141	/* Size (in Memory Blocks) of TX pool */
142	__le32 tx_total;
143
144	struct wl12xx_fw_packet_counters counters;
145
146	__le32 log_start_addr;
147} __packed;
148
149#endif /* __WL12XX_PRIV_H__ */
150