Searched refs:ch (Results 151 - 175 of 1048) sorted by last modified time

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/linux-master/sound/core/
H A Dpcm_compat.c336 int err, ch, i; local
345 ch = substream->runtime->channels;
346 if (ch > 128)
352 bufs = kmalloc_array(ch, sizeof(void __user *), GFP_KERNEL);
355 for (i = 0; i < ch; i++) {
/linux-master/sound/core/oss/
H A Dmixer_oss.c1134 int ch; local
1140 for (ch = 0; ch < SNDRV_OSS_MAX_MIXERS; ch++)
1141 if (oss_mixer_names[ch] && strcmp(oss_mixer_names[ch], str) == 0)
1143 if (ch >= SNDRV_OSS_MAX_MIXERS) {
1152 mixer_slot_clear(&mixer->slots[ch]);
1162 slot = (struct slot *)mixer->slots[ch].private_data;
1170 tbl->oss_id = ch;
[all...]
/linux-master/include/sound/
H A Demux_synth.h42 void (*reset)(struct snd_emux *emu, int ch);
152 int ch; /* Hardware channel number */ member in struct:snd_emux_voice
/linux-master/include/linux/
H A Dhwmon.h492 * @ch: the char to be considered
499 static inline bool hwmon_is_bad_char(const char ch) argument
501 switch (ch) {
/linux-master/include/linux/firmware/cirrus/
H A Dcs_dsp.h283 struct cs_dsp_chunk ch = { local
288 return ch;
293 * @ch: Pointer to the chunk structure
297 static inline bool cs_dsp_chunk_end(struct cs_dsp_chunk *ch) argument
299 return ch->data == ch->max;
304 * @ch: Pointer to the chunk structure
308 static inline int cs_dsp_chunk_bytes(struct cs_dsp_chunk *ch) argument
310 return ch->bytes;
315 * @ch
319 cs_dsp_chunk_valid_addr(struct cs_dsp_chunk *ch, void *addr) argument
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/linux-master/drivers/pwm/
H A Dpwm-visconti.c28 #define PIPGM_PCSR(ch) (0x400 + 4 * (ch))
29 #define PIPGM_PDUT(ch) (0x420 + 4 * (ch))
30 #define PIPGM_PWMC(ch) (0x440 + 4 * (ch))
H A Dpwm-sunplus.c32 #define SP7021_PWM_MODE0_PWMEN(ch) BIT(ch)
33 #define SP7021_PWM_MODE0_BYPASS(ch) BIT(8 + (ch))
35 #define SP7021_PWM_MODE1_CNT_EN(ch) BIT(ch)
36 #define SP7021_PWM_FREQ(ch) (0x008 + 4 * (ch))
38 #define SP7021_PWM_DUTY(ch) (0x018 + 4 * (ch))
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H A Dpwm-stm32.c311 static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch, argument
339 if (active_channels(priv) & ~(1 << ch * 4)) {
357 regmap_write(priv->regmap, TIM_CCR1 + 4 * ch, dty);
360 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
364 if (ch < 2)
374 static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch, argument
379 mask = TIM_CCER_CC1P << (ch * 4);
381 mask |= TIM_CCER_CC1NP << (ch * 4);
389 static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch) argument
399 mask = TIM_CCER_CC1E << (ch *
414 stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch) argument
478 int ch = pwm->hwpwm; local
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H A Dpwm-sun4i.c31 #define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
45 #define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
H A Dpwm-sifive.c319 int ch; local
324 for (ch = 0; ch < chip->npwm; ch++) {
325 pwm = &chip->pwms[ch];
H A Dpwm-rz-mtu3.c135 unsigned int ch; local
137 for (ch = 0; ch < RZ_MTU3_MAX_HW_CHANNELS; ch++, priv++) {
170 u32 ch; local
173 ch = priv - rz_mtu3_pwm->channel_data;
181 if (!rz_mtu3_pwm->user_count[ch]) {
189 rz_mtu3_pwm->user_count[ch]++;
199 u32 ch; local
202 ch
216 u32 ch; local
248 u32 ch; local
328 u32 ch; local
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H A Dpwm-keembay.c35 #define KMB_PWM_LEADIN_OFFSET(ch) (0x00 + 4 * (ch))
36 #define KMB_PWM_HIGHLOW_OFFSET(ch) (0x20 + 4 * (ch))
79 static void keembay_pwm_enable(struct keembay_pwm *priv, int ch) argument
82 KMB_PWM_LEADIN_OFFSET(ch));
85 static void keembay_pwm_disable(struct keembay_pwm *priv, int ch) argument
88 KMB_PWM_LEADIN_OFFSET(ch));
H A Dpwm-brcmstb.c34 #define PWM_CWORD_MSB(ch) (0x08 + ((ch) * PWM_CH_SIZE))
35 #define PWM_CWORD_LSB(ch) (0x0c + ((ch) * PWM_CH_SIZE))
47 #define PWM_ON(ch) (0x18 + ((ch) * PWM_CH_SIZE))
49 #define PWM_PERIOD(ch) (0x1c + ((ch) * PWM_CH_SIZE))
H A Dpwm-atmel.c117 unsigned int ch, unsigned long offset)
119 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
125 unsigned int ch, unsigned long offset,
128 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
146 static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch) argument
156 chip->update_pending |= (1 << ch);
161 static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch) argument
167 if (chip->update_pending & (1 << ch)) {
170 if (chip->update_pending & (1 << ch))
179 static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch) argument
116 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip, unsigned int ch, unsigned long offset) argument
124 atmel_pwm_ch_writel(struct atmel_pwm_chip *chip, unsigned int ch, unsigned long offset, unsigned long val) argument
[all...]
H A Dpwm-bcm-iproc.c15 #define IPROC_PWM_CTRL_TYPE_SHIFT(ch) (15 + (ch))
16 #define IPROC_PWM_CTRL_POLARITY_SHIFT(ch) (8 + (ch))
17 #define IPROC_PWM_CTRL_EN_SHIFT(ch) (ch)
19 #define IPROC_PWM_PERIOD_OFFSET(ch) (0x04 + ((ch) << 3))
23 #define IPROC_PWM_DUTY_CYCLE_OFFSET(ch) (0x08 + ((ch) <<
[all...]
/linux-master/drivers/pmdomain/renesas/
H A Drcar-sysc.c178 struct rcar_sysc_ch ch; member in struct:rcar_sysc_pd
193 return rcar_sysc_power(&pd->ch, false);
201 return rcar_sysc_power(&pd->ch, true);
255 if (!rcar_sysc_power_is_off(&pd->ch)) {
260 rcar_sysc_power(&pd->ch, true);
415 pd->ch.chan_offs = area->chan_offs;
416 pd->ch.chan_bit = area->chan_bit;
417 pd->ch.isr_bit = area->isr_bit;
476 if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx)
479 return rcar_sysc_power(&pd->ch, o
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/linux-master/drivers/platform/x86/dell/
H A Ddell-laptop.c1559 char ch; local
1563 ret = sscanf(buf, "%d %c", &value, &ch);
1567 ch = 's';
1574 switch (ch) {
/linux-master/drivers/mmc/host/
H A Ddw_mmc.c773 dmaengine_terminate_async(host->dms->ch);
805 ret = dmaengine_slave_config(host->dms->ch, &cfg);
811 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
829 dma_async_issue_pending(host->dms->ch);
841 host->dms->ch = dma_request_chan(host->dev, "rx-tx");
842 if (IS_ERR(host->dms->ch)) {
843 int ret = PTR_ERR(host->dms->ch);
857 if (host->dms->ch) {
858 dma_release_channel(host->dms->ch);
859 host->dms->ch
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/linux-master/drivers/hwmon/
H A Dnct6683.c259 "AMD TSI Addr 9ch",
525 int ch = data->in_index[index]; local
530 reg = NCT6683_REG_MON(ch);
534 reg = NCT6683_REG_MON_LOW(ch);
538 reg = NCT6683_REG_MON_HIGH(ch);
548 int ch = data->temp_index[index]; local
556 reg = NCT6683_REG_INTEL_TEMP_MAX(ch);
559 reg = NCT6683_REG_INTEL_TEMP_CRIT(ch);
568 reg = NCT6683_REG_MON_LOW(ch);
571 reg = NCT6683_REG_TEMP_MAX(ch);
618 u8 ch = data->temp_index[i]; local
[all...]
H A Dmax31790.c19 #define MAX31790_REG_FAN_CONFIG(ch) (0x02 + (ch))
20 #define MAX31790_REG_FAN_DYNAMICS(ch) (0x08 + (ch))
23 #define MAX31790_REG_TACH_COUNT(ch) (0x18 + (ch) * 2)
24 #define MAX31790_REG_PWM_DUTY_CYCLE(ch) (0x30 + (ch) * 2)
25 #define MAX31790_REG_PWMOUT(ch) (0x40 + (ch) *
[all...]
H A Dmax31760.c24 #define STATUS_ALARM_CRIT(ch) BIT(2 + 2 * (ch))
25 #define STATUS_ALARM_MAX(ch) BIT(3 + 2 * (ch))
28 #define REG_TACH(ch) (0x52 + (ch) * 2)
29 #define REG_TEMP_INPUT(ch) (0x56 + (ch) * 2)
30 #define REG_TEMP_MAX(ch) (0x06 + (ch) *
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H A Dmax127.c26 #define MAX127_SET_CHANNEL(ch) (((ch) & 7) << MAX127_CTRL_SEL_SHIFT)
H A Daspeed-g6-pwm-tach.c65 #define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
78 #define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
90 #define TACH_ASPEED_CTRL(ch) (((ch) * 0x10) + 0x08)
117 #define TACH_ASPEED_STS(ch) (((ch) * 0x10) + 0x0C)
405 u8 ch, index; local
409 ch
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/linux-master/drivers/gpu/drm/imx/dcss/
H A Ddcss-scaler.c90 struct dcss_scaler_ch ch[3]; member in struct:dcss_scaler
287 static void dcss_scaler_write(struct dcss_scaler_ch *ch, u32 val, u32 ofs) argument
289 struct dcss_scaler *scl = ch->scl;
291 dcss_ctxld_write(scl->ctxld, scl->ctx_id, val, ch->base_ofs + ofs);
297 struct dcss_scaler_ch *ch; local
301 ch = &scl->ch[i];
303 ch->base_ofs = scaler_base + i * 0x400;
305 ch->base_reg = devm_ioremap(scl->dev, ch
341 struct dcss_scaler_ch *ch = &scl->ch[ch_no]; local
349 struct dcss_scaler_ch *ch = &scl->ch[ch_num]; local
363 dcss_scaler_yuv_enable(struct dcss_scaler_ch *ch, bool en) argument
369 dcss_scaler_rtr_8lines_enable(struct dcss_scaler_ch *ch, bool en) argument
375 dcss_scaler_bit_depth_set(struct dcss_scaler_ch *ch, int depth) argument
402 dcss_scaler_format_set(struct dcss_scaler_ch *ch, enum buffer_format src_fmt, enum buffer_format dst_fmt) argument
410 dcss_scaler_res_set(struct dcss_scaler_ch *ch, int src_xres, int src_yres, int dst_xres, int dst_yres, u32 pix_format, enum buffer_format dst_format) argument
474 dcss_scaler_fractions_set(struct dcss_scaler_ch *ch, int src_xres, int src_yres, int dst_xres, int dst_yres, u32 src_format, u32 dst_format, enum chroma_location src_chroma_loc) argument
570 dcss_scaler_program_5_coef_set(struct dcss_scaler_ch *ch, int base_addr, int coef[][PSC_NUM_TAPS]) argument
605 dcss_scaler_program_7_coef_set(struct dcss_scaler_ch *ch, int base_addr, int coef[][PSC_NUM_TAPS]) argument
644 dcss_scaler_yuv_coef_set(struct dcss_scaler_ch *ch, enum buffer_format src_format, enum buffer_format dst_format, bool use_5_taps, int src_xres, int src_yres, int dst_xres, int dst_yres) argument
699 dcss_scaler_rgb_coef_set(struct dcss_scaler_ch *ch, int src_xres, int src_yres, int dst_xres, int dst_yres) argument
718 dcss_scaler_set_rgb10_order(struct dcss_scaler_ch *ch, const struct drm_format_info *format) argument
763 struct dcss_scaler_ch *ch = &scl->ch[ch_num]; local
773 struct dcss_scaler_ch *ch = &scl->ch[ch_num]; local
830 struct dcss_scaler_ch *ch = &scl->ch[chnum]; local
[all...]
H A Ddcss-dpr.c118 struct dcss_dpr_ch ch[3]; member in struct:dcss_dpr
121 static void dcss_dpr_write(struct dcss_dpr_ch *ch, u32 val, u32 ofs) argument
123 struct dcss_dpr *dpr = ch->dpr;
125 dcss_ctxld_write(dpr->ctxld, dpr->ctx_id, val, ch->base_ofs + ofs);
130 struct dcss_dpr_ch *ch; local
134 ch = &dpr->ch[i];
136 ch->base_ofs = dpr_base + i * 0x1000;
138 ch->base_reg = devm_ioremap(dpr->dev, ch
179 struct dcss_dpr_ch *ch = &dpr->ch[ch_no]; local
185 dcss_dpr_x_pix_wide_adjust(struct dcss_dpr_ch *ch, u32 pix_wide, u32 pix_format) argument
205 dcss_dpr_y_pix_high_adjust(struct dcss_dpr_ch *ch, u32 pix_high, u32 pix_format) argument
219 struct dcss_dpr_ch *ch = &dpr->ch[ch_num]; local
247 struct dcss_dpr_ch *ch = &dpr->ch[ch_num]; local
257 dcss_dpr_argb_comp_sel(struct dcss_dpr_ch *ch, int a_sel, int r_sel, int g_sel, int b_sel) argument
272 dcss_dpr_pix_size_set(struct dcss_dpr_ch *ch, const struct drm_format_info *format) argument
301 dcss_dpr_uv_swap(struct dcss_dpr_ch *ch, bool swap) argument
307 dcss_dpr_y_uv_swap(struct dcss_dpr_ch *ch, bool swap) argument
313 dcss_dpr_2plane_en(struct dcss_dpr_ch *ch, bool en) argument
319 dcss_dpr_yuv_en(struct dcss_dpr_ch *ch, bool en) argument
327 struct dcss_dpr_ch *ch = &dpr->ch[ch_num]; local
382 dcss_dpr_rtram_set(struct dcss_dpr_ch *ch, u32 pix_format) argument
415 dcss_dpr_setup_components(struct dcss_dpr_ch *ch, const struct drm_format_info *format) argument
460 dcss_dpr_tile_set(struct dcss_dpr_ch *ch, uint64_t modifier) argument
495 struct dcss_dpr_ch *ch = &dpr->ch[ch_num]; local
520 struct dcss_dpr_ch *ch = &dpr->ch[chnum]; local
534 struct dcss_dpr_ch *ch = &dpr->ch[ch_num]; local
[all...]

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