/haiku/src/system/kernel/arch/arm/ |
H A D | arch_uart_pl011.cpp | 11 #include <arch/arm/reg.h> 193 ArchUARTPL011::Out32(int reg, uint32 data) argument 195 *(volatile uint32*)(Base() + reg) = data; 200 ArchUARTPL011::In32(int reg) argument 202 return *(volatile uint32*)(Base() + reg);
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/haiku/src/bin/ |
H A D | sysinfo.cpp | 295 print_TLB(uint32 reg, const char *pages) argument 301 entries[0] = (reg & 0xff); 302 ways[0] = ((reg >> 8) & 0xff); 303 entries[1] = ((reg >> 16) & 0xff); 304 ways[1] = ((reg >> 24) & 0xff); 319 print_level2_cache(uint32 reg, const char *name) argument 321 uint32 size = (reg >> 16) & 0xffff; 322 uint32 ways = (reg >> 12) & 0xf; 323 uint32 linesPerTag = (reg >> 8) & 0xf; 325 uint32 lineSize = reg 340 print_level1_cache(uint32 reg, const char *name) argument [all...] |
/haiku/src/add-ons/accelerants/nvidia/engine/ |
H A D | nv_proto.h | 42 void set_pll(uint32 reg, uint32 clk);
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/haiku/src/add-ons/kernel/drivers/network/ether/ipro100/dev/fxp/ |
H A D | if_fxpvar.h | 249 #define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg) 250 #define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg) 251 #define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg) 252 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val) 253 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, va [all...] |
H A D | if_fxp.c | 266 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 267 static int fxp_miibus_writereg(device_t dev, int phy, int reg, 1140 uint16_t reg; local 1148 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 1150 reg = FXP_EEPROM_EECS; 1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1153 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 1155 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 1170 uint16_t reg, data; local 1184 reg 2775 fxp_miibus_readreg(device_t dev, int phy, int reg) argument 2795 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) argument [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/wb840/ |
H A D | wb840.h | 486 #define WB_SETBIT(reg, x) write32(reg, read32(reg) | x) 487 #define WB_CLRBIT(reg, x) write32(reg, read32(reg) & ~x)
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/haiku/src/add-ons/kernel/drivers/network/ether/vt612x/dev/vge/ |
H A D | if_vgevar.h | 217 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 218 bus_write_stream_4(sc->vge_res, reg, val) 219 #define CSR_WRITE_4(sc, reg, val) \ 220 bus_write_4(sc->vge_res, reg, val) 221 #define CSR_WRITE_2(sc, reg, val) \ 222 bus_write_2(sc->vge_res, reg, val) 223 #define CSR_WRITE_1(sc, reg, val) \ 224 bus_write_1(sc->vge_res, reg, val) 226 #define CSR_READ_4(sc, reg) \ 227 bus_read_4(sc->vge_res, reg) [all...] |
H A D | if_vge.c | 362 vge_miibus_readreg(device_t dev, int phy, int reg) argument 373 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 396 vge_miibus_writereg(device_t dev, int phy, int reg, int data) argument 406 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
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/haiku/src/add-ons/kernel/drivers/network/ether/vt612x/dev/mii/ |
H A D | ciphy.c | 129 int reg, speed, gig; local 196 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 197 if (reg & BMSR_LINK)
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/haiku/src/add-ons/kernel/drivers/network/ether/via_rhine/dev/vr/ |
H A D | if_vrreg.h | 753 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->vr_res, reg, val) 754 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val) 755 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->vr_res, reg, val) 757 #define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg) 758 #define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg) [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/via_rhine/dev/mii/ |
H A D | ciphy.c | 129 int reg, speed, gig; local 196 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 197 if (reg & BMSR_LINK)
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/haiku/src/add-ons/kernel/drivers/network/ether/usb_davicom/ |
H A D | DavicomDevice.cpp | 1018 DavicomDevice::_ReadRegister(uint8 reg, size_t size, uint8* buffer) argument 1026 ReqReadRegister, 0, reg, size, buffer, &actualLength); 1038 DavicomDevice::_WriteRegister(uint8 reg, size_t size, uint8* buffer) argument 1047 ReqWriteRegister, 0, reg, size, buffer, &actualLength); 1054 DavicomDevice::_Write1Register(uint8 reg, uint8 value) argument 1060 ReqWriteRegisterByte, value, reg, 0, NULL, &actualLength); 1067 DavicomDevice::_ReadMII(uint8 reg, uint16* data) argument 1070 status_t result = _Write1Register(RegEPAR, EPARIntPHY | (reg & EPARMask)); 1072 TRACE_ALWAYS("Failed to set MII address %#x. Error:%#x\n", reg, result); 1111 DavicomDevice::_WriteMII(uint8 reg, uint1 argument [all...] |
H A D | DavicomDevice.h | 144 status_t _ReadRegister(uint8 reg, size_t size, uint8* buffer); 145 status_t _WriteRegister(uint8 reg, size_t size, uint8* buffer); 146 status_t _Write1Register(uint8 reg, uint8 buffer); 147 status_t _ReadMII(uint8 reg, uint16* data); 148 status_t _WriteMII(uint8 reg, uint16 data);
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/haiku/src/add-ons/kernel/drivers/network/ether/syskonnect/dev/sk/ |
H A D | if_skreg.h | 147 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 150 #define SK_REG(reg) ((reg) & SK_REG_MASK) 177 #define SK_IF_READ_4(sc_if, skip, reg) \ 178 sk_win_read_4(sc_if->sk_softc, reg + \ 180 #define SK_IF_READ_2(sc_if, skip, reg) \ 181 sk_win_read_2(sc_if->sk_softc, reg + \ 183 #define SK_IF_READ_1(sc_if, skip, reg) \ 184 sk_win_read_1(sc_if->sk_softc, reg 1432 int reg; member in struct:sk_bcom_hack [all...] |
H A D | if_sk.c | 354 #define SK_SETBIT(sc, reg, x) \ 355 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 357 #define SK_CLRBIT(sc, reg, x) \ 358 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 360 #define SK_WIN_SETBIT_4(sc, reg, x) \ 361 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 363 #define SK_WIN_CLRBIT_4(sc, reg, 3381 u_int16_t reg; local 3530 u_int16_t reg; local [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/syskonnect/dev/mii/ |
H A D | e1000phy.c | 189 uint16_t reg, page; local 191 reg = PHY_READ(sc, E1000_SCR); 193 reg &= ~E1000_SCR_AUTO_X_MODE; 194 PHY_WRITE(sc, E1000_SCR, reg); 199 reg = PHY_READ(sc, E1000_SCR); 200 reg &= ~E1000_SCR_MODE_MASK; 201 reg |= E1000_SCR_MODE_1000BX; 202 PHY_WRITE(sc, E1000_SCR, reg); 206 reg = PHY_READ(sc, E1000_SCR); 207 reg | 311 int reg; local 477 uint16_t reg; local [all...] |
H A D | xmphy.c | 145 int reg; local 190 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 191 if (reg & BMSR_LINK)
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/haiku/src/add-ons/kernel/drivers/network/ether/sis900/dev/sis/ |
H A D | if_sis.c | 121 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 123 #define CSR_BARRIER(sc, reg, length, flags) \ 124 bus_barrier(sc->sis_res[0], reg, length, flags) 193 #define SIS_SETBIT(sc, reg, x) \ 194 CSR_WRITE_4(sc, reg, \ 195 CSR_READ_4(sc, reg) | (x)) 197 #define SIS_CLRBIT(sc, reg, x) \ 198 CSR_WRITE_4(sc, reg, \ 199 CSR_READ_4(sc, reg) 386 uint8_t reg; local 467 sis_miibus_readreg(device_t dev, int phy, int reg) argument 530 sis_miibus_writereg(device_t dev, int phy, int reg, int data) argument 579 uint32_t reg; local [all...] |
H A D | if_sisreg.h | 402 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 404 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
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/haiku/src/add-ons/kernel/drivers/network/ether/sis900/dev/mii/ |
H A D | nsphyter.c | 225 int reg, i; local 228 reg = BMCR_RESET; 230 reg = BMCR_RESET | BMCR_ISO; 231 PHY_WRITE(sc, MII_BMCR, reg); 253 reg = PHY_READ(sc, MII_BMCR); 254 if (reg != 0 && (reg & BMCR_RESET) == 0) 262 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
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/haiku/src/add-ons/kernel/drivers/network/ether/sis19x/dev/sge/ |
H A D | if_sgereg.h | 376 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sge_res, reg, val) 377 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->sge_res, reg, val) 378 #define CSR_WRITE_1(cs, reg, val) bus_write_1(sc->sge_res, reg, val) 380 #define CSR_READ_4(sc, reg) bus_read_4(sc->sge_res, reg) 381 #define CSR_READ_2(sc, reg) bus_read_2(sc->sge_res, reg) [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/rtl81xx/dev/rl/ |
H A D | if_rlreg.h | 946 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 947 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 948 #define CSR_WRITE_4(sc, reg, val) \ 949 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 950 #define CSR_WRITE_2(sc, reg, val) \ 951 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 952 #define CSR_WRITE_1(sc, reg, val) \ 953 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 955 #define CSR_READ_4(sc, reg) \ 956 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/rtl81xx/dev/re/ |
H A D | if_re.c | 448 re_gmii_readreg(device_t dev, int phy, int reg) argument 458 if (reg == RL_GMEDIASTAT) { 463 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 486 re_gmii_writereg(device_t dev, int phy, int reg, int data) argument 494 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 518 re_miibus_readreg(device_t dev, int phy, int reg) argument 527 rval = re_gmii_readreg(dev, phy, reg); 531 switch (reg) { 572 re_miibus_writereg(device_t dev, int phy, int reg, int data) argument 581 rval = re_gmii_writereg(dev, phy, reg, dat 1222 phy, reg, rid; local 3095 uint32_t reg; local [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/rtl81xx/dev/mii/ |
H A D | rgephy.c | 285 uint16_t reg; local 291 reg = PHY_READ(sc, RGEPHY_F_MII_SSR); 292 if (reg & RGEPHY_F_SSR_LINK) 295 reg = PHY_READ(sc, RGEPHY_MII_SSR); 296 if (reg & RGEPHY_SSR_LINK) 301 reg = PHY_READ(sc, URE_GMEDIASTAT); 303 reg = PHY_READ(sc, RL_GMEDIASTAT); 304 if (reg & RL_GMEDIASTAT_LINK)
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/haiku/src/add-ons/kernel/drivers/network/ether/rtl8139/dev/rl/ |
H A D | if_rl.c | 392 rl_miibus_readreg(device_t dev, int phy, int reg) argument 400 switch (reg) { 434 return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg)); 438 rl_miibus_writereg(device_t dev, int phy, int reg, int data) argument 446 switch (reg) { 474 mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data);
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