1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2008, 2009, 2010 Nikolay Denev <ndenev@gmail.com> 5 * Copyright (c) 2007, 2008 Alexander Pohoyda <alexander.pohoyda@gmx.net> 6 * Copyright (c) 1997, 1998, 1999 7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Bill Paul. 20 * 4. Neither the name of the author nor the names of any co-contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 27 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AUTHORS OR 28 * THE VOICES IN THEIR HEADS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 35 * OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * $FreeBSD$ 38 */ 39 40#ifndef _IF_SGEREG_H 41#define _IF_SGEREG_H 42 43/* 44 * SiS PCI vendor ID. 45 */ 46#define SIS_VENDORID 0x1039 47 48/* 49 * SiS PCI device IDs 50 */ 51#define SIS_DEVICEID_190 0x0190 52#define SIS_DEVICEID_191 0x0191 53 54#define TX_CTL 0x00 55#define TX_DESC 0x04 56#define Reserved0 0x08 57#define TX_NEXT 0x0c 58 59#define RX_CTL 0x10 60#define RX_DESC 0x14 61#define Reserved1 0x18 62#define RX_NEXT 0x1c 63 64#define IntrStatus 0x20 65#define IntrMask 0x24 66#define IntrControl 0x28 67#define IntrTimer 0x2c 68 69#define PMControl 0x30 70#define Reserved2 0x34 71#define ROMControl 0x38 72#define ROMInterface 0x3c 73#define StationControl 0x40 74#define GMIIControl 0x44 75#define GMacIOCR 0x48 76#define GMacIOCTL 0x4c 77#define TxMacControl 0x50 78#define TxMacTimeLimit 0x54 79#define RGMIIDelay 0x58 80#define Reserved3 0x5c 81#define RxMacControl 0x60 /* 1 WORD */ 82#define RxMacAddr 0x62 /* 6x BYTE */ 83#define RxHashTable 0x68 /* 1 LONG */ 84#define RxHashTable2 0x6c /* 1 LONG */ 85#define RxWakeOnLan 0x70 86#define RxWakeOnLanData 0x74 87#define RxMPSControl 0x78 88#define Reserved4 0x7c 89 90/* 91 * IntrStatus Register Content 92 */ 93#define INTR_SOFT 0x40000000 94#define INTR_TIMER 0x20000000 95#define INTR_PAUSE_FRAME 0x00080000 96#define INTR_MAGIC_FRAME 0x00040000 97#define INTR_WAKE_FRAME 0x00020000 98#define INTR_LINK 0x00010000 99#define INTR_RX_IDLE 0x00000080 100#define INTR_RX_DONE 0x00000040 101#define INTR_TXQ1_IDLE 0x00000020 102#define INTR_TXQ1_DONE 0x00000010 103#define INTR_TX_IDLE 0x00000008 104#define INTR_TX_DONE 0x00000004 105#define INTR_RX_HALT 0x00000002 106#define INTR_TX_HALT 0x00000001 107 108#define SGE_INTRS \ 109 (INTR_RX_IDLE | INTR_RX_DONE | INTR_TXQ1_IDLE | \ 110 INTR_TXQ1_DONE |INTR_TX_IDLE | INTR_TX_DONE | \ 111 INTR_TX_HALT | INTR_RX_HALT) 112 113/* 114 * RxStatusDesc Register Content 115 */ 116#define RxRES 0x00200000 117#define RxCRC 0x00080000 118#define RxRUNT 0x00100000 119#define RxRWT 0x00400000 120 121/* 122 * RX_CTL Register Content 123 */ 124#define RX_CTL_POLL 0x00000010 125#define RX_CTL_ENB 0x00000001 126 127/* 128 * TX_CTL Register Content 129 */ 130#define TX_CTL_POLL 0x00000010 131#define TX_CTL_ENB 0x00000001 132 133/* 134 * RxMacControl Register Content 135 */ 136#define AcceptBroadcast 0x0800 137#define AcceptMulticast 0x0400 138#define AcceptMyPhys 0x0200 139#define AcceptAllPhys 0x0100 140#define AcceptErr 0x0020 141#define AcceptRunt 0x0010 142#define RXMAC_STRIP_VLAN 0x0020 143#define RXMAC_STRIP_FCS 0x0010 144#define RXMAC_PAD_ENB 0x0004 145#define RXMAC_CSUM_ENB 0x0002 146 147#define SGE_RX_PAD_BYTES 10 148 149/* Station control register. */ 150#define SC_LOOPBACK 0x80000000 151#define SC_RGMII 0x00008000 152#define SC_FDX 0x00001000 153#define SC_SPEED_MASK 0x00000c00 154#define SC_SPEED_10 0x00000400 155#define SC_SPEED_100 0x00000800 156#define SC_SPEED_1000 0x00000c00 157 158/* 159 * Gigabit Media Independent Interface CTL register 160 */ 161#define GMI_DATA 0xffff0000 162#define GMI_DATA_SHIFT 16 163#define GMI_REG 0x0000f800 164#define GMI_REG_SHIFT 11 165#define GMI_PHY 0x000007c0 166#define GMI_PHY_SHIFT 6 167#define GMI_OP_WR 0x00000020 168#define GMI_OP_RD 0x00000000 169#define GMI_REQ 0x00000010 170#define GMI_MDIO 0x00000008 171#define GMI_MDDIR 0x00000004 172#define GMI_MDC 0x00000002 173#define GMI_MDEN 0x00000001 174 175/* Tx descriptor command bits. */ 176#define TDC_OWN 0x80000000 177#define TDC_INTR 0x40000000 178#define TDC_THOL3 0x30000000 179#define TDC_THOL2 0x20000000 180#define TDC_THOL1 0x10000000 181#define TDC_THOL0 0x00000000 182#define TDC_LS 0x08000000 183#define TDC_IP_CSUM 0x04000000 184#define TDC_TCP_CSUM 0x02000000 185#define TDC_UDP_CSUM 0x01000000 186#define TDC_BST 0x00800000 187#define TDC_EXT 0x00400000 188#define TDC_DEF 0x00200000 189#define TDC_BKF 0x00100000 190#define TDC_CRS 0x00080000 191#define TDC_COL 0x00040000 192#define TDC_CRC 0x00020000 193#define TDC_PAD 0x00010000 194#define TDC_VLAN_MASK 0x0000FFFF 195 196#define SGE_TX_INTR_FRAMES 32 197 198/* 199 * TX descriptor status bits. 200 */ 201#define TDS_INS_VLAN 0x80000000 202#define TDS_OWC 0x00080000 203#define TDS_ABT 0x00040000 204#define TDS_FIFO 0x00020000 205#define TDS_CRS 0x00010000 206#define TDS_COLLS 0x0000ffff 207#define SGE_TX_ERROR(x) ((x) & (TDS_OWC | TDS_ABT | TDS_FIFO | TDS_CRS)) 208#define TX_ERR_BITS "\20" \ 209 "\21CRS\22FIFO\23ABT\24OWC" 210 211/* Rx descriptor command bits. */ 212#define RDC_OWN 0x80000000 213#define RDC_INTR 0x40000000 214#define RDC_IP_CSUM 0x20000000 215#define RDC_TCP_CSUM 0x10000000 216#define RDC_UDP_CSUM 0x08000000 217#define RDC_IP_CSUM_OK 0x04000000 218#define RDC_TCP_CSUM_OK 0x02000000 219#define RDC_UDP_CSUM_OK 0x01000000 220#define RDC_WAKEUP 0x00400000 221#define RDC_MAGIC 0x00200000 222#define RDC_PAUSE 0x00100000 223#define RDC_BCAST 0x000c0000 224#define RDC_MCAST 0x00080000 225#define RDC_UCAST 0x00040000 226#define RDC_CRCOFF 0x00020000 227#define RDC_PREADD 0x00010000 228#define RDC_VLAN_MASK 0x0000FFFF 229 230/* 231 * RX descriptor status bits 232 */ 233#define RDS_VLAN 0x80000000 234#define RDS_DESCS 0x3f000000 235#define RDS_ABORT 0x00800000 236#define RDS_SHORT 0x00400000 237#define RDS_LIMIT 0x00200000 238#define RDS_MIIER 0x00100000 239#define RDS_OVRUN 0x00080000 240#define RDS_NIBON 0x00040000 241#define RDS_COLON 0x00020000 242#define RDS_CRCOK 0x00010000 243#define SGE_RX_ERROR(x) \ 244 ((x) & (RDS_COLON | RDS_NIBON | RDS_OVRUN | RDS_MIIER | \ 245 RDS_LIMIT | RDS_SHORT | RDS_ABORT)) 246#define SGE_RX_NSEGS(x) (((x) & RDS_DESCS) >> 24) 247#define RX_ERR_BITS "\20" \ 248 "\21CRCOK\22COLON\23NIBON\24OVRUN" \ 249 "\25MIIER\26LIMIT\27SHORT\30ABORT" \ 250 "\40VLAN" 251 252#define RING_END 0x80000000 253#define SGE_RX_BYTES(x) ((x) & 0xFFFF) 254#define SGE_INC(x, y) (x) = (((x) + 1) % y) 255 256/* Taken from Solaris driver */ 257#define EI_DATA 0xffff0000 258#define EI_DATA_SHIFT 16 259#define EI_OFFSET 0x0000fc00 260#define EI_OFFSET_SHIFT 10 261#define EI_OP 0x00000300 262#define EI_OP_SHIFT 8 263#define EI_OP_RD (2 << EI_OP_SHIFT) 264#define EI_OP_WR (1 << EI_OP_SHIFT) 265#define EI_REQ 0x00000080 266#define EI_DO 0x00000008 267#define EI_DI 0x00000004 268#define EI_CLK 0x00000002 269#define EI_CS 0x00000001 270 271/* 272 * EEPROM Addresses 273 */ 274#define EEPROMSignature 0x00 275#define EEPROMCLK 0x01 276#define EEPROMInfo 0x02 277#define EEPROMMACAddr 0x03 278 279struct sge_desc { 280 uint32_t sge_sts_size; 281 uint32_t sge_cmdsts; 282 uint32_t sge_ptr; 283 uint32_t sge_flags; 284}; 285 286#define SGE_RX_RING_CNT 256 /* [8, 1024] */ 287#define SGE_TX_RING_CNT 256 /* [8, 8192] */ 288#define SGE_DESC_ALIGN 16 289#define SGE_MAXTXSEGS 35 290#define SGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 291#define SGE_TSO_MAXSEGSIZE 4096 292#define SGE_RX_BUF_ALIGN sizeof(uint64_t) 293 294#define SGE_RX_RING_SZ (SGE_RX_RING_CNT * sizeof(struct sge_desc)) 295#define SGE_TX_RING_SZ (SGE_TX_RING_CNT * sizeof(struct sge_desc)) 296#define SGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 297 298struct sge_list_data { 299 struct sge_desc *sge_rx_ring; 300 struct sge_desc *sge_tx_ring; 301 /* physical bus addresses of sge_rx_ring/sge_tx_ring */ 302 bus_addr_t sge_rx_paddr; 303 bus_addr_t sge_tx_paddr; 304}; 305 306struct sge_txdesc { 307 struct mbuf *tx_m; 308 bus_dmamap_t tx_dmamap; 309 int tx_ndesc; 310}; 311 312struct sge_rxdesc { 313 struct mbuf *rx_m; 314 bus_dmamap_t rx_dmamap; 315}; 316 317struct sge_chain_data { 318 bus_dma_tag_t sge_tag; 319 bus_dma_tag_t sge_rx_tag; 320 bus_dma_tag_t sge_tx_tag; 321 bus_dmamap_t sge_rx_dmamap; 322 bus_dmamap_t sge_tx_dmamap; 323 bus_dma_tag_t sge_txmbuf_tag; 324 bus_dma_tag_t sge_rxmbuf_tag; 325 struct sge_txdesc sge_txdesc[SGE_TX_RING_CNT]; 326 struct sge_rxdesc sge_rxdesc[SGE_RX_RING_CNT]; 327 bus_dmamap_t sge_rx_spare_map; 328 int sge_rx_cons; 329 int sge_tx_prod; 330 int sge_tx_cons; 331 int sge_tx_cnt; 332}; 333 334struct sge_type { 335 uint16_t sge_vid; 336 uint16_t sge_did; 337 char *sge_name; 338}; 339 340struct sge_softc { 341 struct ifnet *sge_ifp; /* interface info */ 342 struct resource *sge_res; 343 int sge_res_id; 344 int sge_res_type; 345 struct resource *sge_irq; 346 void *sge_intrhand; 347 device_t sge_dev; 348 device_t sge_miibus; 349 uint8_t sge_rev; 350 struct sge_list_data sge_ldata; 351 struct sge_chain_data sge_cdata; 352 struct callout sge_stat_ch; 353 int sge_timer; 354 int sge_flags; 355#define SGE_FLAG_FASTETHER 0x0001 356#define SGE_FLAG_SIS190 0x0002 357#define SGE_FLAG_RGMII 0x0010 358#define SGE_FLAG_SPEED_1000 0x2000 359#define SGE_FLAG_FDX 0x4000 360#define SGE_FLAG_LINK 0x8000 361 int sge_if_flags; 362 int sge_intrcontrol; 363 int sge_intrtimer; 364 struct mtx sge_mtx; 365 366 uint32_t haiku_interrupt_status; 367}; 368 369#define SGE_LOCK(_sc) mtx_lock(&(_sc)->sge_mtx) 370#define SGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sge_mtx) 371#define SGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sge_mtx, MA_OWNED) 372 373/* 374 * Register space access macros. 375 */ 376#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sge_res, reg, val) 377#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->sge_res, reg, val) 378#define CSR_WRITE_1(cs, reg, val) bus_write_1(sc->sge_res, reg, val) 379 380#define CSR_READ_4(sc, reg) bus_read_4(sc->sge_res, reg) 381#define CSR_READ_2(sc, reg) bus_read_2(sc->sge_res, reg) 382#define CSR_READ_1(sc, reg) bus_read_1(sc->sge_res, reg) 383 384#define SGE_TIMEOUT 1000 385 386#endif /* _IF_SGEREG_H */ 387