dev/sk/if_sk.c

354 #define SK_SETBIT(sc, reg, x)		\
355 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
357 #define SK_CLRBIT(sc, reg, x)		\
358 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
360 #define SK_WIN_SETBIT_4(sc, reg, x)	\
361 	sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
363 #define SK_WIN_CLRBIT_4(sc, reg, x)	\
364 	sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
366 #define SK_WIN_SETBIT_2(sc, reg, x)	\
367 	sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
369 #define SK_WIN_CLRBIT_2(sc, reg, x)	\
370 	sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
373 sk_win_read_4(sc, reg)
375 	int			reg;
378 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
379 	return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
381 	return(CSR_READ_4(sc, reg));
386 sk_win_read_2(sc, reg)
388 	int			reg;
391 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
392 	return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
394 	return(CSR_READ_2(sc, reg));
399 sk_win_read_1(sc, reg)
401 	int			reg;
404 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
405 	return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
407 	return(CSR_READ_1(sc, reg));
412 sk_win_write_4(sc, reg, val)
414 	int			reg;
418 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
419 	CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
421 	CSR_WRITE_4(sc, reg, val);
427 sk_win_write_2(sc, reg, val)
429 	int			reg;
433 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
434 	CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
436 	CSR_WRITE_2(sc, reg, val);
442 sk_win_write_1(sc, reg, val)
444 	int			reg;
448 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
449 	CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
451 	CSR_WRITE_1(sc, reg, val);
470 sk_miibus_readreg(dev, phy, reg)
472 	int			phy, reg;
482 		v = sk_xmac_miibus_readreg(sc_if, phy, reg);
487 		v = sk_marv_miibus_readreg(sc_if, phy, reg);
499 sk_miibus_writereg(dev, phy, reg, val)
501 	int			phy, reg, val;
511 		v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
516 		v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
552 sk_xmac_miibus_readreg(sc_if, phy, reg)
554 	int			phy, reg;
558 	SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
580 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
582 	int			phy, reg, val;
586 	SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
631 sk_marv_miibus_readreg(sc_if, phy, reg)
633 	int			phy, reg;
644 		      YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
664 sk_marv_miibus_writereg(sc_if, phy, reg, val)
666 	int			phy, reg, val;
672 		      YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
3276 			while(bhack[i].reg) {
3278 				    bhack[i].reg, bhack[i].val);
3381 	u_int16_t		reg;
3437 	reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3440 	reg |= YU_PAR_MIB_CLR;
3441 	SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3444 	reg &= ~YU_PAR_MIB_CLR;
3445 	SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3447 	/* receive control reg */
3455 	reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3457 		reg |= YU_SMR_MFL_JUMBO;
3458 	SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3530 	u_int16_t		reg;
3693 		reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3694 		reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3697 		reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3699 		SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);