/linux-master/drivers/gpu/drm/radeon/ |
H A D | r600.c | 2639 WREG32(R600_CP_RB_WPTR, ring->wptr); 2743 ring->wptr = 0; 2744 WREG32(CP_RB_WPTR, ring->wptr); 3371 next_rptr = ring->wptr + 3 + 4; 3377 next_rptr = ring->wptr + 5 + 4; 3461 * increments the rptr. When the rptr catches up with the wptr, all the 3610 /* set rptr, wptr to 0 */ 3722 /* set rptr, wptr to 0 */ 4038 u32 wptr, tmp; local 4041 wptr 4093 u32 wptr; local [all...] |
H A D | si.c | 3395 next_rptr = ring->wptr + 3 + 4 + 8; 3401 next_rptr = ring->wptr + 5 + 4 + 8; 3658 ring->wptr = 0; 3659 WREG32(CP_RB0_WPTR, ring->wptr); 3689 ring->wptr = 0; 3690 WREG32(CP_RB1_WPTR, ring->wptr); 3713 ring->wptr = 0; 3714 WREG32(CP_RB2_WPTR, ring->wptr); 5921 /* set rptr, wptr to 0 */ 6007 /* set rptr, wptr t 6192 u32 wptr, tmp; local 6230 u32 wptr; local [all...] |
H A D | cik.c | 3734 next_rptr = ring->wptr + 3 + 4; 3740 next_rptr = ring->wptr + 5 + 4; 4078 ring->wptr = 0; 4079 WREG32(CP_RB0_WPTR, ring->wptr); 4135 WREG32(CP_RB0_WPTR, ring->wptr); 4160 u32 wptr; local 4164 wptr = rdev->wb.wb[ring->wptr_offs/4]; 4168 wptr = RREG32(CP_HQD_PQ_WPTR); 4173 return wptr; 4180 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; 7483 u32 wptr, tmp; local 7542 u32 wptr; local [all...] |
H A D | evergreen.c | 2939 next_rptr = ring->wptr + 3 + 4; 2945 next_rptr = ring->wptr + 5 + 4; 3097 ring->wptr = 0; 3098 WREG32(CP_RB_WPTR, ring->wptr); 4677 u32 wptr, tmp; local 4680 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 4682 wptr = RREG32(IH_RB_WPTR); 4684 if (wptr & RB_OVERFLOW) { 4685 wptr &= ~RB_OVERFLOW; 4687 * from the last not overwritten vector (wptr 4706 u32 wptr; local [all...] |
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | vcn_v5_0_0.c | 692 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 846 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1066 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1067 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1069 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
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H A D | gfx_v9_0.c | 833 amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask)); 2108 ring->wptr = 0; 2872 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 3117 ring->wptr = 0; 3118 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3119 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3301 ring->wptr = 0; 3348 ring->wptr = 0; 3382 /* disable wptr polling */ 3549 ring->wptr 5081 u64 wptr; local 5361 u64 wptr; local [all...] |
H A D | gfx_v11_0.c | 3286 ring->wptr = 0; 3287 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3288 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3325 ring->wptr = 0; 3326 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3327 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3626 /* set up gfx hqd wptr */ 3724 ring->wptr = 0; 3902 /* disable wptr polling */ 4015 ring->wptr 5220 u64 wptr; local 5258 u64 wptr; local [all...] |
H A D | vcn_v4_0_5.c | 933 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1117 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1342 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1343 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1345 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
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H A D | vcn_v4_0.c | 268 ring->wptr = 0; 1022 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1205 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1355 ring_enc->wptr = 0; 1679 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1680 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1682 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
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H A D | gfx_v6_0.c | 2078 ring->wptr = 0; 2079 WREG32(mmCP_RB0_WPTR, ring->wptr); 2125 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2134 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2137 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2165 ring->wptr = 0; 2166 WREG32(mmCP_RB1_WPTR, ring->wptr); 2185 ring->wptr = 0; 2186 WREG32(mmCP_RB2_WPTR, ring->wptr);
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H A D | gfx_v9_4_3.c | 1307 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1587 ring->wptr = 0; 1634 ring->wptr = 0; 1669 /* disable wptr polling */ 1836 ring->wptr = 0; 1893 ring->wptr = 0; 2664 u64 wptr; local 2668 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2671 return wptr; 2680 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); [all...] |
H A D | amdgpu_umsch_mm.c | 524 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 526 WREG32(umsch->rb_wptr, ring->wptr << 2);
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H A D | gfx_v8_0.c | 4263 ring->wptr = 0; 4264 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 4505 ring->wptr = 0; 4506 mqd->cp_hqd_pq_wptr = ring->wptr; 4566 /* disable wptr polling */ 4607 ring->wptr = 0; 4657 ring->wptr = 0; 6032 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 6033 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 6035 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); [all...] |
H A D | gfx_v10_0.c | 6123 ring->wptr = 0; 6124 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6125 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6162 ring->wptr = 0; 6163 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6164 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6370 /* set up gfx hqd wptr */ 6481 ring->wptr = 0; 6645 /* disable wptr polling */ 6757 ring->wptr 8183 u64 wptr; local 8249 u64 wptr; local [all...] |
H A D | amdgpu_ras.h | 547 unsigned int wptr; member in struct:ras_ih_data
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/linux-master/drivers/scsi/qla4xxx/ |
H A D | ql4_nx.c | 3701 uint16_t *wptr; local 3709 wptr = (uint16_t *)ha->request_ring; 3724 if (*wptr == cpu_to_le16(0xffff)) 3736 chksum += le16_to_cpu(*wptr++); 3815 uint16_t *wptr; local 3824 wptr = (uint16_t *)ha->request_ring; 3829 if (*wptr == cpu_to_le16(0xffff)) 3838 chksum += le16_to_cpu(*wptr++); 3878 uint32_t *wptr; local 3882 wptr [all...] |
/linux-master/drivers/net/ethernet/cortina/ |
H A D | gemini.h | 192 unsigned int wptr : 16; /* Write Ptr, RW */ member in struct:dma_rwptr::bit_000c 948 unsigned int wptr:16; member in struct:nontoe_qhdr1::bit_nonqhdr1
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H A D | gemini.c | 772 w = rw.bits.wptr; 884 pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order; 1258 w = rw.bits.wptr; 1428 w = rw.bits.wptr;
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/linux-master/drivers/gpu/drm/amd/display/dmub/src/ |
H A D | dmub_srv.c | 596 /* reset the cache of the last wptr as well now that hw is reset */ 723 uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); local 725 if (rptr > dmub->inbox1_rb.capacity || wptr > dmub->inbox1_rb.capacity) { 729 dmub->inbox1_rb.wrpt = wptr;
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/linux-master/drivers/scsi/qla2xxx/ |
H A D | qla_isr.c | 570 __le16 __iomem *wptr; local 586 wptr = MAILBOX_REG(ha, reg, 1); 590 wptr = MAILBOX_REG(ha, reg, 8); 592 ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr); 594 ha->mailbox_out[cnt] = rd_reg_word(wptr); 596 wptr++; 609 __le16 __iomem *wptr; local 614 wptr = ®24->mailbox1; 616 wptr = ®82->mailbox_out[1]; 620 for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr 3822 __le16 __iomem *wptr; local [all...] |
/linux-master/drivers/media/platform/amphion/ |
H A D | vpu_rpc.h | 13 u32 wptr; member in struct:vpu_rpc_buffer_desc
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H A D | venc.c | 766 frame->info.wptr - inst->stream_buffer.phys, 770 frame->info.wptr = vpu_helper_step_walk(&inst->stream_buffer, 771 frame->info.wptr, skipped); 810 u32 rptr = frame->info.wptr;
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H A D | vpu_msgs.c | 87 dev_dbg(inst->dev, "[%d] frame id = %d, wptr = 0x%x, size = %d\n", 88 inst->id, info.frame_id, info.wptr, info.frame_size);
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/linux-master/drivers/gpu/drm/msm/ |
H A D | msm_gpu.h | 536 u32 wptr; member in struct:msm_gpu_state::__anon755
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/linux-master/drivers/gpu/drm/msm/adreno/ |
H A D | a5xx_gpu.c | 38 uint32_t wptr; local 53 /* Make sure to wrap wptr if we need to */ 54 wptr = get_wptr(ring); 63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); 180 * Periodically update shadow-wptr if needed, so that we 1081 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
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