drm/radeon/cik.c

3734 			next_rptr = ring->wptr + 3 + 4;
3740 			next_rptr = ring->wptr + 5 + 4;
4078 	ring->wptr = 0;
4079 	WREG32(CP_RB0_WPTR, ring->wptr);
4135 	WREG32(CP_RB0_WPTR, ring->wptr);
4160 	u32 wptr;
4164 		wptr = rdev->wb.wb[ring->wptr_offs/4];
4168 		wptr = RREG32(CP_HQD_PQ_WPTR);
4173 	return wptr;
4180 	rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;
4181 	WDOORBELL32(ring->doorbell_index, ring->wptr);
4190 	/* Disable wptr polling. */
4609 		/* disable wptr polling */
4717 		rdev->ring[idx].wptr = 0;
4718 		mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
6796  * host is currently reading, and a wptr (write pointer)
6800  * wptr.  When there is an interrupt, the host then starts
6840 	/* set rptr, wptr to 0 */
6984 	/* set rptr, wptr to 0 */
7471  * cik_get_ih_wptr - get the IH ring buffer wptr
7475  * Get the IH ring buffer wptr from either the register
7479  * Returns the value of the wptr.
7483 	u32 wptr, tmp;
7486 		wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
7488 		wptr = RREG32(IH_RB_WPTR);
7490 	if (wptr & RB_OVERFLOW) {
7491 		wptr &= ~RB_OVERFLOW;
7493 		 * from the last not overwritten vector (wptr + 16). Hopefully
7497 			 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
7498 		rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
7503 	return (wptr & rdev->ih.ptr_mask);
7542 	u32 wptr;
7556 	wptr = cik_get_ih_wptr(rdev);
7564 	DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
7566 	/* Order reading of wptr vs. reading of IH ring data */
7572 	while (rptr != wptr) {
7573 		/* wptr/rptr are in bytes! */
8080 		/* wptr/rptr are in bytes! */
8098 	/* make sure wptr hasn't changed while processing */
8099 	wptr = cik_get_ih_wptr(rdev);
8100 	if (wptr != rptr)