Lines Matching refs:wptr
833 amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask));
2108 ring->wptr = 0;
2872 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
3117 ring->wptr = 0;
3118 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3119 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3301 ring->wptr = 0;
3348 ring->wptr = 0;
3382 /* disable wptr polling */
3549 ring->wptr = 0;
3607 ring->wptr = 0;
4331 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring))
5081 u64 wptr;
5085 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5087 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
5088 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
5091 return wptr;
5100 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
5101 WDOORBELL64(ring->doorbell_index, ring->wptr);
5103 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5104 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5361 u64 wptr;
5365 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5368 return wptr;
5377 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
5378 WDOORBELL64(ring->doorbell_index, ring->wptr);
5622 ret = ring->wptr & ring->buf_mask;