/linux-master/drivers/gpu/drm/amd/pm/powerplay/ |
H A D | amd_powerplay.c | 437 static void pp_dpm_powergate_vce(void *handle, bool gate) argument 448 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); 451 static void pp_dpm_powergate_uvd(void *handle, bool gate) argument 462 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); 1199 static int pp_dpm_powergate_gfx(void *handle, bool gate) argument 1211 return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate); 1214 static void pp_dpm_powergate_acp(void *handle, bool gate) argument 1226 hwmgr->hwmgr_func->powergate_acp(hwmgr, gate); 1229 static void pp_dpm_powergate_sdma(void *handle, bool gate) argument 1241 hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate); 1244 pp_set_powergating_by_smu(void *handle, uint32_t block_type, bool gate) argument [all...] |
/linux-master/drivers/clk/sunxi/ |
H A D | clk-sunxi.c | 888 u8 gate; /* is it independently gateable? */ member in struct:divs_data::__anon73 916 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ 952 struct clk_gate *gate = NULL; local 1034 /* If this leaf clock can be gated, create a gate */ 1035 if (data->div[i].gate) { 1036 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 1037 if (!gate) 1040 gate->reg = reg; 1041 gate [all...] |
/linux-master/drivers/clk/uniphier/ |
H A D | clk-uniphier.h | 64 struct uniphier_clk_gate_data gate; member in union:uniphier_clk_data::__anon59 100 .data.gate = { \
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/linux-master/drivers/clk/pxa/ |
H A D | clk-pxa.h | 99 * | Mux |---| CKEN gate | 115 struct clk_gate gate; member in struct:desc_clk_cken 128 .gate = { .bit_idx = _cken_bit }, \
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/linux-master/drivers/clk/renesas/ |
H A D | r9a06g032-clocks.c | 62 * @gate: clock enable/disable 69 * which controls some aspect of clock gating. The @gate field 82 struct regbit gate, reset, ready, midle; member in struct:r9a06g032_gate 88 K_GATE = 0, /* gate which enable/disable */ 104 * @gate: clock enable/disable 117 * @dual.g1: 1st source gate (clock enable/disable) 119 * @dual.g2: 2nd source gate (clock enable/disable) 134 struct r9a06g032_gate gate; member in union:r9a06g032_clkdesc::__anon152 157 .gate = _clk, \ 170 .gate 731 struct r9a06g032_gate gate; member in struct:r9a06g032_clk_gate 1174 struct r9a06g032_gate gate[2]; member in struct:r9a06g032_clk_dualgate 1194 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw); local 1203 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw); local [all...] |
/linux-master/net/sched/ |
H A D | act_gate.c | 596 entry->gate.entries = tcf_gate_get_list(act); 598 if (!entry->gate.entries) 602 entry->destructor_priv = entry->gate.entries; 617 entry->gate.prio = tcf_gate_prio(act); 618 entry->gate.basetime = tcf_gate_basetime(act); 619 entry->gate.cycletime = tcf_gate_cycletime(act); 620 entry->gate.cycletimeext = tcf_gate_cycletimeext(act); 621 entry->gate.num_entries = tcf_gate_num_entries(act); 636 .kind = "gate", 648 MODULE_ALIAS_NET_ACT("gate"); [all...] |
/linux-master/drivers/pwm/ |
H A D | pwm-meson.c | 95 struct clk_gate gate; member in struct:meson_pwm_channel 469 snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i); 479 channel->gate.reg = meson->base + REG_MISC_AB; 480 channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_shift; 481 channel->gate.hw.init = &init; 482 channel->gate.flags = 0; 483 channel->gate.lock = &meson->lock; 485 err = devm_clk_hw_register(dev, &channel->gate.hw); 489 channel->clk = devm_clk_hw_get_clk(dev, &channel->gate.hw, NULL);
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/linux-master/drivers/media/platform/samsung/s5p-g2d/ |
H A D | g2d.h | 26 struct clk *gate; member in struct:g2d_dev
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/linux-master/drivers/clk/bcm/ |
H A D | clk-iproc.h | 211 const struct iproc_asiu_gate *gate,
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/linux-master/drivers/clk/ingenic/ |
H A D | cgu.h | 121 * struct ingenic_cgu_gate_info - information about a clock gate 122 * @reg: offset of the gate control register within the CGU 123 * @bit: offset of the bit in the register that controls the gate 151 * @gate: information valid if type includes CGU_CLK_GATE 180 struct ingenic_cgu_gate_info gate; member in struct:ingenic_cgu_clk_info::__anon243::__anon244
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/linux-master/drivers/media/platform/st/stm32/dma2d/ |
H A D | dma2d.h | 116 struct clk *gate; member in struct:dma2d_dev
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H A D | dma2d.c | 495 clk_enable(dev->gate); 527 clk_disable(dev->gate); 620 dev->gate = clk_get(&pdev->dev, "dma2d"); 621 if (IS_ERR(dev->gate)) { 622 dev_err(&pdev->dev, "failed to get dma2d clock gate\n"); 627 ret = clk_prepare(dev->gate); 629 dev_err(&pdev->dev, "failed to prepare dma2d clock gate\n"); 689 clk_unprepare(dev->gate); 691 clk_put(dev->gate); 705 clk_unprepare(dev->gate); [all...] |
/linux-master/drivers/mfd/ |
H A D | sm501.c | 312 * alters the power active gate to set specific units on or off 319 unsigned long gate; local 325 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 347 if (gate & (1 << unit)) 349 gate |= (1 << unit); 351 if (!(gate & (1 << unit))) 353 gate &= ~(1 << unit); 358 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 364 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 370 gate 514 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); local [all...] |
/linux-master/arch/um/os-Linux/drivers/ |
H A D | ethertap_user.c | 91 static int etap_tramp(char *dev, char *gate, int control_me, argument 107 if (gate != NULL) { 108 strscpy(gate_buf, gate);
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/linux-master/drivers/nfc/pn544/ |
H A D | pn544.c | 480 static int pn544_hci_target_from_gate(struct nfc_hci_dev *hdev, u8 gate, argument 483 switch (gate) { 502 u8 gate, 508 if (gate == PN544_RF_READER_NFCIP1_INITIATOR_GATE) 609 pr_info(DRIVER_DESC ": %s for gate=%d\n", __func__, 719 u8 gate = hdev->pipes[pipe].gate; local 725 if (gate == PN544_RF_READER_NFCIP1_INITIATOR_GATE) { 726 r = nfc_hci_target_discovered(hdev, gate); 727 } else if (gate 501 pn544_hci_complete_target_discovered(struct nfc_hci_dev *hdev, u8 gate, struct nfc_target *target) argument [all...] |
/linux-master/net/mac80211/ |
H A D | mesh_pathtbl.c | 177 * @gate_mpath: An active mpath the frames will be sent to (i.e. the gate) 183 * a gate mpath. The function also adds the Address Extension field and 189 * The gate mpath must be an active mpath with a valid mpath->next_hop. 231 mpath_dbg(gate_mpath->sdata, "Mpath queue for gate %pM has %d frames\n", 332 * mesh_path_add_gate - add the given mpath to a mesh gate to our path table 333 * @mpath: gate path to add to table 361 "Mesh path: Recorded new gate: %pM. %d known gates\n", 370 * mesh_gate_del - remove a mesh gate from the list of known gates 372 * @mpath: gate mpath 387 "Mesh path: Deleted gate 968 struct mesh_path *gate; local [all...] |
/linux-master/drivers/media/tuners/ |
H A D | tda18271-common.c | 14 enum tda18271_i2c_gate gate; local 17 switch (priv->gate) { 20 gate = priv->gate; 26 gate = TDA18271_GATE_DIGITAL; 30 gate = TDA18271_GATE_ANALOG; 35 switch (gate) {
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/linux-master/drivers/net/ethernet/microchip/sparx5/ |
H A D | sparx5_tc_flower.c | 704 if (act->gate.prio < -1 || act->gate.prio > SPX5_PSFP_SG_MAX_IPV) { 705 NL_SET_ERR_MSG_MOD(extack, "Invalid gate priority"); 709 if (act->gate.cycletime < SPX5_PSFP_SG_MIN_CYCLE_TIME_NS || 710 act->gate.cycletime > SPX5_PSFP_SG_MAX_CYCLE_TIME_NS) { 711 NL_SET_ERR_MSG_MOD(extack, "Invalid gate cycletime"); 715 if (act->gate.cycletimeext > SPX5_PSFP_SG_MAX_CYCLE_TIME_NS) { 716 NL_SET_ERR_MSG_MOD(extack, "Invalid gate cycletimeext"); 720 if (act->gate.num_entries >= SPX5_PSFP_GCE_CNT) { 721 NL_SET_ERR_MSG_MOD(extack, "Invalid number of gate entrie [all...] |
/linux-master/drivers/clk/st/ |
H A D | clkgen-pll.c | 708 struct clk_gate *gate; local 713 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 714 if (!gate) 717 gate->flags = CLK_GATE_SET_TO_DISABLE; 718 gate->reg = reg + pll_data->odf_gate[odf].offset; 719 gate->bit_idx = pll_data->odf_gate[odf].shift; 720 gate->lock = odf_lock; 724 kfree(gate); 737 &gate [all...] |
/linux-master/drivers/net/dsa/sja1105/ |
H A D | sja1105_flower.c | 420 act->gate.prio, 421 act->gate.basetime, 422 act->gate.cycletime, 423 act->gate.cycletimeext, 424 act->gate.num_entries, 425 act->gate.entries); 444 "Can only offload gate action together with redirect or trap");
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/linux-master/net/nfc/hci/ |
H A D | hci.h | 12 u8 gate; member in struct:gate_pipe_map
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/linux-master/drivers/clk/hisilicon/ |
H A D | clk.h | 3 * Hisilicon Hi3620 clock gate driver 155 hisi_clk_unregister(gate)
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/linux-master/scripts/gcc-plugins/ |
H A D | gcc-generate-gimple-pass.h | 94 virtual bool gate(function *) { return _GATE(); } function in class:__anon1200::_PASS_NAME_PASS
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H A D | gcc-generate-simple_ipa-pass.h | 94 virtual bool gate(function *) { return _GATE(); } function in class:__anon1203::_PASS_NAME_PASS
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H A D | gcc-generate-rtl-pass.h | 94 virtual bool gate(function *) { return _GATE(); } function in class:__anon1202::_PASS_NAME_PASS
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