clk/renesas/r9a06g032-clocks.c

62  * @gate:   clock enable/disable
69  * which controls some aspect of clock gating. The @gate field
82 	struct regbit gate, reset, ready, midle;
88 	K_GATE = 0,	/* gate which enable/disable */
104  * @gate:      clock enable/disable
117  * @dual.g1:   1st source gate (clock enable/disable)
119  * @dual.g2:   2nd source gate (clock enable/disable)
134 		struct r9a06g032_gate gate;
157 	.gate = _clk, \
170 	.gate = I_GATE(__VA_ARGS__) \
178 	.gate = I_GATE(__VA_ARGS__) \
631 	 * parent for a clock, but also the gate it's supposed to use.
722  * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
723  * clock gate framework as the gates on the R9A06G032 have a special enabling
731 	struct r9a06g032_gate gate;
820 	WARN_ON(!g->gate.reg && !g->gate.bit);
823 	clk_rdesc_set(clocks, g->gate, on);
848 	r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);
856 	r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);
863 	/* if clock is in reset, the gate might be on, and still not 'be' on */
864 	if (g->gate.reset.reg && !clk_rdesc_get(g->clocks, g->gate.reset))
867 	return clk_rdesc_get(g->clocks, g->gate.gate);
897 	g->gate = desc->gate;
1093  * active gate (and turn the others off) and force a recalculation of the rates.
1097  * that knows which gate to poke at, depending on the parent's bit position.
1142 	/* allocate the gate */
1174 	struct r9a06g032_gate gate[2];
1185 	/* we always turn off the 'other' gate, regardless */
1186 	r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
1187 	r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
1194 	struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
1196 	r9a06g032_clk_dualgate_setenable(gate, 1);
1203 	struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
1205 	r9a06g032_clk_dualgate_setenable(gate, 0);
1213 	return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
1232 	/* allocate the gate */
1239 	g->gate[0].gate = desc->dual.g1;
1240 	g->gate[0].reset = desc->dual.r1;
1241 	g->gate[1].gate = desc->dual.g2;
1242 	g->gate[1].reset = desc->dual.r2;