/u-boot/drivers/spi/ |
H A D | stm32_spi.c | 102 void __iomem *base; member in struct:stm32_spi_plat 126 void __iomem *base = plat->base; local 129 (readl(base + STM32_SPI_SR) & SPI_SR_TXP)) { 136 writel(*tx_buf32, base + STM32_SPI_TXDR); 142 writew(*tx_buf16, base + STM32_SPI_TXDR); 147 writeb(*tx_buf8, base + STM32_SPI_TXDR); 159 void __iomem *base = plat->base; local 160 u32 sr = readl(base 196 stm32_spi_enable(void __iomem *base) argument 206 stm32_spi_disable(void __iomem *base) argument 220 void __iomem *base = plat->base; local 232 void __iomem *base = plat->base; local 243 void __iomem *base = plat->base; local 294 void __iomem *base = plat->base; local 329 void __iomem *base = plat->base; local 353 void __iomem *base = plat->base; local 392 void __iomem *base = plat->base; local 497 void __iomem *base = plat->base; local 545 void __iomem *base = plat->base; local 614 void __iomem *base = plat->base; local [all...] |
H A D | uniphier_spi.c | 74 void __iomem *base; member in struct:uniphier_spi_plat 82 void __iomem *base; member in struct:uniphier_spi_priv 93 val = readl(priv->base + SSI_CTL); 98 writel(val, priv->base + SSI_CTL); 103 pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL)); 104 pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS)); 105 pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS)); 106 pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS)); 107 pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS)); 108 pr_debug("SR %08x\n", readl(priv->base [all...] |
/u-boot/drivers/serial/ |
H A D | serial_stm32.c | 33 static void _stm32_serial_setbrg(void __iomem *base, argument 43 clrbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit)); 49 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8); 52 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8); 58 writel(mantissa | fraction, base + BRR_OFFSET(stm32f4)); 60 setbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit)); 67 _stm32_serial_setbrg(plat->base, plat->uart_info, 78 void __iomem *cr1 = plat->base + CR1_OFFSET(stm32f4); 125 void __iomem *base = plat->base; local 144 _stm32_serial_putc(void __iomem *base, struct stm32_uart_info *uart_info, const char c) argument 169 void __iomem *base = plat->base; local 179 _stm32_serial_init(void __iomem *base, struct stm32_uart_info *uart_info) argument 303 void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); local 314 void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); local [all...] |
H A D | serial_msm_geni.c | 132 phys_addr_t base; member in struct:msm_serial_data 200 * @base: Pointer to the concerned serial engine. 207 static inline u32 geni_se_get_tx_fifo_depth(long base) argument 211 tx_fifo_depth = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_DEPTH_MSK) >> 218 * @base: Pointer to the concerned serial engine. 225 static inline u32 geni_se_get_tx_fifo_width(long base) argument 229 tx_fifo_width = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_WIDTH_MSK) >> 261 geni_serial_baud(priv->base, clk_div, baud); 268 * @base: Pointer to the concerned serial engine. 296 tx_fifo_depth = geni_se_get_tx_fifo_depth(priv->base); 317 qcom_geni_serial_setup_tx(u64 base, u32 xmit_size) argument 343 qcom_geni_serial_tx_empty(u64 base) argument 357 geni_se_setup_s_cmd(u64 base, u32 cmd, u32 params) argument 368 qcom_geni_serial_start_tx(u64 base) argument 643 phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); local 652 phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); local [all...] |
/u-boot/drivers/gpio/ |
H A D | mpc8xx_gpio.c | 37 /* The bank's register base in memory */ 38 void __iomem *base; member in struct:mpc8xx_gpio_data 85 static inline u16 gpio16_get_val(void __iomem *base, u16 mask, int type) argument 87 struct iop_16 *regs = base; 92 static inline u16 gpio16_get_dir(void __iomem *base, u16 mask, int type) argument 94 struct iop_16 *regs = base; 99 static inline void gpio16_set_in(void __iomem *base, u16 gpios, int type) argument 101 struct iop_16 *regs = base; 108 static inline void gpio16_set_lo(void __iomem *base, u16 gpios, int type) argument 110 struct iop_16 *regs = base; 117 gpio16_set_hi(void __iomem *base, u16 gpios, int type) argument 127 gpio32_get_val(void __iomem *base, u32 mask, int type) argument 137 gpio32_get_dir(void __iomem *base, u32 mask, int type) argument 147 gpio32_set_in(void __iomem *base, u32 gpios, int type) argument 162 gpio32_set_lo(void __iomem *base, u32 gpios, int type) argument 177 gpio32_set_hi(void __iomem *base, u32 gpios, int type) argument [all...] |
H A D | mpc8xxx_gpio.c | 20 /* The bank's register base in memory */ 21 struct ccsr_gpio __iomem *base; member in struct:mpc8xxx_gpio_data 50 return in_le32(&data->base->gpdat) & mask; 52 return in_be32(&data->base->gpdat) & mask; 60 return in_le32(&data->base->gpdir) & mask; 62 return in_be32(&data->base->gpdir) & mask; 70 return in_le32(&data->base->gpodr) & mask; 72 return in_be32(&data->base->gpodr) & mask; 81 setbits_le32(&data->base->gpodr, gpios); 83 setbits_be32(&data->base 114 struct ccsr_gpio *base = data->base; local [all...] |
H A D | da8xx_gpio.h | 24 struct davinci_gpio *base; member in struct:davinci_gpio_bank 36 ulong base; /* address of registers in physical memory */ member in struct:davinci_gpio_plat
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H A D | cortina_gpio.c | 29 void __iomem *base; member in struct:cortina_gpio_bank 37 setbits_32(priv->base, BIT(offset)); 46 clrbits_32(priv->base, BIT(offset)); 54 return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset); 62 setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset)); 70 if (readl(priv->base) & BIT(offset)) 89 priv->base = dev_remap_addr_index(dev, 0); 90 if (!priv->base)
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H A D | hi6220_gpio.c | 19 data = readb(bank->base + HI6220_GPIO_DIR); 21 writeb(data, bank->base + HI6220_GPIO_DIR); 31 writeb(!!value << gpio, bank->base + (BIT(gpio + 2))); 41 data = readb(bank->base + HI6220_GPIO_DIR); 43 writeb(data, bank->base + HI6220_GPIO_DIR); 54 return !!readb(bank->base + (BIT(gpio + 2))); 80 bank->base = (u8 *)plat->base;
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/u-boot/drivers/adc/ |
H A D | stm32-adc-core.h | 35 * @base: control registers base cpu addr 43 void __iomem *base; member in struct:stm32_adc_common
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/u-boot/arch/x86/include/asm/arch-apollolake/ |
H A D | uart.h | 36 void apl_uart_init(pci_dev_t bdf, ulong base);
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/u-boot/include/dm/platform_data/ |
H A D | serial_sh.h | 26 * @base: Register base address 32 unsigned long base; member in struct:sh_serial_plat
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H A D | serial_pl01x.h | 17 * @base: Register base address 28 unsigned long base; member in struct:pl01x_serial_plat
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/u-boot/drivers/clk/exynos/ |
H A D | clk-pll.h | 25 void samsung_clk_register_pll(void __iomem *base, unsigned int cmu_id,
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/u-boot/drivers/video/ |
H A D | mcde_simple.c | 49 fdt_addr_t base; member in struct:mcde_simple_priv 60 priv->base = dev_read_addr(dev); 61 if (priv->base == FDT_ADDR_T_NONE) 64 plat->base = readl(priv->base + MCDE_EXTSRC0A0); 65 if (!plat->base) 68 val = readl(priv->base + MCDE_OVL0CONF); 73 val = readl(priv->base + MCDE_EXTSRC0CONF); 87 val = readl(priv->base + MCDE_CHNL0SYNCHMOD); 91 debug("MCDE base [all...] |
/u-boot/drivers/watchdog/ |
H A D | designware_wdt.c | 23 void __iomem *base; member in struct:designware_wdt_priv 32 static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz, argument 41 writel(i | (i << 4), base + DW_WDT_TORR); 46 static void designware_wdt_enable(void __iomem *base) argument 48 writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR); 51 static unsigned int designware_wdt_is_enabled(void __iomem *base) argument 53 return readl(base + DW_WDT_CR) & BIT(0); 56 static void designware_wdt_reset_common(void __iomem *base) argument 58 if (designware_wdt_is_enabled(base)) 60 writel(DW_WDT_CRR_RESTART_VAL, base [all...] |
H A D | bcm2835_wdt.c | 30 void __iomem *base; member in struct:bcm2835_wdt_priv 38 void __iomem *base = priv->base; local 41 writel(PM_PASSWORD | timeout_ticks, base + PM_WDOG); 42 cur = readl(base + PM_RSTC); 44 base + PM_RSTC); 76 void __iomem *base = priv->base; local 78 writel(PM_PASSWORD | PM_RSTC_RESET, base + PM_RSTC); 114 priv->base [all...] |
H A D | apple_wdt.c | 18 void *base; member in struct:apple_wdt_priv 26 writel(0, priv->base + APPLE_WDT_CUR_TIME); 40 writel(0, priv->base + APPLE_WDT_CUR_TIME); 41 writel(timeout, priv->base + APPLE_WDT_BARK_TIME); 42 writel(APPLE_WDT_CTRL_RESET_EN, priv->base + APPLE_WDT_CTRL); 51 writel(0, priv->base + APPLE_WDT_CTRL); 91 priv->base = dev_read_addr_ptr(dev); 92 if (!priv->base)
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/u-boot/drivers/reset/ |
H A D | stm32-reset.c | 27 fdt_addr_t base; member in struct:stm32_reset_priv 42 writel(BIT(offset), priv->base + bank); 44 clrbits_le32(priv->base + bank, BIT(offset)); 46 setbits_le32(priv->base + bank, BIT(offset)); 63 writel(BIT(offset), priv->base + bank + RCC_CL); 65 setbits_le32(priv->base + bank, BIT(offset)); 67 clrbits_le32(priv->base + bank, BIT(offset)); 81 priv->base = dev_read_addr(dev); 82 if (priv->base == FDT_ADDR_T_NONE) { 84 priv->base [all...] |
/u-boot/arch/arm/cpu/armv7/bcm235xx/ |
H A D | clk-core.c | 56 static inline int wait_bit(void *base, u32 offset, u32 bit, bool want) argument 65 val = readl(base + offset); 73 __func__, base + offset, bit, want); 86 void *base = (void *)c->ccu_clk_mgr_base; local 94 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); 108 reg = readl(base + cd->gate.offset); 110 writel(reg, base + cd->gate.offset); 115 reg = readl(base + cd->div.offset); 118 writel(reg, base + cd->div.offset); 123 reg = readl(base 210 void *base = (void *)c->ccu_clk_mgr_base; local 261 void *base = (void *)c->ccu_clk_mgr_base; local 340 void *base = (void *)c->ccu_clk_mgr_base; local [all...] |
/u-boot/arch/arm/cpu/armv7/bcm281xx/ |
H A D | clk-core.c | 56 static inline int wait_bit(void *base, u32 offset, u32 bit, bool want) argument 65 val = readl(base + offset); 73 __func__, base + offset, bit, want); 86 void *base = (void *)c->ccu_clk_mgr_base; local 94 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); 108 reg = readl(base + cd->gate.offset); 110 writel(reg, base + cd->gate.offset); 115 reg = readl(base + cd->div.offset); 118 writel(reg, base + cd->div.offset); 123 reg = readl(base 210 void *base = (void *)c->ccu_clk_mgr_base; local 261 void *base = (void *)c->ccu_clk_mgr_base; local 340 void *base = (void *)c->ccu_clk_mgr_base; local [all...] |
/u-boot/drivers/clk/rockchip/ |
H A D | clk_pll.c | 293 void __iomem *base, ulong pll_id, 313 rk_clrsetreg(base + pll->mode_offset, 318 rk_setreg(base + pll->con_offset + 0x4, 321 rk_clrsetreg(base + pll->con_offset, 326 rk_clrsetreg(base + pll->con_offset + 0x4, 332 rk_clrsetreg(base + pll->con_offset + 0x4, 335 writel((readl(base + pll->con_offset + 0x8) & 338 base + pll->con_offset + 0x8); 342 rk_clrreg(base + pll->con_offset + 0x4, 346 while (!(readl(base 292 rk3036_pll_set_rate(struct rockchip_pll_clock *pll, void __iomem *base, ulong pll_id, ulong drate) argument 360 rk3036_pll_get_rate(struct rockchip_pll_clock *pll, void __iomem *base, ulong pll_id) argument 428 rk3588_pll_set_rate(struct rockchip_pll_clock *pll, void __iomem *base, ulong pll_id, ulong drate) argument 546 rk3588_pll_get_rate(struct rockchip_pll_clock *pll, void __iomem *base, ulong pll_id) argument 605 rockchip_pll_get_rate(struct rockchip_pll_clock *pll, void __iomem *base, ulong pll_id) argument 631 rockchip_pll_set_rate(struct rockchip_pll_clock *pll, void __iomem *base, ulong pll_id, ulong drate) argument [all...] |
/u-boot/drivers/clk/qcom/ |
H A D | clock-apq8096.c | 55 clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); 56 clk_rcg_set_rate_mnd(priv->base, SDCC2_CMD_RCGR, div, 0, 0, 58 clk_enable_gpll0(priv->base, &gpll0_vote_clk); 59 clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); 67 clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk); 70 clk_rcg_set_rate_mnd(priv->base, BLSP2_UART2_APPS_CMD_RCGR, 1, 192, 15625, 74 clk_enable_gpll0(priv->base, &gpll0_vote_clk); 77 clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR);
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/u-boot/common/ |
H A D | memsize.c | 43 * the actually available RAM size between addresses `base' and 44 * `base + maxsize'. 46 long get_ram_size(long *base, long maxsize) argument 58 addr = base + cnt; /* pointer arith! */ 67 addr = base; 80 *base = save_base; 82 addr = base + cnt; 90 addr = base + cnt; /* pointer arith! */ 102 addr = base + cnt; 107 * base an [all...] |
/u-boot/drivers/net/octeontx2/ |
H A D | rvu_common.c | 17 q->base = memalign(CONFIG_SYS_CACHELINE_SIZE, qsize * entry_sz); 18 if (!q->base) 23 q->iova = (dma_addr_t)(q->base); 25 q->qsize, q->entry_sz, q->alloc_sz, q->base); 31 if (q->base) 32 free(q->base);
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