1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Qualcomm GENI serial engine UART driver 4 * 5 * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> 6 * 7 * Based on Linux driver. 8 */ 9 10#include <asm/io.h> 11#include <clk.h> 12#include <common.h> 13#include <dm.h> 14#include <errno.h> 15#include <linux/delay.h> 16#include <linux/time.h> 17#include <misc.h> 18#include <serial.h> 19 20#define UART_OVERSAMPLING 32 21#define STALE_TIMEOUT 160 22 23/* Registers*/ 24#define GENI_FORCE_DEFAULT_REG 0x20 25#define GENI_SER_M_CLK_CFG 0x48 26#define GENI_SER_S_CLK_CFG 0x4C 27#define SE_HW_PARAM_0 0xE24 28#define SE_GENI_STATUS 0x40 29#define SE_GENI_S_CMD0 0x630 30#define SE_GENI_S_CMD_CTRL_REG 0x634 31#define SE_GENI_S_IRQ_CLEAR 0x648 32#define SE_GENI_S_IRQ_STATUS 0x640 33#define SE_GENI_S_IRQ_EN 0x644 34#define SE_GENI_M_CMD0 0x600 35#define SE_GENI_M_CMD_CTRL_REG 0x604 36#define SE_GENI_M_IRQ_CLEAR 0x618 37#define SE_GENI_M_IRQ_STATUS 0x610 38#define SE_GENI_M_IRQ_EN 0x614 39#define SE_GENI_TX_FIFOn 0x700 40#define SE_GENI_RX_FIFOn 0x780 41#define SE_GENI_TX_FIFO_STATUS 0x800 42#define SE_GENI_RX_FIFO_STATUS 0x804 43#define SE_GENI_TX_WATERMARK_REG 0x80C 44#define SE_GENI_TX_PACKING_CFG0 0x260 45#define SE_GENI_TX_PACKING_CFG1 0x264 46#define SE_GENI_RX_PACKING_CFG0 0x284 47#define SE_GENI_RX_PACKING_CFG1 0x288 48#define SE_UART_RX_STALE_CNT 0x294 49#define SE_UART_TX_TRANS_LEN 0x270 50#define SE_UART_TX_STOP_BIT_LEN 0x26c 51#define SE_UART_TX_WORD_LEN 0x268 52#define SE_UART_RX_WORD_LEN 0x28c 53#define SE_UART_TX_TRANS_CFG 0x25c 54#define SE_UART_TX_PARITY_CFG 0x2a4 55#define SE_UART_RX_TRANS_CFG 0x280 56#define SE_UART_RX_PARITY_CFG 0x2a8 57 58#define M_TX_FIFO_WATERMARK_EN (BIT(30)) 59#define DEF_TX_WM 2 60/* GENI_FORCE_DEFAULT_REG fields */ 61#define FORCE_DEFAULT (BIT(0)) 62 63#define S_CMD_ABORT_EN (BIT(5)) 64 65#define UART_START_READ 0x1 66 67/* GENI_M_CMD_CTRL_REG */ 68#define M_GENI_CMD_CANCEL (BIT(2)) 69#define M_GENI_CMD_ABORT (BIT(1)) 70#define M_GENI_DISABLE (BIT(0)) 71 72#define M_CMD_ABORT_EN (BIT(5)) 73#define M_CMD_DONE_EN (BIT(0)) 74#define M_CMD_DONE_DISABLE_MASK (~M_CMD_DONE_EN) 75 76#define S_GENI_CMD_ABORT (BIT(1)) 77 78/* GENI_S_CMD0 fields */ 79#define S_OPCODE_MSK (GENMASK(31, 27)) 80#define S_PARAMS_MSK (GENMASK(26, 0)) 81 82/* GENI_STATUS fields */ 83#define M_GENI_CMD_ACTIVE (BIT(0)) 84#define S_GENI_CMD_ACTIVE (BIT(12)) 85#define M_CMD_DONE_EN (BIT(0)) 86#define S_CMD_DONE_EN (BIT(0)) 87 88#define M_OPCODE_SHIFT 27 89#define S_OPCODE_SHIFT 27 90#define M_TX_FIFO_WATERMARK_EN (BIT(30)) 91#define UART_START_TX 0x1 92#define UART_CTS_MASK (BIT(1)) 93#define M_SEC_IRQ_EN (BIT(31)) 94#define TX_FIFO_WC_MSK (GENMASK(27, 0)) 95#define RX_FIFO_WC_MSK (GENMASK(24, 0)) 96 97#define S_RX_FIFO_WATERMARK_EN (BIT(26)) 98#define S_RX_FIFO_LAST_EN (BIT(27)) 99#define M_RX_FIFO_WATERMARK_EN (BIT(26)) 100#define M_RX_FIFO_LAST_EN (BIT(27)) 101 102/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ 103#define SER_CLK_EN (BIT(0)) 104#define CLK_DIV_MSK (GENMASK(15, 4)) 105#define CLK_DIV_SHFT 4 106 107/* SE_HW_PARAM_0 fields */ 108#define TX_FIFO_WIDTH_MSK (GENMASK(29, 24)) 109#define TX_FIFO_WIDTH_SHFT 24 110#define TX_FIFO_DEPTH_MSK (GENMASK(21, 16)) 111#define TX_FIFO_DEPTH_SHFT 16 112 113/* GENI SE QUP Registers */ 114#define QUP_HW_VER_REG 0x4 115#define QUP_SE_VERSION_2_5 0x20050000 116 117/* 118 * Predefined packing configuration of the serial engine (CFG0, CFG1 regs) 119 * for uart mode. 120 * 121 * Defines following configuration: 122 * - Bits of data per transfer word 8 123 * - Number of words per fifo element 4 124 * - Transfer from MSB to LSB or vice-versa false 125 */ 126#define UART_PACKING_CFG0 0xf 127#define UART_PACKING_CFG1 0x0 128 129DECLARE_GLOBAL_DATA_PTR; 130 131struct msm_serial_data { 132 phys_addr_t base; 133 u32 baud; 134 u32 oversampling; 135}; 136 137unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200, 138 32000000, 48000000, 64000000, 80000000, 139 96000000, 100000000}; 140 141/** 142 * get_clk_cfg() - Get clock rate to apply on clock supplier. 143 * @clk_freq: Desired clock frequency after build-in divider. 144 * 145 * Return: frequency, supported by clock supplier, multiple of clk_freq. 146 */ 147static int get_clk_cfg(unsigned long clk_freq) 148{ 149 for (int i = 0; i < ARRAY_SIZE(root_freq); i++) { 150 if (!(root_freq[i] % clk_freq)) 151 return root_freq[i]; 152 } 153 return 0; 154} 155 156/** 157 * get_clk_div_rate() - Find clock supplier frequency, and calculate divisor. 158 * @baud: Baudrate. 159 * @sampling_rate: Clock ticks per character. 160 * @clk_div: Pointer to calculated divisor. 161 * 162 * This function searches for suitable frequency for clock supplier, 163 * calculates divisor for internal divider, based on found frequency, 164 * and stores divisor under clk_div pointer. 165 * 166 * Return: frequency, supported by clock supplier, multiple of clk_freq. 167 */ 168static int get_clk_div_rate(u32 baud, u64 sampling_rate, u32 *clk_div) 169{ 170 unsigned long ser_clk; 171 unsigned long desired_clk; 172 173 desired_clk = baud * sampling_rate; 174 ser_clk = get_clk_cfg(desired_clk); 175 if (!ser_clk) { 176 pr_err("%s: Can't find matching DFS entry for baud %d\n", 177 __func__, baud); 178 return ser_clk; 179 } 180 181 *clk_div = ser_clk / desired_clk; 182 return ser_clk; 183} 184 185static int geni_serial_set_clock_rate(struct udevice *dev, u64 rate) 186{ 187 struct clk *clk; 188 int ret; 189 190 clk = devm_clk_get(dev, NULL); 191 if (IS_ERR(clk)) 192 return PTR_ERR(clk); 193 194 ret = clk_set_rate(clk, rate); 195 return ret; 196} 197 198/** 199 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine 200 * @base: Pointer to the concerned serial engine. 201 * 202 * This function is used to get the depth i.e. number of elements in the 203 * TX fifo of the serial engine. 204 * 205 * Return: TX fifo depth in units of FIFO words. 206 */ 207static inline u32 geni_se_get_tx_fifo_depth(long base) 208{ 209 u32 tx_fifo_depth; 210 211 tx_fifo_depth = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_DEPTH_MSK) >> 212 TX_FIFO_DEPTH_SHFT); 213 return tx_fifo_depth; 214} 215 216/** 217 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine 218 * @base: Pointer to the concerned serial engine. 219 * 220 * This function is used to get the width i.e. word size per element in the 221 * TX fifo of the serial engine. 222 * 223 * Return: TX fifo width in bits 224 */ 225static inline u32 geni_se_get_tx_fifo_width(long base) 226{ 227 u32 tx_fifo_width; 228 229 tx_fifo_width = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_WIDTH_MSK) >> 230 TX_FIFO_WIDTH_SHFT); 231 return tx_fifo_width; 232} 233 234static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div, 235 int baud) 236{ 237 u32 s_clk_cfg = 0; 238 239 s_clk_cfg |= SER_CLK_EN; 240 s_clk_cfg |= (clk_div << CLK_DIV_SHFT); 241 242 writel(s_clk_cfg, base_address + GENI_SER_M_CLK_CFG); 243 writel(s_clk_cfg, base_address + GENI_SER_S_CLK_CFG); 244} 245 246static int msm_serial_setbrg(struct udevice *dev, int baud) 247{ 248 struct msm_serial_data *priv = dev_get_priv(dev); 249 u64 clk_rate; 250 u32 clk_div; 251 int ret; 252 253 priv->baud = baud; 254 255 clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div); 256 ret = geni_serial_set_clock_rate(dev, clk_rate); 257 if (ret < 0) { 258 pr_err("%s: Couldn't set clock rate: %d\n", __func__, ret); 259 return ret; 260 } 261 geni_serial_baud(priv->base, clk_div, baud); 262 263 return 0; 264} 265 266/** 267 * qcom_geni_serial_poll_bit() - Poll reg bit until desired value or timeout. 268 * @base: Pointer to the concerned serial engine. 269 * @offset: Offset to register address. 270 * @field: AND bitmask for desired bit. 271 * @set: Desired bit value. 272 * 273 * This function is used to get the width i.e. word size per element in the 274 * TX fifo of the serial engine. 275 * 276 * Return: true, when register bit equals desired value, false, when timeout 277 * reached. 278 */ 279static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset, 280 int field, bool set) 281{ 282 u32 reg; 283 struct msm_serial_data *priv = dev_get_priv(dev); 284 unsigned int baud; 285 unsigned int tx_fifo_depth; 286 unsigned int tx_fifo_width; 287 unsigned int fifo_bits; 288 unsigned long timeout_us = 10000; 289 290 baud = 115200; 291 292 if (priv) { 293 baud = priv->baud; 294 if (!baud) 295 baud = 115200; 296 tx_fifo_depth = geni_se_get_tx_fifo_depth(priv->base); 297 tx_fifo_width = geni_se_get_tx_fifo_width(priv->base); 298 fifo_bits = tx_fifo_depth * tx_fifo_width; 299 /* 300 * Total polling iterations based on FIFO worth of bytes to be 301 * sent at current baud. Add a little fluff to the wait. 302 */ 303 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 304 } 305 306 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 307 while (timeout_us) { 308 reg = readl(priv->base + offset); 309 if ((bool)(reg & field) == set) 310 return true; 311 udelay(10); 312 timeout_us -= 10; 313 } 314 return false; 315} 316 317static void qcom_geni_serial_setup_tx(u64 base, u32 xmit_size) 318{ 319 u32 m_cmd; 320 321 writel(xmit_size, base + SE_UART_TX_TRANS_LEN); 322 m_cmd = UART_START_TX << M_OPCODE_SHIFT; 323 writel(m_cmd, base + SE_GENI_M_CMD0); 324} 325 326static inline void qcom_geni_serial_poll_tx_done(const struct udevice *dev) 327{ 328 struct msm_serial_data *priv = dev_get_priv(dev); 329 int done = 0; 330 u32 irq_clear = M_CMD_DONE_EN; 331 332 done = qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS, 333 M_CMD_DONE_EN, true); 334 if (!done) { 335 writel(M_GENI_CMD_ABORT, priv->base + SE_GENI_M_CMD_CTRL_REG); 336 irq_clear |= M_CMD_ABORT_EN; 337 qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS, 338 M_CMD_ABORT_EN, true); 339 } 340 writel(irq_clear, priv->base + SE_GENI_M_IRQ_CLEAR); 341} 342 343static u32 qcom_geni_serial_tx_empty(u64 base) 344{ 345 return !readl(base + SE_GENI_TX_FIFO_STATUS); 346} 347 348/** 349 * geni_se_setup_s_cmd() - Setup the secondary sequencer 350 * @se: Pointer to the concerned serial engine. 351 * @cmd: Command/Operation to setup in the secondary sequencer. 352 * @params: Parameter for the sequencer command. 353 * 354 * This function is used to configure the secondary sequencer with the 355 * command and its associated parameters. 356 */ 357static inline void geni_se_setup_s_cmd(u64 base, u32 cmd, u32 params) 358{ 359 u32 s_cmd; 360 361 s_cmd = readl(base + SE_GENI_S_CMD0); 362 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK); 363 s_cmd |= (cmd << S_OPCODE_SHIFT); 364 s_cmd |= (params & S_PARAMS_MSK); 365 writel(s_cmd, base + SE_GENI_S_CMD0); 366} 367 368static void qcom_geni_serial_start_tx(u64 base) 369{ 370 u32 irq_en; 371 u32 status; 372 373 status = readl(base + SE_GENI_STATUS); 374 if (status & M_GENI_CMD_ACTIVE) 375 return; 376 377 if (!qcom_geni_serial_tx_empty(base)) 378 return; 379 380 irq_en = readl(base + SE_GENI_M_IRQ_EN); 381 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 382 383 writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG); 384 writel(irq_en, base + SE_GENI_M_IRQ_EN); 385} 386 387static void qcom_geni_serial_start_rx(struct udevice *dev) 388{ 389 u32 status; 390 struct msm_serial_data *priv = dev_get_priv(dev); 391 392 status = readl(priv->base + SE_GENI_STATUS); 393 394 geni_se_setup_s_cmd(priv->base, UART_START_READ, 0); 395 396 setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 397 setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 398} 399 400static void qcom_geni_serial_abort_rx(struct udevice *dev) 401{ 402 struct msm_serial_data *priv = dev_get_priv(dev); 403 404 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 405 406 writel(S_GENI_CMD_ABORT, priv->base + SE_GENI_S_CMD_CTRL_REG); 407 qcom_geni_serial_poll_bit(dev, SE_GENI_S_CMD_CTRL_REG, 408 S_GENI_CMD_ABORT, false); 409 writel(irq_clear, priv->base + SE_GENI_S_IRQ_CLEAR); 410 writel(FORCE_DEFAULT, priv->base + GENI_FORCE_DEFAULT_REG); 411} 412 413static void msm_geni_serial_setup_rx(struct udevice *dev) 414{ 415 struct msm_serial_data *priv = dev_get_priv(dev); 416 417 qcom_geni_serial_abort_rx(dev); 418 419 writel(UART_PACKING_CFG0, priv->base + SE_GENI_RX_PACKING_CFG0); 420 writel(UART_PACKING_CFG1, priv->base + SE_GENI_RX_PACKING_CFG1); 421 422 geni_se_setup_s_cmd(priv->base, UART_START_READ, 0); 423 424 setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 425 setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 426} 427 428static int msm_serial_putc(struct udevice *dev, const char ch) 429{ 430 struct msm_serial_data *priv = dev_get_priv(dev); 431 432 writel(DEF_TX_WM, priv->base + SE_GENI_TX_WATERMARK_REG); 433 qcom_geni_serial_setup_tx(priv->base, 1); 434 435 qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS, 436 M_TX_FIFO_WATERMARK_EN, true); 437 438 writel(ch, priv->base + SE_GENI_TX_FIFOn); 439 writel(M_TX_FIFO_WATERMARK_EN, priv->base + SE_GENI_M_IRQ_CLEAR); 440 441 qcom_geni_serial_poll_tx_done(dev); 442 443 return 0; 444} 445 446static int msm_serial_getc(struct udevice *dev) 447{ 448 struct msm_serial_data *priv = dev_get_priv(dev); 449 u32 rx_fifo; 450 u32 m_irq_status; 451 u32 s_irq_status; 452 453 writel(1 << S_OPCODE_SHIFT, priv->base + SE_GENI_S_CMD0); 454 455 qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS, M_SEC_IRQ_EN, 456 true); 457 458 m_irq_status = readl(priv->base + SE_GENI_M_IRQ_STATUS); 459 s_irq_status = readl(priv->base + SE_GENI_S_IRQ_STATUS); 460 writel(m_irq_status, priv->base + SE_GENI_M_IRQ_CLEAR); 461 writel(s_irq_status, priv->base + SE_GENI_S_IRQ_CLEAR); 462 qcom_geni_serial_poll_bit(dev, SE_GENI_RX_FIFO_STATUS, RX_FIFO_WC_MSK, 463 true); 464 465 if (!readl(priv->base + SE_GENI_RX_FIFO_STATUS)) 466 return 0; 467 468 rx_fifo = readl(priv->base + SE_GENI_RX_FIFOn); 469 return rx_fifo & 0xff; 470} 471 472static int msm_serial_pending(struct udevice *dev, bool input) 473{ 474 struct msm_serial_data *priv = dev_get_priv(dev); 475 476 if (input) 477 return readl(priv->base + SE_GENI_RX_FIFO_STATUS) & 478 RX_FIFO_WC_MSK; 479 else 480 return readl(priv->base + SE_GENI_TX_FIFO_STATUS) & 481 TX_FIFO_WC_MSK; 482 483 return 0; 484} 485 486static const struct dm_serial_ops msm_serial_ops = { 487 .putc = msm_serial_putc, 488 .pending = msm_serial_pending, 489 .getc = msm_serial_getc, 490 .setbrg = msm_serial_setbrg, 491}; 492 493static int geni_set_oversampling(struct udevice *dev) 494{ 495 struct msm_serial_data *priv = dev_get_priv(dev); 496 ofnode parent_node = ofnode_get_parent(dev_ofnode(dev)); 497 u32 geni_se_version; 498 fdt_addr_t addr; 499 500 priv->oversampling = UART_OVERSAMPLING; 501 502 /* 503 * It could happen that GENI SE IP is missing in the board's device 504 * tree or GENI UART node is a direct child of SoC device tree node. 505 */ 506 if (!ofnode_device_is_compatible(parent_node, "qcom,geni-se-qup")) { 507 pr_err("%s: UART node must be a child of geniqup node\n", 508 __func__); 509 return -ENODEV; 510 } 511 512 /* Read the HW_VER register relative to the parents address space */ 513 addr = ofnode_get_addr(parent_node); 514 geni_se_version = readl(addr + QUP_HW_VER_REG); 515 516 if (geni_se_version >= QUP_SE_VERSION_2_5) 517 priv->oversampling /= 2; 518 519 return 0; 520} 521 522static inline void geni_serial_init(struct udevice *dev) 523{ 524 struct msm_serial_data *priv = dev_get_priv(dev); 525 phys_addr_t base_address = priv->base; 526 u32 tx_trans_cfg; 527 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 528 u32 rx_trans_cfg = 0; 529 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 530 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 531 u32 bits_per_char; 532 533 /* 534 * Ignore Flow control. 535 * n = 8. 536 */ 537 tx_trans_cfg = UART_CTS_MASK; 538 bits_per_char = BITS_PER_BYTE; 539 540 /* 541 * Make an unconditional cancel on the main sequencer to reset 542 * it else we could end up in data loss scenarios. 543 */ 544 qcom_geni_serial_poll_tx_done(dev); 545 qcom_geni_serial_abort_rx(dev); 546 547 writel(UART_PACKING_CFG0, base_address + SE_GENI_TX_PACKING_CFG0); 548 writel(UART_PACKING_CFG1, base_address + SE_GENI_TX_PACKING_CFG1); 549 writel(UART_PACKING_CFG0, base_address + SE_GENI_RX_PACKING_CFG0); 550 writel(UART_PACKING_CFG1, base_address + SE_GENI_RX_PACKING_CFG1); 551 552 writel(tx_trans_cfg, base_address + SE_UART_TX_TRANS_CFG); 553 writel(tx_parity_cfg, base_address + SE_UART_TX_PARITY_CFG); 554 writel(rx_trans_cfg, base_address + SE_UART_RX_TRANS_CFG); 555 writel(rx_parity_cfg, base_address + SE_UART_RX_PARITY_CFG); 556 writel(bits_per_char, base_address + SE_UART_TX_WORD_LEN); 557 writel(bits_per_char, base_address + SE_UART_RX_WORD_LEN); 558 writel(stop_bit_len, base_address + SE_UART_TX_STOP_BIT_LEN); 559} 560 561static int msm_serial_probe(struct udevice *dev) 562{ 563 struct msm_serial_data *priv = dev_get_priv(dev); 564 int ret; 565 566 ret = geni_set_oversampling(dev); 567 if (ret < 0) 568 return ret; 569 570 /* No need to reinitialize the UART after relocation */ 571 if (gd->flags & GD_FLG_RELOC) 572 return 0; 573 574 geni_serial_init(dev); 575 msm_geni_serial_setup_rx(dev); 576 qcom_geni_serial_start_rx(dev); 577 qcom_geni_serial_start_tx(priv->base); 578 579 return 0; 580} 581 582static int msm_serial_ofdata_to_platdata(struct udevice *dev) 583{ 584 struct msm_serial_data *priv = dev_get_priv(dev); 585 586 priv->base = dev_read_addr(dev); 587 if (priv->base == FDT_ADDR_T_NONE) 588 return -EINVAL; 589 590 return 0; 591} 592 593static const struct udevice_id msm_serial_ids[] = { 594 { .compatible = "qcom,geni-debug-uart" }, 595 { } 596}; 597 598U_BOOT_DRIVER(serial_msm_geni) = { 599 .name = "serial_msm_geni", 600 .id = UCLASS_SERIAL, 601 .of_match = msm_serial_ids, 602 .of_to_plat = msm_serial_ofdata_to_platdata, 603 .priv_auto = sizeof(struct msm_serial_data), 604 .probe = msm_serial_probe, 605 .ops = &msm_serial_ops, 606 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, 607}; 608 609static const struct udevice_id geniqup_ids[] = { 610 { .compatible = "qcom,geni-se-qup" }, 611 { } 612}; 613 614U_BOOT_DRIVER(geni_se_qup) = { 615 .name = "geni-se-qup", 616 .id = UCLASS_NOP, 617 .of_match = geniqup_ids, 618 .bind = dm_scan_fdt_dev, 619 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, 620}; 621 622#ifdef CONFIG_DEBUG_UART_MSM_GENI 623 624static struct msm_serial_data init_serial_data = { 625 .base = CONFIG_VAL(DEBUG_UART_BASE) 626}; 627 628/* Serial dumb device, to reuse driver code */ 629static struct udevice init_dev = { 630 .priv_ = &init_serial_data, 631}; 632 633#include <debug_uart.h> 634 635#define CLK_DIV (CONFIG_DEBUG_UART_CLOCK / \ 636 (CONFIG_BAUDRATE * UART_OVERSAMPLING)) 637#if (CONFIG_DEBUG_UART_CLOCK % (CONFIG_BAUDRATE * UART_OVERSAMPLING) > 0) 638#error Clocks cannot be set at early debug. Change CONFIG_BAUDRATE 639#endif 640 641static inline void _debug_uart_init(void) 642{ 643 phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); 644 645 geni_serial_init(&init_dev); 646 geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE); 647 qcom_geni_serial_start_tx(base); 648} 649 650static inline void _debug_uart_putc(int ch) 651{ 652 phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); 653 654 writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG); 655 qcom_geni_serial_setup_tx(base, 1); 656 qcom_geni_serial_poll_bit(&init_dev, SE_GENI_M_IRQ_STATUS, 657 M_TX_FIFO_WATERMARK_EN, true); 658 659 writel(ch, base + SE_GENI_TX_FIFOn); 660 writel(M_TX_FIFO_WATERMARK_EN, base + SE_GENI_M_IRQ_CLEAR); 661 qcom_geni_serial_poll_tx_done(&init_dev); 662} 663 664DEBUG_UART_FUNCS 665 666#endif 667