1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (c) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 4 * Copyright (c) 2014 Renesas Electronics Corporation 5 */ 6 7#ifndef __serial_sh_h 8#define __serial_sh_h 9 10enum sh_clk_mode { 11 INT_CLK, 12 EXT_CLK, 13}; 14 15enum sh_serial_type { 16 PORT_SCI, 17 PORT_SCIF, 18 PORT_SCIFA, 19 PORT_SCIFB, 20 PORT_HSCIF, 21}; 22 23/* 24 * Information about SCIF port 25 * 26 * @base: Register base address 27 * @clk: Input clock rate, used for calculating the baud rate divisor 28 * @clk_mode: Clock mode, set internal (INT) or external (EXT) 29 * @type: Type of SCIF 30 */ 31struct sh_serial_plat { 32 unsigned long base; 33 unsigned int clk; 34 enum sh_clk_mode clk_mode; 35 enum sh_serial_type type; 36}; 37#endif /* __serial_sh_h */ 38