1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Clock drivers for Qualcomm APQ8096 4 * 5 * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org> 6 * 7 * Based on Little Kernel driver, simplified 8 */ 9 10#include <common.h> 11#include <clk-uclass.h> 12#include <dm.h> 13#include <errno.h> 14#include <asm/io.h> 15#include <linux/bitops.h> 16#include <dt-bindings/clock/qcom,gcc-msm8996.h> 17 18#include "clock-qcom.h" 19 20/* Clocks: (from CLK_CTL_BASE) */ 21#define GPLL0_STATUS (0x0000) 22#define APCS_GPLL_ENA_VOTE (0x52000) 23#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) 24 25#define SDCC2_BCR (0x14000) /* block reset */ 26#define SDCC2_APPS_CBCR (0x14004) /* branch control */ 27#define SDCC2_AHB_CBCR (0x14008) 28#define SDCC2_CMD_RCGR (0x14010) 29 30#define BLSP2_AHB_CBCR (0x25004) 31#define BLSP2_UART2_APPS_CBCR (0x29004) 32#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) 33 34/* GPLL0 clock control registers */ 35#define GPLL0_STATUS_ACTIVE BIT(30) 36#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) 37 38static const struct pll_vote_clk gpll0_vote_clk = { 39 .status = GPLL0_STATUS, 40 .status_bit = GPLL0_STATUS_ACTIVE, 41 .ena_vote = APCS_GPLL_ENA_VOTE, 42 .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0, 43}; 44 45static struct vote_clk gcc_blsp2_ahb_clk = { 46 .cbcr_reg = BLSP2_AHB_CBCR, 47 .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, 48 .vote_bit = BIT(15), 49}; 50 51static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) 52{ 53 int div = 5; 54 55 clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); 56 clk_rcg_set_rate_mnd(priv->base, SDCC2_CMD_RCGR, div, 0, 0, 57 CFG_CLK_SRC_GPLL0, 8); 58 clk_enable_gpll0(priv->base, &gpll0_vote_clk); 59 clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); 60 61 return rate; 62} 63 64static int clk_init_uart(struct msm_clk_priv *priv) 65{ 66 /* Enable AHB clock */ 67 clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk); 68 69 /* 7372800 uart block clock @ GPLL0 */ 70 clk_rcg_set_rate_mnd(priv->base, BLSP2_UART2_APPS_CMD_RCGR, 1, 192, 15625, 71 CFG_CLK_SRC_GPLL0, 16); 72 73 /* Vote for gpll0 clock */ 74 clk_enable_gpll0(priv->base, &gpll0_vote_clk); 75 76 /* Enable core clk */ 77 clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR); 78 79 return 0; 80} 81 82static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate) 83{ 84 struct msm_clk_priv *priv = dev_get_priv(clk->dev); 85 86 switch (clk->id) { 87 case GCC_SDCC1_APPS_CLK: /* SDC1 */ 88 return clk_init_sdc(priv, rate); 89 break; 90 case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/ 91 return clk_init_uart(priv); 92 default: 93 return 0; 94 } 95} 96 97static struct msm_clk_data apq8096_clk_data = { 98 .set_rate = apq8096_clk_set_rate, 99}; 100 101static const struct udevice_id gcc_apq8096_of_match[] = { 102 { 103 .compatible = "qcom,gcc-msm8996", 104 .data = (ulong)&apq8096_clk_data, 105 }, 106 { } 107}; 108 109U_BOOT_DRIVER(gcc_apq8096) = { 110 .name = "gcc_apq8096", 111 .id = UCLASS_NOP, 112 .of_match = gcc_apq8096_of_match, 113 .bind = qcom_cc_bind, 114 .flags = DM_FLAG_PRE_RELOC, 115}; 116