1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2020 Cortina-Access 4 * 5 * GPIO Driver for Cortina Access CAxxxx Line of SoCs 6 */ 7 8#include <dm.h> 9#include <log.h> 10#include <asm/io.h> 11#include <asm/gpio.h> 12#include <linux/bitops.h> 13#include <linux/compat.h> 14#include <linux/compiler.h> 15 16/* GPIO Register Map */ 17#define CORTINA_GPIO_CFG 0x00 18#define CORTINA_GPIO_OUT 0x04 19#define CORTINA_GPIO_IN 0x08 20#define CORTINA_GPIO_LVL 0x0C 21#define CORTINA_GPIO_EDGE 0x10 22#define CORTINA_GPIO_BOTHEDGE 0x14 23#define CORTINA_GPIO_IE 0x18 24#define CORTINA_GPIO_INT 0x1C 25#define CORTINA_GPIO_STAT 0x20 26 27struct cortina_gpio_bank { 28 void __iomem *base; 29}; 30 31#ifdef CONFIG_DM_GPIO 32static int ca_gpio_direction_input(struct udevice *dev, unsigned int offset) 33{ 34 struct cortina_gpio_bank *priv = dev_get_priv(dev); 35 36 setbits_32(priv->base, BIT(offset)); 37 return 0; 38} 39 40static int 41ca_gpio_direction_output(struct udevice *dev, unsigned int offset, int value) 42{ 43 struct cortina_gpio_bank *priv = dev_get_priv(dev); 44 45 clrbits_32(priv->base, BIT(offset)); 46 return 0; 47} 48 49static int ca_gpio_get_value(struct udevice *dev, unsigned int offset) 50{ 51 struct cortina_gpio_bank *priv = dev_get_priv(dev); 52 53 return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset); 54} 55 56static int ca_gpio_set_value(struct udevice *dev, unsigned int offset, 57 int value) 58{ 59 struct cortina_gpio_bank *priv = dev_get_priv(dev); 60 61 setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset)); 62 return 0; 63} 64 65static int ca_gpio_get_function(struct udevice *dev, unsigned int offset) 66{ 67 struct cortina_gpio_bank *priv = dev_get_priv(dev); 68 69 if (readl(priv->base) & BIT(offset)) 70 return GPIOF_INPUT; 71 else 72 return GPIOF_OUTPUT; 73} 74 75static const struct dm_gpio_ops gpio_cortina_ops = { 76 .direction_input = ca_gpio_direction_input, 77 .direction_output = ca_gpio_direction_output, 78 .get_value = ca_gpio_get_value, 79 .set_value = ca_gpio_set_value, 80 .get_function = ca_gpio_get_function, 81}; 82 83static int ca_gpio_probe(struct udevice *dev) 84{ 85 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 86 struct cortina_gpio_bank *priv = dev_get_priv(dev); 87 88 priv->base = dev_remap_addr_index(dev, 0); 89 if (!priv->base) 90 return -EINVAL; 91 92 uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32); 93 uc_priv->bank_name = dev->name; 94 95 debug("Done Cortina GPIO init\n"); 96 return 0; 97} 98 99static const struct udevice_id ca_gpio_ids[] = { 100 {.compatible = "cortina,ca-gpio"}, 101 {} 102}; 103 104U_BOOT_DRIVER(cortina_gpio) = { 105 .name = "cortina-gpio", 106 .id = UCLASS_GPIO, 107 .ops = &gpio_cortina_ops, 108 .probe = ca_gpio_probe, 109 .priv_auto = sizeof(struct cortina_gpio_bank), 110 .of_match = ca_gpio_ids, 111}; 112#endif /* CONFIG_DM_GPIO */ 113