/u-boot/drivers/mmc/ |
H A D | rockchip_sdhci.c | 142 int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable); 308 static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable) argument 316 if (!enable) { 378 * Before switching to hs400es mode, the driver will enable 536 static int rockchip_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable) argument 542 return data->config_dll(host, clock, enable);
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/u-boot/drivers/video/zynqmp/ |
H A D | zynqmp_dpsub.c | 210 static void enable_gfx_buffers(struct udevice *dev, u8 enable) argument 218 if (enable) { 282 static void set_blender_alpha(struct udevice *dev, u8 alpha, u8 enable) argument 287 regval = enable; 326 static void config_msa_sync_clk_mode(struct udevice *dev, u8 enable) argument 332 msa_config->synchronous_clock_mode = enable; 334 if (enable == 1) { 734 static void enable_main_link(struct udevice *dev, u8 enable) argument 741 writel(enable, dp_sub->base_addr + DP_ENABLE_MAIN_STREAM); 783 * @enable 792 set_enhanced_frame_mode(struct udevice *dev, u8 enable) argument 924 set_downspread(struct udevice *dev, u8 enable) argument [all...] |
/u-boot/drivers/pinctrl/renesas/ |
H A D | pfc.c | 405 u32 enable, updown; local 413 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); 415 enable |= BIT(bit); 425 sh_pfc_write(pfc, reg->puen, enable); 427 enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 429 enable |= BIT(bit); 431 sh_pfc_write(pfc, reg->pud, enable);
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/u-boot/drivers/clk/at91/ |
H A D | compat.c | 157 .enable = at91_slow_clk_enable, 214 .enable = main_osc_clk_enable, 255 .enable = plla_clk_enable, 328 .enable = at91_plladiv_clk_enable, 438 .enable = system_clk_enable, 532 .enable = periph_clk_enable, 637 .enable = utmi_clk_enable,
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H A D | clk-master.c | 105 .enable = clk_master_enable, 181 .enable = clk_master_enable, 325 .enable = clk_sama7g5_master_enable,
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/u-boot/drivers/misc/ |
H A D | gsc.c | 38 GSC_SC_CTRL1_SLEEP_EN = 0, /* 1 = enable sleep */ 43 GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */ 44 GSC_SC_CTRL1_BOOT_CHK = 6, /* 1 = enable alt boot check */ 146 static int gsc_thermal_get_info(struct udevice *dev, u8 *outreg, int *tmax, bool *enable) argument 164 if (enable) 165 *enable = reg & 1; 477 if (cmd && !strcmp(cmd, "enable")) { 546 "[sleep <secs>]|[hwmon]|[wd-disable][thermal [disable|enable [temp]]]\n");
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/u-boot/include/ |
H A D | net.h | 185 int (*set_promisc)(struct udevice *dev, bool enable); 925 * @enable: true to enable binding of bootdevs when binding new Ethernet 928 void eth_set_enable_bootdevs(bool enable); 930 static inline void eth_set_enable_bootdevs(bool enable) {} argument
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/u-boot/drivers/net/ |
H A D | dwc_eth_qos_rockchip.c | 31 void (*set_clock_selection)(struct udevice *dev, bool enable); 252 static void rk3588_set_clock_selection(struct udevice *dev, bool enable) argument 260 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(data->id) :
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/u-boot/drivers/power/regulator/ |
H A D | bd71837.c | 42 * @enable_reg: register address used to enable/disable regulator 43 * @enablemask: register mask used to enable/disable regulator 159 * We use enable mask 'HW_STATE_CONTROL' to indicate that this regulator 299 static int bd71837_set_enable(struct udevice *dev, bool enable) argument 310 return enable ? 0 : -EINVAL; 312 if (enable)
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/u-boot/drivers/pwm/ |
H A D | pwm-meson.c | 14 * Setting the polarity will disable and re-enable the PWM output. 96 static int meson_pwm_set_enable(struct udevice *dev, uint channel, bool enable); 180 static int meson_pwm_set_enable(struct udevice *dev, uint channeln, bool enable) argument 196 if (enable) {
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/u-boot/board/ge/b1x5v2/ |
H A D | b1x5v2.c | 159 .enable = lcd_enable, 182 .enable = lcd_enable, 205 .enable = lcd_enable,
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/u-boot/drivers/clk/stm32/ |
H A D | clk-stm32mp1.c | 1435 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, argument 1440 if (enable) 1446 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) argument 1448 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); 1451 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, argument 1459 if (enable) 1467 log_err("OSC %x @ %x timeout for enable=%d : 0x%x\n", 1468 mask_rdy, address, enable, readl(address)); 1510 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable) argument 1512 stm32mp1_ls_osc_set(enable, rc 1530 stm32mp1_csi_set(fdt_addr_t rcc, int enable) argument 1536 stm32mp1_hsi_set(fdt_addr_t rcc, int enable) argument [all...] |
/u-boot/drivers/net/octeontx2/ |
H A D | cgx_intf.c | 566 int cgx_intf_set_an_lbk(struct udevice *ethdev, int enable) argument 575 cmd.cmd_args.enable = enable; 583 printf("AN loopback %s for %s\n", enable ? "set" : "clear",
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/u-boot/arch/arm/mach-nexell/include/mach/ |
H A D | display.h | 139 int tp_on; /* transparency color enable */ 143 int enable; member in struct:dp_plane_info
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H A D | mipi_display.h | 161 /* enable auto vertical count mode */ 163 /* enable hsync-end packets in vsync-pulse and v-porch area */ 210 int (*enable)(struct mipi_dsi_device *dsi); member in struct:mipi_panel_ops
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/u-boot/drivers/clk/mtmips/ |
H A D | clk-mt7620.c | 109 .enable = mt7620_clk_enable,
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/u-boot/arch/mips/mach-octeon/ |
H A D | cvmx-helper-agl.c | 135 agl_prtx_ctl.s.enable = 1; 156 * Bringup and enable a RGMII interface. After this call packet
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/u-boot/arch/mips/mach-octeon/include/mach/ |
H A D | cvmx-helper-fdt.h | 57 /** For muxes, the bit(s) to set to enable them */ 384 * Given the bus to a device, enable it. 386 * @param[in] bus i2c bus descriptor to enable or disable 387 * @param enable set to true to enable, false to disable 393 int cvmx_fdt_enable_i2c_bus(const struct cvmx_fdt_i2c_bus_info *bus, bool enable);
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/u-boot/board/tbs/tbs2910/ |
H A D | tbs2910.c | 55 .enable = do_enable_hdmi, 126 /* enable ipu1_di0_clk */
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/u-boot/drivers/clk/exynos/ |
H A D | clk.h | 37 .enable = ccf_clk_enable, \
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/u-boot/drivers/clk/ |
H A D | clk_sandbox.c | 108 .enable = sandbox_clk_enable,
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H A D | ics8n3qv01.c | 203 .enable = ics8n3qv01_enable,
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/u-boot/drivers/clk/imx/ |
H A D | clk-imx6q.c | 31 .enable = ccf_clk_enable,
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/u-boot/drivers/clk/mediatek/ |
H A D | clk-mtk.c | 429 /* enable clock gate */ 440 /* enable scpsys clock off control */ 551 .enable = mtk_apmixedsys_enable, 558 .enable = mtk_clk_mux_enable, 565 .enable = mtk_clk_mux_enable, 572 .enable = mtk_clk_gate_enable,
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/u-boot/arch/arm/mach-imx/imx9/ |
H A D | clock.c | 289 /* Set SPREAD_SPECRUM enable to 0 */ 559 int enable_i2c_clk(unsigned char enable, u32 i2c_num) argument 564 if (enable) { 633 void enable_usboh3_clk(unsigned char enable) argument 635 if (enable) { 820 /* enable clock */ 921 /* enable clock */
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