1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Pin Control driver for SuperH Pin Function Controller. 4 * 5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart 6 * 7 * Copyright (C) 2008 Magnus Damm 8 * Copyright (C) 2009 - 2012 Paul Mundt 9 * Copyright (C) 2017 Marek Vasut 10 */ 11 12#define DRV_NAME "sh-pfc" 13 14#include <dm.h> 15#include <errno.h> 16#include <dm/device_compat.h> 17#include <dm/devres.h> 18#include <dm/pinctrl.h> 19#include <linux/bitops.h> 20#include <linux/bug.h> 21#include <linux/io.h> 22#include <linux/sizes.h> 23 24#include "sh_pfc.h" 25 26enum sh_pfc_model { 27 SH_PFC_R8A7790 = 0, 28 SH_PFC_R8A7791, 29 SH_PFC_R8A7792, 30 SH_PFC_R8A7793, 31 SH_PFC_R8A7794, 32 SH_PFC_R8A7795, 33 SH_PFC_R8A77960, 34 SH_PFC_R8A77961, 35 SH_PFC_R8A774A1, 36 SH_PFC_R8A774B1, 37 SH_PFC_R8A774C0, 38 SH_PFC_R8A774E1, 39 SH_PFC_R8A77965, 40 SH_PFC_R8A77970, 41 SH_PFC_R8A77980, 42 SH_PFC_R8A77990, 43 SH_PFC_R8A77995, 44 SH_PFC_R8A779A0, 45 SH_PFC_R8A779F0, 46 SH_PFC_R8A779G0, 47 SH_PFC_R8A779H0, 48}; 49 50struct sh_pfc_pin_config { 51 u32 type; 52 const char *name; 53}; 54 55struct sh_pfc_pinctrl { 56 struct sh_pfc *pfc; 57 58 struct sh_pfc_pin_config *configs; 59}; 60 61struct sh_pfc_pin_range { 62 u16 start; 63 u16 end; 64}; 65 66struct sh_pfc_pinctrl_priv { 67 struct sh_pfc pfc; 68 struct sh_pfc_pinctrl pmx; 69}; 70 71int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) 72{ 73 unsigned int offset; 74 unsigned int i; 75 76 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { 77 const struct sh_pfc_pin_range *range = &pfc->ranges[i]; 78 79 if (pin <= range->end) 80 return pin >= range->start 81 ? offset + pin - range->start : -1; 82 83 offset += range->end - range->start + 1; 84 } 85 86 return -EINVAL; 87} 88 89static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) 90{ 91 if (enum_id < r->begin) 92 return 0; 93 94 if (enum_id > r->end) 95 return 0; 96 97 return 1; 98} 99 100u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) 101{ 102 switch (reg_width) { 103 case 8: 104 return readb(mapped_reg); 105 case 16: 106 return readw(mapped_reg); 107 case 32: 108 return readl(mapped_reg); 109 } 110 111 BUG(); 112 return 0; 113} 114 115void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, 116 u32 data) 117{ 118 switch (reg_width) { 119 case 8: 120 writeb(data, mapped_reg); 121 return; 122 case 16: 123 writew(data, mapped_reg); 124 return; 125 case 32: 126 writel(data, mapped_reg); 127 return; 128 } 129 130 BUG(); 131} 132 133u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) 134{ 135 return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32); 136} 137 138static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data) 139{ 140 u32 unlock; 141 142 if (!pfc->info->unlock_reg) 143 return; 144 145 if (pfc->info->unlock_reg >= 0x80000000UL) 146 unlock = pfc->info->unlock_reg; 147 else 148 /* unlock_reg is a mask */ 149 unlock = reg & ~pfc->info->unlock_reg; 150 151 sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)unlock, 32, ~data); 152} 153 154void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) 155{ 156 sh_pfc_unlock_reg(pfc, reg, data); 157 sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data); 158} 159 160static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, 161 const struct pinmux_cfg_reg *crp, 162 unsigned int in_pos, 163 void __iomem **mapped_regp, u32 *maskp, 164 unsigned int *posp) 165{ 166 unsigned int k; 167 168 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg; 169 170 if (crp->field_width) { 171 *maskp = (1 << crp->field_width) - 1; 172 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); 173 } else { 174 *maskp = (1 << crp->var_field_width[in_pos]) - 1; 175 *posp = crp->reg_width; 176 for (k = 0; k <= in_pos; k++) 177 *posp -= abs(crp->var_field_width[k]); 178 } 179} 180 181static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 182 const struct pinmux_cfg_reg *crp, 183 unsigned int field, u32 value) 184{ 185 void __iomem *mapped_reg; 186 unsigned int pos; 187 u32 mask, data; 188 189 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); 190 191 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " 192 "r_width = %u, f_width = %u\n", 193 crp->reg, value, field, crp->reg_width, crp->field_width); 194 195 mask = ~(mask << pos); 196 value = value << pos; 197 198 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); 199 data &= mask; 200 data |= value; 201 202 sh_pfc_unlock_reg(pfc, crp->reg, data); 203 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); 204} 205 206static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, 207 const struct pinmux_cfg_reg **crp, 208 unsigned int *fieldp, u32 *valuep) 209{ 210 unsigned int k = 0; 211 212 while (1) { 213 const struct pinmux_cfg_reg *config_reg = 214 pfc->info->cfg_regs + k; 215 unsigned int r_width = config_reg->reg_width; 216 unsigned int f_width = config_reg->field_width; 217 unsigned int curr_width; 218 unsigned int bit_pos; 219 unsigned int pos = 0; 220 unsigned int m = 0; 221 222 if (!r_width) 223 break; 224 225 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width, m++) { 226 u32 ncomb; 227 u32 n; 228 229 if (f_width) { 230 curr_width = f_width; 231 } else { 232 curr_width = abs(config_reg->var_field_width[m]); 233 if (config_reg->var_field_width[m] < 0) 234 continue; 235 } 236 237 ncomb = 1 << curr_width; 238 for (n = 0; n < ncomb; n++) { 239 if (config_reg->enum_ids[pos + n] == enum_id) { 240 *crp = config_reg; 241 *fieldp = m; 242 *valuep = n; 243 return 0; 244 } 245 } 246 pos += ncomb; 247 } 248 k++; 249 } 250 251 return -EINVAL; 252} 253 254static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, 255 u16 *enum_idp) 256{ 257 const u16 *data = pfc->info->pinmux_data; 258 unsigned int k; 259 260 if (pos) { 261 *enum_idp = data[pos + 1]; 262 return pos + 1; 263 } 264 265 for (k = 0; k < pfc->info->pinmux_data_size; k++) { 266 if (data[k] == mark) { 267 *enum_idp = data[k + 1]; 268 return k + 1; 269 } 270 } 271 272 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", 273 mark); 274 return -EINVAL; 275} 276 277int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 278{ 279 const struct pinmux_range *range; 280 int pos = 0; 281 282 switch (pinmux_type) { 283 case PINMUX_TYPE_GPIO: 284 case PINMUX_TYPE_FUNCTION: 285 range = NULL; 286 break; 287 288 case PINMUX_TYPE_OUTPUT: 289 range = &pfc->info->output; 290 break; 291 292 case PINMUX_TYPE_INPUT: 293 range = &pfc->info->input; 294 break; 295 296 default: 297 return -EINVAL; 298 } 299 300 /* Iterate over all the configuration fields we need to update. */ 301 while (1) { 302 const struct pinmux_cfg_reg *cr; 303 unsigned int field; 304 u16 enum_id; 305 u32 value; 306 int in_range; 307 int ret; 308 309 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); 310 if (pos < 0) 311 return pos; 312 313 if (!enum_id) 314 break; 315 316 /* Check if the configuration field selects a function. If it 317 * doesn't, skip the field if it's not applicable to the 318 * requested pinmux type. 319 */ 320 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); 321 if (!in_range) { 322 if (pinmux_type == PINMUX_TYPE_FUNCTION) { 323 /* Functions are allowed to modify all 324 * fields. 325 */ 326 in_range = 1; 327 } else if (pinmux_type != PINMUX_TYPE_GPIO) { 328 /* Input/output types can only modify fields 329 * that correspond to their respective ranges. 330 */ 331 in_range = sh_pfc_enum_in_range(enum_id, range); 332 333 /* 334 * special case pass through for fixed 335 * input-only or output-only pins without 336 * function enum register association. 337 */ 338 if (in_range && enum_id == range->force) 339 continue; 340 } 341 /* GPIOs are only allowed to modify function fields. */ 342 } 343 344 if (!in_range) 345 continue; 346 347 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); 348 if (ret < 0) 349 return ret; 350 351 sh_pfc_write_config_reg(pfc, cr, field, value); 352 } 353 354 return 0; 355} 356 357const struct pinmux_bias_reg * 358rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, 359 unsigned int *bit) 360{ 361 unsigned int i, j; 362 363 for (i = 0; info->bias_regs[i].puen || info->bias_regs[i].pud; i++) { 364 for (j = 0; j < ARRAY_SIZE(info->bias_regs[i].pins); j++) { 365 if (info->bias_regs[i].pins[j] == pin) { 366 *bit = j; 367 return &info->bias_regs[i]; 368 } 369 } 370 } 371 372 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); 373 374 return NULL; 375} 376 377unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) 378{ 379 const struct pinmux_bias_reg *reg; 380 unsigned int bit; 381 382 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); 383 if (!reg) 384 return PIN_CONFIG_BIAS_DISABLE; 385 386 if (reg->puen) { 387 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) 388 return PIN_CONFIG_BIAS_DISABLE; 389 else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit))) 390 return PIN_CONFIG_BIAS_PULL_UP; 391 else 392 return PIN_CONFIG_BIAS_PULL_DOWN; 393 } else { 394 if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) 395 return PIN_CONFIG_BIAS_PULL_DOWN; 396 else 397 return PIN_CONFIG_BIAS_DISABLE; 398 } 399} 400 401void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 402 unsigned int bias) 403{ 404 const struct pinmux_bias_reg *reg; 405 u32 enable, updown; 406 unsigned int bit; 407 408 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); 409 if (!reg) 410 return; 411 412 if (reg->puen) { 413 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); 414 if (bias != PIN_CONFIG_BIAS_DISABLE) { 415 enable |= BIT(bit); 416 417 if (reg->pud) { 418 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 419 if (bias == PIN_CONFIG_BIAS_PULL_UP) 420 updown |= BIT(bit); 421 422 sh_pfc_write(pfc, reg->pud, updown); 423 } 424 } 425 sh_pfc_write(pfc, reg->puen, enable); 426 } else { 427 enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 428 if (bias == PIN_CONFIG_BIAS_PULL_DOWN) 429 enable |= BIT(bit); 430 431 sh_pfc_write(pfc, reg->pud, enable); 432 } 433} 434 435static int sh_pfc_init_ranges(struct sh_pfc *pfc) 436{ 437 struct sh_pfc_pin_range *range; 438 unsigned int nr_ranges; 439 unsigned int i; 440 441 if (pfc->info->pins[0].pin == (u16)-1) { 442 /* Pin number -1 denotes that the SoC doesn't report pin numbers 443 * in its pin arrays yet. Consider the pin numbers range as 444 * continuous and allocate a single range. 445 */ 446 pfc->nr_ranges = 1; 447 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL); 448 if (pfc->ranges == NULL) 449 return -ENOMEM; 450 451 pfc->ranges->start = 0; 452 pfc->ranges->end = pfc->info->nr_pins - 1; 453 pfc->nr_gpio_pins = pfc->info->nr_pins; 454 455 return 0; 456 } 457 458 /* Count, allocate and fill the ranges. The PFC SoC data pins array must 459 * be sorted by pin numbers, and pins without a GPIO port must come 460 * last. 461 */ 462 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { 463 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) 464 nr_ranges++; 465 } 466 467 pfc->nr_ranges = nr_ranges; 468 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL); 469 if (pfc->ranges == NULL) 470 return -ENOMEM; 471 472 range = pfc->ranges; 473 range->start = pfc->info->pins[0].pin; 474 475 for (i = 1; i < pfc->info->nr_pins; ++i) { 476 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) 477 continue; 478 479 range->end = pfc->info->pins[i-1].pin; 480 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 481 pfc->nr_gpio_pins = range->end + 1; 482 483 range++; 484 range->start = pfc->info->pins[i].pin; 485 } 486 487 range->end = pfc->info->pins[i-1].pin; 488 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 489 pfc->nr_gpio_pins = range->end + 1; 490 491 return 0; 492} 493 494static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev) 495{ 496 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 497 498 return priv->pfc.info->nr_pins; 499} 500 501static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev, 502 unsigned selector) 503{ 504 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 505 506 return priv->pfc.info->pins[selector].name; 507} 508 509static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev) 510{ 511 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 512 513 return priv->pfc.info->nr_groups; 514} 515 516static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev, 517 unsigned selector) 518{ 519 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 520 521 return priv->pfc.info->groups[selector].name; 522} 523 524static int sh_pfc_pinctrl_get_pin_muxing(struct udevice *dev, 525 unsigned int selector, 526 char *buf, int size) 527{ 528 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 529 struct sh_pfc_pinctrl *pmx = &priv->pmx; 530 struct sh_pfc *pfc = &priv->pfc; 531 struct sh_pfc_pin_config *cfg; 532 const struct sh_pfc_pin *pin; 533 int idx; 534 535 pin = &priv->pfc.info->pins[selector]; 536 if (!pin) { 537 snprintf(buf, size, "Unknown"); 538 return -EINVAL; 539 } 540 541 idx = sh_pfc_get_pin_index(pfc, pin->pin); 542 cfg = &pmx->configs[idx]; 543 snprintf(buf, size, "%s", cfg->name); 544 545 return 0; 546} 547 548static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev) 549{ 550 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 551 552 return priv->pfc.info->nr_functions; 553} 554 555static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev, 556 unsigned selector) 557{ 558 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 559 560 return priv->pfc.info->functions[selector].name; 561} 562 563static int sh_pfc_gpio_request_enable(struct udevice *dev, 564 unsigned pin_selector) 565{ 566 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 567 struct sh_pfc_pinctrl *pmx = &priv->pmx; 568 struct sh_pfc *pfc = &priv->pfc; 569 struct sh_pfc_pin_config *cfg; 570 const struct sh_pfc_pin *pin = NULL; 571 int i, ret, idx; 572 573 for (i = 0; i < pfc->info->nr_pins; i++) { 574 if (priv->pfc.info->pins[i].pin != pin_selector) 575 continue; 576 577 pin = &priv->pfc.info->pins[i]; 578 break; 579 } 580 581 if (!pin) 582 return -EINVAL; 583 584 idx = sh_pfc_get_pin_index(pfc, pin->pin); 585 cfg = &pmx->configs[idx]; 586 587 if (cfg->type != PINMUX_TYPE_NONE) { 588 if (!strcmp(cfg->name, pin->name)) 589 return 0; 590 591 dev_err(pfc->dev, "Pin already used as %s\n", 592 cfg->name); 593 return -EBUSY; 594 } 595 596 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); 597 if (ret) 598 return ret; 599 600 cfg->type = PINMUX_TYPE_GPIO; 601 cfg->name = "gpio"; 602 603 return 0; 604} 605 606static int sh_pfc_gpio_disable_free(struct udevice *dev, 607 unsigned pin_selector) 608{ 609 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 610 struct sh_pfc_pinctrl *pmx = &priv->pmx; 611 struct sh_pfc *pfc = &priv->pfc; 612 struct sh_pfc_pin_config *cfg; 613 const struct sh_pfc_pin *pin = NULL; 614 int i, idx; 615 616 for (i = 0; i < pfc->info->nr_pins; i++) { 617 if (priv->pfc.info->pins[i].pin != pin_selector) 618 continue; 619 620 pin = &priv->pfc.info->pins[i]; 621 break; 622 } 623 624 if (!pin) 625 return -EINVAL; 626 627 idx = sh_pfc_get_pin_index(pfc, pin->pin); 628 cfg = &pmx->configs[idx]; 629 630 cfg->type = PINMUX_TYPE_NONE; 631 cfg->name = "none"; 632 633 return 0; 634} 635 636static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector, 637 unsigned func_selector) 638{ 639 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 640 struct sh_pfc_pinctrl *pmx = &priv->pmx; 641 struct sh_pfc *pfc = &priv->pfc; 642 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector]; 643 int idx = sh_pfc_get_pin_index(pfc, pin->pin); 644 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 645 int ret; 646 647 if (cfg->type != PINMUX_TYPE_NONE) { 648 if (!strcmp(cfg->name, pin->name)) 649 return 0; 650 651 dev_err(pfc->dev, "Pin already used as %s\n", 652 cfg->name); 653 return -EBUSY; 654 } 655 656 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION); 657 if (ret) 658 return ret; 659 660 cfg->type = PINMUX_TYPE_FUNCTION; 661 cfg->name = "function"; 662 663 return 0; 664} 665 666static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector, 667 unsigned func_selector) 668{ 669 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 670 struct sh_pfc_pinctrl *pmx = &priv->pmx; 671 struct sh_pfc *pfc = &priv->pfc; 672 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector]; 673 bool grp_pins_configured = true; 674 struct sh_pfc_pin_config *cfg; 675 unsigned int i; 676 int ret = 0; 677 int idx; 678 679 for (i = 0; i < grp->nr_pins; ++i) { 680 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 681 cfg = &pmx->configs[idx]; 682 683 if (cfg->type != PINMUX_TYPE_NONE) { 684 if (!strcmp(cfg->name, grp->name)) 685 continue; 686 687 dev_err(pfc->dev, "Pin already used as %s\n", 688 cfg->name); 689 ret = -EBUSY; 690 goto done; 691 } else { 692 grp_pins_configured = false; 693 } 694 } 695 696 if (grp_pins_configured) 697 return 0; 698 699 for (i = 0; i < grp->nr_pins; ++i) { 700 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); 701 if (ret < 0) 702 break; 703 704 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 705 cfg = &pmx->configs[idx]; 706 cfg->type = PINMUX_TYPE_FUNCTION; 707 cfg->name = priv->pfc.info->groups[group_selector].name; 708 } 709 710done: 711 return ret; 712} 713#if CONFIG_IS_ENABLED(PINCONF) 714static const struct pinconf_param sh_pfc_pinconf_params[] = { 715 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 716 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 717 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 718 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 719 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 }, 720}; 721 722static void __iomem * 723sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin, 724 unsigned int *offset, unsigned int *size) 725{ 726 const struct pinmux_drive_reg_field *field; 727 const struct pinmux_drive_reg *reg; 728 unsigned int i; 729 730 for (reg = pfc->info->drive_regs; reg->reg; ++reg) { 731 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { 732 field = ®->fields[i]; 733 734 if (field->size && field->pin == pin) { 735 *offset = field->offset; 736 *size = field->size; 737 738 return (void __iomem *)(uintptr_t)reg->reg; 739 } 740 } 741 } 742 743 return NULL; 744} 745 746static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, 747 unsigned int pin, u16 strength) 748{ 749 unsigned int offset; 750 unsigned int size; 751 unsigned int step; 752 void __iomem *reg; 753 u32 val; 754 755 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 756 if (!reg) 757 return -EINVAL; 758 759 step = size == 2 ? 6 : 3; 760 761 if (strength < step || strength > 24) 762 return -EINVAL; 763 764 /* Convert the value from mA based on a full drive strength value of 765 * 24mA. We can make the full value configurable later if needed. 766 */ 767 strength = strength / step - 1; 768 769 val = sh_pfc_read_raw_reg(reg, 32); 770 val &= ~GENMASK(offset + 4 - 1, offset); 771 val |= strength << offset; 772 773 sh_pfc_unlock_reg(pfc, (uintptr_t)reg, val); 774 sh_pfc_write_raw_reg(reg, 32, val); 775 776 return 0; 777} 778 779/* Check whether the requested parameter is supported for a pin. */ 780static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, 781 unsigned int param) 782{ 783 int idx = sh_pfc_get_pin_index(pfc, _pin); 784 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 785 786 switch (param) { 787 case PIN_CONFIG_BIAS_DISABLE: 788 return pin->configs & 789 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN); 790 791 case PIN_CONFIG_BIAS_PULL_UP: 792 return pin->configs & SH_PFC_PIN_CFG_PULL_UP; 793 794 case PIN_CONFIG_BIAS_PULL_DOWN: 795 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; 796 797 case PIN_CONFIG_DRIVE_STRENGTH: 798 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; 799 800 case PIN_CONFIG_POWER_SOURCE: 801 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; 802 803 default: 804 return false; 805 } 806} 807 808static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, 809 unsigned int param, unsigned int arg) 810{ 811 struct sh_pfc *pfc = pmx->pfc; 812 void __iomem *pocctrl; 813 u32 addr, val; 814 int bit, ret; 815 int idx = sh_pfc_get_pin_index(pfc, _pin); 816 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 817 unsigned int mode, hi, lo; 818 819 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 820 return -ENOTSUPP; 821 822 switch (param) { 823 case PIN_CONFIG_BIAS_PULL_UP: 824 case PIN_CONFIG_BIAS_PULL_DOWN: 825 case PIN_CONFIG_BIAS_DISABLE: 826 if (!pfc->info->ops || !pfc->info->ops->set_bias) 827 return -ENOTSUPP; 828 829 pfc->info->ops->set_bias(pfc, _pin, param); 830 831 break; 832 833 case PIN_CONFIG_DRIVE_STRENGTH: 834 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg); 835 if (ret < 0) 836 return ret; 837 838 break; 839 840 case PIN_CONFIG_POWER_SOURCE: 841 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 842 return -ENOTSUPP; 843 844 bit = pfc->info->ops->pin_to_pocctrl(_pin, &addr); 845 if (bit < 0) { 846 printf("invalid pin %#x", _pin); 847 return bit; 848 } 849 850 if (arg != 1800 && arg != 2500 && arg != 3300) 851 return -EINVAL; 852 853 pocctrl = (void __iomem *)(uintptr_t)addr; 854 855 mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; 856 lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500; 857 hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500; 858 859 val = sh_pfc_read_raw_reg(pocctrl, 32); 860 if (arg == hi) 861 val |= BIT(bit); 862 else 863 val &= ~BIT(bit); 864 865 sh_pfc_unlock_reg(pfc, addr, val); 866 sh_pfc_write_raw_reg(pocctrl, 32, val); 867 868 break; 869 870 default: 871 return -ENOTSUPP; 872 } 873 874 return 0; 875} 876 877static int sh_pfc_pinconf_pin_set(struct udevice *dev, 878 unsigned int pin_selector, 879 unsigned int param, unsigned int arg) 880{ 881 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 882 struct sh_pfc_pinctrl *pmx = &priv->pmx; 883 struct sh_pfc *pfc = &priv->pfc; 884 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector]; 885 886 sh_pfc_pinconf_set(pmx, pin->pin, param, arg); 887 888 return 0; 889} 890 891static int sh_pfc_pinconf_group_set(struct udevice *dev, 892 unsigned int group_selector, 893 unsigned int param, unsigned int arg) 894{ 895 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 896 struct sh_pfc_pinctrl *pmx = &priv->pmx; 897 struct sh_pfc *pfc = &priv->pfc; 898 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector]; 899 unsigned int i; 900 901 for (i = 0; i < grp->nr_pins; i++) 902 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg); 903 904 return 0; 905} 906#endif 907 908static struct pinctrl_ops sh_pfc_pinctrl_ops = { 909 .get_pins_count = sh_pfc_pinctrl_get_pins_count, 910 .get_pin_name = sh_pfc_pinctrl_get_pin_name, 911 .get_groups_count = sh_pfc_pinctrl_get_groups_count, 912 .get_group_name = sh_pfc_pinctrl_get_group_name, 913 .get_pin_muxing = sh_pfc_pinctrl_get_pin_muxing, 914 .get_functions_count = sh_pfc_pinctrl_get_functions_count, 915 .get_function_name = sh_pfc_pinctrl_get_function_name, 916 917#if CONFIG_IS_ENABLED(PINCONF) 918 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params), 919 .pinconf_params = sh_pfc_pinconf_params, 920 .pinconf_set = sh_pfc_pinconf_pin_set, 921 .pinconf_group_set = sh_pfc_pinconf_group_set, 922#endif 923 .pinmux_set = sh_pfc_pinctrl_pin_set, 924 .pinmux_group_set = sh_pfc_pinctrl_group_set, 925 .set_state = pinctrl_generic_set_state, 926 927 .gpio_request_enable = sh_pfc_gpio_request_enable, 928 .gpio_disable_free = sh_pfc_gpio_disable_free, 929}; 930 931static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 932{ 933 unsigned int i; 934 935 /* Allocate and initialize the pins and configs arrays. */ 936 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins, 937 GFP_KERNEL); 938 if (unlikely(!pmx->configs)) 939 return -ENOMEM; 940 941 for (i = 0; i < pfc->info->nr_pins; ++i) { 942 struct sh_pfc_pin_config *cfg = &pmx->configs[i]; 943 cfg->type = PINMUX_TYPE_NONE; 944 cfg->name = "none"; 945 } 946 947 return 0; 948} 949 950 951static int sh_pfc_pinctrl_probe(struct udevice *dev) 952{ 953 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 954 enum sh_pfc_model model = dev_get_driver_data(dev); 955 fdt_addr_t base; 956 957 base = dev_read_addr(dev); 958 if (base == FDT_ADDR_T_NONE) 959 return -EINVAL; 960 961 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K); 962 if (!priv->pfc.regs) 963 return -ENOMEM; 964 965#ifdef CONFIG_PINCTRL_PFC_R8A7790 966 if (model == SH_PFC_R8A7790) 967 priv->pfc.info = &r8a7790_pinmux_info; 968#endif 969#ifdef CONFIG_PINCTRL_PFC_R8A7791 970 if (model == SH_PFC_R8A7791) 971 priv->pfc.info = &r8a7791_pinmux_info; 972#endif 973#ifdef CONFIG_PINCTRL_PFC_R8A7792 974 if (model == SH_PFC_R8A7792) 975 priv->pfc.info = &r8a7792_pinmux_info; 976#endif 977#ifdef CONFIG_PINCTRL_PFC_R8A7793 978 if (model == SH_PFC_R8A7793) 979 priv->pfc.info = &r8a7793_pinmux_info; 980#endif 981#ifdef CONFIG_PINCTRL_PFC_R8A7794 982 if (model == SH_PFC_R8A7794) 983 priv->pfc.info = &r8a7794_pinmux_info; 984#endif 985#ifdef CONFIG_PINCTRL_PFC_R8A77951 986 if (model == SH_PFC_R8A7795) 987 priv->pfc.info = &r8a77951_pinmux_info; 988#endif 989#ifdef CONFIG_PINCTRL_PFC_R8A77960 990 if (model == SH_PFC_R8A77960) 991 priv->pfc.info = &r8a77960_pinmux_info; 992#endif 993#ifdef CONFIG_PINCTRL_PFC_R8A77961 994 if (model == SH_PFC_R8A77961) 995 priv->pfc.info = &r8a77961_pinmux_info; 996#endif 997#ifdef CONFIG_PINCTRL_PFC_R8A774A1 998 if (model == SH_PFC_R8A774A1) 999 priv->pfc.info = &r8a774a1_pinmux_info; 1000#endif 1001#ifdef CONFIG_PINCTRL_PFC_R8A774B1 1002 if (model == SH_PFC_R8A774B1) 1003 priv->pfc.info = &r8a774b1_pinmux_info; 1004#endif 1005#ifdef CONFIG_PINCTRL_PFC_R8A774C0 1006 if (model == SH_PFC_R8A774C0) 1007 priv->pfc.info = &r8a774c0_pinmux_info; 1008#endif 1009#ifdef CONFIG_PINCTRL_PFC_R8A774E1 1010 if (model == SH_PFC_R8A774E1) 1011 priv->pfc.info = &r8a774e1_pinmux_info; 1012#endif 1013#ifdef CONFIG_PINCTRL_PFC_R8A77965 1014 if (model == SH_PFC_R8A77965) 1015 priv->pfc.info = &r8a77965_pinmux_info; 1016#endif 1017#ifdef CONFIG_PINCTRL_PFC_R8A77970 1018 if (model == SH_PFC_R8A77970) 1019 priv->pfc.info = &r8a77970_pinmux_info; 1020#endif 1021#ifdef CONFIG_PINCTRL_PFC_R8A77980 1022 if (model == SH_PFC_R8A77980) 1023 priv->pfc.info = &r8a77980_pinmux_info; 1024#endif 1025#ifdef CONFIG_PINCTRL_PFC_R8A77990 1026 if (model == SH_PFC_R8A77990) 1027 priv->pfc.info = &r8a77990_pinmux_info; 1028#endif 1029#ifdef CONFIG_PINCTRL_PFC_R8A77995 1030 if (model == SH_PFC_R8A77995) 1031 priv->pfc.info = &r8a77995_pinmux_info; 1032#endif 1033#ifdef CONFIG_PINCTRL_PFC_R8A779A0 1034 if (model == SH_PFC_R8A779A0) 1035 priv->pfc.info = &r8a779a0_pinmux_info; 1036#endif 1037#ifdef CONFIG_PINCTRL_PFC_R8A779F0 1038 if (model == SH_PFC_R8A779F0) 1039 priv->pfc.info = &r8a779f0_pinmux_info; 1040#endif 1041#ifdef CONFIG_PINCTRL_PFC_R8A779G0 1042 if (model == SH_PFC_R8A779G0) 1043 priv->pfc.info = &r8a779g0_pinmux_info; 1044#endif 1045#ifdef CONFIG_PINCTRL_PFC_R8A779H0 1046 if (model == SH_PFC_R8A779H0) 1047 priv->pfc.info = &r8a779h0_pinmux_info; 1048#endif 1049 1050 priv->pmx.pfc = &priv->pfc; 1051 sh_pfc_init_ranges(&priv->pfc); 1052 sh_pfc_map_pins(&priv->pfc, &priv->pmx); 1053 1054 return 0; 1055} 1056 1057static const struct udevice_id sh_pfc_pinctrl_ids[] = { 1058#ifdef CONFIG_PINCTRL_PFC_R8A7790 1059 { 1060 .compatible = "renesas,pfc-r8a7790", 1061 .data = SH_PFC_R8A7790, 1062 }, 1063#endif 1064#ifdef CONFIG_PINCTRL_PFC_R8A7791 1065 { 1066 .compatible = "renesas,pfc-r8a7791", 1067 .data = SH_PFC_R8A7791, 1068 }, 1069#endif 1070#ifdef CONFIG_PINCTRL_PFC_R8A7792 1071 { 1072 .compatible = "renesas,pfc-r8a7792", 1073 .data = SH_PFC_R8A7792, 1074 }, 1075#endif 1076#ifdef CONFIG_PINCTRL_PFC_R8A7793 1077 { 1078 .compatible = "renesas,pfc-r8a7793", 1079 .data = SH_PFC_R8A7793, 1080 }, 1081#endif 1082#ifdef CONFIG_PINCTRL_PFC_R8A7794 1083 { 1084 .compatible = "renesas,pfc-r8a7794", 1085 .data = SH_PFC_R8A7794, 1086 }, 1087#endif 1088#ifdef CONFIG_PINCTRL_PFC_R8A77951 1089 { 1090 .compatible = "renesas,pfc-r8a7795", 1091 .data = SH_PFC_R8A7795, 1092 }, 1093#endif 1094#ifdef CONFIG_PINCTRL_PFC_R8A77960 1095 { 1096 .compatible = "renesas,pfc-r8a7796", 1097 .data = SH_PFC_R8A77960, 1098 }, 1099#endif 1100#ifdef CONFIG_PINCTRL_PFC_R8A77961 1101 { 1102 .compatible = "renesas,pfc-r8a77961", 1103 .data = SH_PFC_R8A77961, 1104 }, 1105#endif 1106#ifdef CONFIG_PINCTRL_PFC_R8A774A1 1107 { 1108 .compatible = "renesas,pfc-r8a774a1", 1109 .data = SH_PFC_R8A774A1, 1110 }, 1111#endif 1112#ifdef CONFIG_PINCTRL_PFC_R8A774B1 1113 { 1114 .compatible = "renesas,pfc-r8a774b1", 1115 .data = SH_PFC_R8A774B1, 1116 }, 1117#endif 1118#ifdef CONFIG_PINCTRL_PFC_R8A774C0 1119 { 1120 .compatible = "renesas,pfc-r8a774c0", 1121 .data = SH_PFC_R8A774C0, 1122 }, 1123#endif 1124#ifdef CONFIG_PINCTRL_PFC_R8A774E1 1125 { 1126 .compatible = "renesas,pfc-r8a774e1", 1127 .data = SH_PFC_R8A774E1, 1128 }, 1129#endif 1130#ifdef CONFIG_PINCTRL_PFC_R8A77965 1131 { 1132 .compatible = "renesas,pfc-r8a77965", 1133 .data = SH_PFC_R8A77965, 1134 }, 1135#endif 1136#ifdef CONFIG_PINCTRL_PFC_R8A77970 1137 { 1138 .compatible = "renesas,pfc-r8a77970", 1139 .data = SH_PFC_R8A77970, 1140 }, 1141#endif 1142#ifdef CONFIG_PINCTRL_PFC_R8A77980 1143 { 1144 .compatible = "renesas,pfc-r8a77980", 1145 .data = SH_PFC_R8A77980, 1146 }, 1147#endif 1148#ifdef CONFIG_PINCTRL_PFC_R8A77990 1149 { 1150 .compatible = "renesas,pfc-r8a77990", 1151 .data = SH_PFC_R8A77990, 1152 }, 1153#endif 1154#ifdef CONFIG_PINCTRL_PFC_R8A77995 1155 { 1156 .compatible = "renesas,pfc-r8a77995", 1157 .data = SH_PFC_R8A77995, 1158 }, 1159#endif 1160#ifdef CONFIG_PINCTRL_PFC_R8A779A0 1161 { 1162 .compatible = "renesas,pfc-r8a779a0", 1163 .data = SH_PFC_R8A779A0, 1164 }, 1165#endif 1166#ifdef CONFIG_PINCTRL_PFC_R8A779F0 1167 { 1168 .compatible = "renesas,pfc-r8a779f0", 1169 .data = SH_PFC_R8A779F0, 1170 }, 1171#endif 1172#ifdef CONFIG_PINCTRL_PFC_R8A779G0 1173 { 1174 .compatible = "renesas,pfc-r8a779g0", 1175 .data = SH_PFC_R8A779G0, 1176 }, 1177#endif 1178#ifdef CONFIG_PINCTRL_PFC_R8A779H0 1179 { 1180 .compatible = "renesas,pfc-r8a779h0", 1181 .data = SH_PFC_R8A779H0, 1182 }, 1183#endif 1184 1185 { }, 1186}; 1187 1188U_BOOT_DRIVER(pinctrl_sh_pfc) = { 1189 .name = "sh_pfc_pinctrl", 1190 .id = UCLASS_PINCTRL, 1191 .of_match = sh_pfc_pinctrl_ids, 1192 .priv_auto = sizeof(struct sh_pfc_pinctrl_priv), 1193 .ops = &sh_pfc_pinctrl_ops, 1194 .probe = sh_pfc_pinctrl_probe, 1195}; 1196