1/* SPDX-License-Identifier: GPL-2.0+ 2 * 3 * Copyright (C) 2016 Nexell Co., Ltd. 4 * 5 * Author: junghyun, kim <jhkim@nexell.co.kr> 6 */ 7 8#ifndef _NX__DISPLAY_H_ 9#define _NX__DISPLAY_H_ 10 11#define DP_PLANS_NUM 3 12 13/* the display output format. */ 14#define DPC_FORMAT_RGB555 0 /* RGB555 Format */ 15#define DPC_FORMAT_RGB565 1 /* RGB565 Format */ 16#define DPC_FORMAT_RGB666 2 /* RGB666 Format */ 17#define DPC_FORMAT_RGB888 3 /* RGB888 Format */ 18#define DPC_FORMAT_MRGB555A 4 /* MRGB555A Format */ 19#define DPC_FORMAT_MRGB555B 5 /* MRGB555B Format */ 20#define DPC_FORMAT_MRGB565 6 /* MRGB565 Format */ 21#define DPC_FORMAT_MRGB666 7 /* MRGB666 Format */ 22#define DPC_FORMAT_MRGB888A 8 /* MRGB888A Format */ 23#define DPC_FORMAT_MRGB888B 9 /* MRGB888B Format */ 24#define DPC_FORMAT_CCIR656 10 /* ITU-R BT.656 / 601(8-bit) */ 25#define DPC_FORMAT_CCIR601A 12 /* ITU-R BT.601A */ 26#define DPC_FORMAT_CCIR601B 13 /* ITU-R BT.601B */ 27#define DPC_FORMAT_4096COLOR 1 /* 4096 Color Format */ 28#define DPC_FORMAT_16GRAY 3 /* 16 Level Gray Format */ 29 30/* layer pixel format. */ 31#define MLC_RGBFMT_R5G6B5 0x44320000 /* {R5,G6,B5 }. */ 32#define MLC_RGBFMT_B5G6R5 0xC4320000 /* {B5,G6,R5 }. */ 33#define MLC_RGBFMT_X1R5G5B5 0x43420000 /* {X1,R5,G5,B5}. */ 34#define MLC_RGBFMT_X1B5G5R5 0xC3420000 /* {X1,B5,G5,R5}. */ 35#define MLC_RGBFMT_X4R4G4B4 0x42110000 /* {X4,R4,G4,B4}. */ 36#define MLC_RGBFMT_X4B4G4R4 0xC2110000 /* {X4,B4,G4,R4}. */ 37#define MLC_RGBFMT_X8R3G3B2 0x41200000 /* {X8,R3,G3,B2}. */ 38#define MLC_RGBFMT_X8B3G3R2 0xC1200000 /* {X8,B3,G3,R2}. */ 39#define MLC_RGBFMT_A1R5G5B5 0x33420000 /* {A1,R5,G5,B5}. */ 40#define MLC_RGBFMT_A1B5G5R5 0xB3420000 /* {A1,B5,G5,R5}. */ 41#define MLC_RGBFMT_A4R4G4B4 0x22110000 /* {A4,R4,G4,B4}. */ 42#define MLC_RGBFMT_A4B4G4R4 0xA2110000 /* {A4,B4,G4,R4}. */ 43#define MLC_RGBFMT_A8R3G3B2 0x11200000 /* {A8,R3,G3,B2}. */ 44#define MLC_RGBFMT_A8B3G3R2 0x91200000 /* {A8,B3,G3,R2}. */ 45#define MLC_RGBFMT_R8G8B8 0x46530000 /* {R8,G8,B8 }. */ 46#define MLC_RGBFMT_B8G8R8 0xC6530000 /* {B8,G8,R8 }. */ 47#define MLC_RGBFMT_X8R8G8B8 0x46530000 /* {X8,R8,G8,B8}. */ 48#define MLC_RGBFMT_X8B8G8R8 0xC6530000 /* {X8,B8,G8,R8}. */ 49#define MLC_RGBFMT_A8R8G8B8 0x06530000 /* {A8,R8,G8,B8}. */ 50#define MLC_RGBFMT_A8B8G8R8 0x86530000 /* {A8,B8,G8,R8}. */ 51 52/* the data output order in case of ITU-R BT.656 / 601. */ 53#define DPC_YCORDER_CBYCRY 0 54#define DPC_YCORDER_CRYCBY 1 55#define DPC_YCORDER_YCBYCR 2 56#define DPC_YCORDER_YCRYCB 3 57 58/* the PAD output clock. */ 59#define DPC_PADCLKSEL_VCLK 0 /* VCLK */ 60#define DPC_PADCLKSEL_VCLK2 1 /* VCLK2 */ 61 62/* display sync info for DPC */ 63struct dp_sync_info { 64 int interlace; 65 int h_active_len; 66 int h_sync_width; 67 int h_back_porch; 68 int h_front_porch; 69 int h_sync_invert; /* default active low */ 70 int v_active_len; 71 int v_sync_width; 72 int v_back_porch; 73 int v_front_porch; 74 int v_sync_invert; /* default active low */ 75 int pixel_clock_hz; /* HZ */ 76}; 77 78/* syncgen control (DPC) */ 79#define DP_SYNC_DELAY_RGB_PVD (1 << 0) 80#define DP_SYNC_DELAY_HSYNC_CP1 (1 << 1) 81#define DP_SYNC_DELAY_VSYNC_FRAM (1 << 2) 82#define DP_SYNC_DELAY_DE_CP (1 << 3) 83 84struct dp_ctrl_info { 85 /* clock gen */ 86 int clk_src_lv0; 87 int clk_div_lv0; 88 int clk_src_lv1; 89 int clk_div_lv1; 90 /* scan format */ 91 int interlace; 92 /* syncgen format */ 93 unsigned int out_format; 94 int invert_field; /* 0:normal(Low odd), 1:invert (low even) */ 95 int swap_RB; 96 unsigned int yc_order; /* for CCIR output */ 97 /* extern sync delay */ 98 int delay_mask; /* if 0, set defalut delays */ 99 int d_rgb_pvd; /* delay for RGB/PVD, 0~16, default 0 */ 100 int d_hsync_cp1; /* delay for HSYNC/CP1, 0~63, default 12 */ 101 int d_vsync_fram; /* delay for VSYNC/FRAM, 0~63, default 12 */ 102 int d_de_cp2; /* delay for DE/CP2, 0~63, default 12 */ 103 /* sync offset */ 104 int vs_start_offset; /* start vsync offset, defatult 0 */ 105 int vs_end_offset; /* end vsync offset, default 0 */ 106 int ev_start_offset; /* start even vsync offset, default 0 */ 107 int ev_end_offset; /* end even vsync offset , default 0 */ 108 /* pad clock seletor */ 109 int vck_select; /* 0=vclk0, 1=vclk2 */ 110 int clk_inv_lv0; /* OUTCLKINVn */ 111 int clk_delay_lv0; /* OUTCLKDELAYn */ 112 int clk_inv_lv1; /* OUTCLKINVn */ 113 int clk_delay_lv1; /* OUTCLKDELAYn */ 114 int clk_sel_div1; /* 0=clk1_inv, 1=clk1_div_2_ns */ 115}; 116 117/* multi layer control (MLC) */ 118struct dp_plane_top { 119 int screen_width; 120 int screen_height; 121 int video_prior; /* 0: video>RGBn, 1: RGB0>video>RGB1, 122 * 2: RGB0 > RGB1 > video .. */ 123 int interlace; 124 int plane_num; 125 unsigned int back_color; 126}; 127 128struct dp_plane_info { 129 int layer; 130 unsigned int fb_base; 131 int left; 132 int top; 133 int width; 134 int height; 135 int pixel_byte; 136 unsigned int format; 137 int alpha_on; 138 int alpha_depth; 139 int tp_on; /* transparency color enable */ 140 unsigned int tp_color; 141 unsigned int mem_lock_size; /* memory burst access (4,8,16) */ 142 int video_layer; 143 int enable; 144}; 145 146/* 147 * LCD device dependency struct 148 * RGB, LVDS, MiPi, HDMI 149 */ 150enum { 151 DP_DEVICE_RESCONV = 0, 152 DP_DEVICE_RGBLCD = 1, 153 DP_DEVICE_HDMI = 2, 154 DP_DEVICE_MIPI = 3, 155 DP_DEVICE_LVDS = 4, 156 DP_DEVICE_CVBS = 5, 157 DP_DEVICE_DP0 = 6, 158 DP_DEVICE_DP1 = 7, 159 DP_DEVICE_END, 160}; 161 162enum { 163 DP_CLOCK_RESCONV = 0, 164 DP_CLOCK_LCDIF = 1, 165 DP_CLOCK_MIPI = 2, 166 DP_CLOCK_LVDS = 3, 167 DP_CLOCK_HDMI = 4, 168 DP_CLOCK_END, 169}; 170 171enum dp_lvds_format { 172 DP_LVDS_FORMAT_VESA = 0, 173 DP_LVDS_FORMAT_JEIDA = 1, 174 DP_LVDS_FORMAT_LOC = 2, 175}; 176 177#define DEF_VOLTAGE_LEVEL (0x20) 178 179struct dp_lvds_dev { 180 enum dp_lvds_format lvds_format; /* 0:VESA, 1:JEIDA, 2: Location */ 181 int pol_inv_hs; /* hsync polarity invert for VESA, JEIDA */ 182 int pol_inv_vs; /* bsync polarity invert for VESA, JEIDA */ 183 int pol_inv_de; /* de polarity invert for VESA, JEIDA */ 184 int pol_inv_ck; /* input clock(pixel clock) polarity invert */ 185 int voltage_level; 186 /* Location setting */ 187 unsigned int loc_map[9]; /* Location Setting */ 188 unsigned int loc_mask[2]; /* Location Setting, 0 ~ 34 */ 189 unsigned int loc_pol[2]; /* Location Setting, 0 ~ 34 */ 190}; 191 192#include "mipi_display.h" 193 194struct dp_mipi_dev { 195 int lp_bitrate; /* to lcd setup, low power bitrate (150, 100, 80 Mhz) */ 196 int hs_bitrate; /* to lcd data, high speed bitrate (1000, ... Mhz) */ 197 int lpm_trans; 198 int command_mode; 199 unsigned int hs_pllpms; 200 unsigned int hs_bandctl; 201 unsigned int lp_pllpms; 202 unsigned int lp_bandctl; 203 struct mipi_dsi_device dsi; 204}; 205 206struct dp_rgb_dev { 207 int lcd_mpu_type; 208}; 209 210struct dp_hdmi_dev { 211 int preset; 212}; 213 214/* platform data for the driver model */ 215struct nx_display_plat { 216 int module; 217 struct dp_sync_info sync; 218 struct dp_ctrl_info ctrl; 219 struct dp_plane_top top; 220 struct dp_plane_info plane[DP_PLANS_NUM]; 221 int dev_type; 222 void *device; 223}; 224 225/* Lcd api */ 226void nx_lvds_display(int module, 227 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, 228 struct dp_plane_top *top, 229 struct dp_plane_info *planes, 230 struct dp_lvds_dev *dev); 231 232void nx_rgb_display(int module, 233 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, 234 struct dp_plane_top *top, struct dp_plane_info *planes, 235 struct dp_rgb_dev *dev); 236 237void nx_hdmi_display(int module, 238 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, 239 struct dp_plane_top *top, 240 struct dp_plane_info *planes, 241 struct dp_hdmi_dev *dev); 242 243void nx_mipi_display(int module, 244 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, 245 struct dp_plane_top *top, 246 struct dp_plane_info *planes, 247 struct dp_mipi_dev *dev); 248 249int nx_mipi_dsi_lcd_bind(struct mipi_dsi_device *dsi); 250 251/* disaply api */ 252void dp_control_init(int module); 253int dp_control_setup(int module, struct dp_sync_info *sync, 254 struct dp_ctrl_info *ctrl); 255void dp_control_enable(int module, int on); 256 257void dp_plane_init(int module); 258int dp_plane_screen_setup(int module, struct dp_plane_top *top); 259void dp_plane_screen_enable(int module, int on); 260 261int dp_plane_layer_setup(int module, struct dp_plane_info *plane); 262void dp_plane_layer_enable(int module, struct dp_plane_info *plane, int on); 263 264int dp_plane_set_enable(int module, int layer, int on); 265int dp_plane_set_address(int module, int layer, unsigned int address); 266int dp_plane_wait_vsync(int module, int layer, int fps); 267 268#if defined CONFIG_SPL_BUILD || \ 269 (!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL)) 270int nx_display_probe(struct nx_display_plat *plat); 271#endif 272 273#endif 274