1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 * Rockchip SD Host Controller Interface 6 */ 7 8#include <clk.h> 9#include <dm.h> 10#include <dm/ofnode.h> 11#include <dt-structs.h> 12#include <linux/delay.h> 13#include <linux/err.h> 14#include <linux/libfdt.h> 15#include <linux/iopoll.h> 16#include <malloc.h> 17#include <mapmem.h> 18#include "mmc_private.h" 19#include <sdhci.h> 20#include <syscon.h> 21#include <asm/arch-rockchip/clock.h> 22#include <asm/arch-rockchip/hardware.h> 23 24/* DWCMSHC specific Mode Select value */ 25#define DWCMSHC_CTRL_HS400 0x7 26/* 400KHz is max freq for card ID etc. Use that as min */ 27#define EMMC_MIN_FREQ 400000 28#define KHz (1000) 29#define MHz (1000 * KHz) 30#define SDHCI_TUNING_LOOP_COUNT 40 31 32#define PHYCTRL_CALDONE_MASK 0x1 33#define PHYCTRL_CALDONE_SHIFT 0x6 34#define PHYCTRL_CALDONE_DONE 0x1 35#define PHYCTRL_DLLRDY_MASK 0x1 36#define PHYCTRL_DLLRDY_SHIFT 0x5 37#define PHYCTRL_DLLRDY_DONE 0x1 38#define PHYCTRL_FREQSEL_200M 0x0 39#define PHYCTRL_FREQSEL_50M 0x1 40#define PHYCTRL_FREQSEL_100M 0x2 41#define PHYCTRL_FREQSEL_150M 0x3 42#define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \ 43 ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\ 44 PHYCTRL_DLLRDY_DONE) 45 46#define ARASAN_VENDOR_REGISTER 0x78 47#define ARASAN_VENDOR_ENHANCED_STROBE BIT(0) 48 49/* Rockchip specific Registers */ 50#define DWCMSHC_EMMC_EMMC_CTRL 0x52c 51#define DWCMSHC_CARD_IS_EMMC BIT(0) 52#define DWCMSHC_ENHANCED_STROBE BIT(8) 53#define DWCMSHC_EMMC_DLL_CTRL 0x800 54#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) 55#define DWCMSHC_EMMC_DLL_RXCLK 0x804 56#define DWCMSHC_EMMC_DLL_TXCLK 0x808 57#define DWCMSHC_EMMC_DLL_STRBIN 0x80c 58#define DWCMSHC_EMMC_DLL_CMDOUT 0x810 59#define DWCMSHC_EMMC_DLL_STATUS0 0x840 60#define DWCMSHC_EMMC_DLL_STATUS1 0x844 61#define DWCMSHC_EMMC_DLL_START BIT(0) 62#define DWCMSHC_EMMC_DLL_LOCKED BIT(8) 63#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) 64#define DWCMSHC_EMMC_DLL_START_POINT 16 65#define DWCMSHC_EMMC_DLL_START_DEFAULT 5 66#define DWCMSHC_EMMC_DLL_INC_VALUE 2 67#define DWCMSHC_EMMC_DLL_INC 8 68#define DWCMSHC_EMMC_DLL_BYPASS BIT(24) 69#define DWCMSHC_EMMC_DLL_DLYENA BIT(27) 70#define DLL_RXCLK_NO_INVERTER BIT(29) 71#define DLL_RXCLK_ORI_GATE BIT(31) 72#define DLL_TXCLK_TAPNUM_DEFAULT 0x10 73#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) 74#define DLL_TXCLK_NO_INVERTER BIT(29) 75#define DLL_STRBIN_TAPNUM_DEFAULT 0x4 76#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) 77#define DLL_STRBIN_DELAY_NUM_SEL BIT(26) 78#define DLL_STRBIN_DELAY_NUM_OFFSET 16 79#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x10 80#define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 81#define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) 82#define DLL_CMDOUT_SRC_CLK_NEG BIT(28) 83#define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) 84#define DLL_CMDOUT_BOTH_CLK_EDGE BIT(30) 85 86#define DLL_LOCK_WO_TMOUT(x) \ 87 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 88 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 89#define ROCKCHIP_MAX_CLKS 3 90 91#define FLAG_INVERTER_FLAG_IN_RXCLK BIT(0) 92 93struct rockchip_sdhc_plat { 94 struct mmc_config cfg; 95 struct mmc mmc; 96}; 97 98struct rockchip_emmc_phy { 99 u32 emmcphy_con[7]; 100 u32 reserved; 101 u32 emmcphy_status; 102}; 103 104struct rockchip_sdhc { 105 struct sdhci_host host; 106 struct udevice *dev; 107 void *base; 108 struct rockchip_emmc_phy *phy; 109 struct clk emmc_clk; 110}; 111 112struct sdhci_data { 113 int (*get_phy)(struct udevice *dev); 114 115 /** 116 * set_control_reg() - Set SDHCI control registers 117 * 118 * This is the set_control_reg() SDHCI operation that should be 119 * used for the hardware this driver data is associated with. 120 * Normally, this is used to set up control registers for 121 * voltage level and UHS speed mode. 122 * 123 * @host: SDHCI host structure 124 */ 125 void (*set_control_reg)(struct sdhci_host *host); 126 127 /** 128 * set_ios_post() - Host specific hook after set_ios() calls 129 * 130 * This is the set_ios_post() SDHCI operation that should be 131 * used for the hardware this driver data is associated with. 132 * Normally, this is a hook that is called after sdhci_set_ios() 133 * that does any necessary host-specific configuration. 134 * 135 * @host: SDHCI host structure 136 * Return: 0 if successful, -ve on error 137 */ 138 int (*set_ios_post)(struct sdhci_host *host); 139 140 void (*set_clock)(struct sdhci_host *host, u32 div); 141 int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable); 142 143 /** 144 * set_enhanced_strobe() - Set HS400 Enhanced Strobe config 145 * 146 * This is the set_enhanced_strobe() SDHCI operation that should 147 * be used for the hardware this driver data is associated with. 148 * Normally, this is used to set any host-specific configuration 149 * necessary for HS400 ES. 150 * 151 * @host: SDHCI host structure 152 * Return: 0 if successful, -ve on error 153 */ 154 int (*set_enhanced_strobe)(struct sdhci_host *host); 155 156 u32 flags; 157 u8 hs200_txclk_tapnum; 158 u8 hs400_txclk_tapnum; 159}; 160 161static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock) 162{ 163 u32 caldone, dllrdy, freqsel; 164 165 writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]); 166 writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]); 167 writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]); 168 169 /* 170 * According to the user manual, calpad calibration 171 * cycle takes more than 2us without the minimal recommended 172 * value, so we may need a little margin here 173 */ 174 udelay(3); 175 writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]); 176 177 /* 178 * According to the user manual, it asks driver to 179 * wait 5us for calpad busy trimming. But it seems that 180 * 5us of caldone isn't enough for all cases. 181 */ 182 udelay(500); 183 caldone = readl(&phy->emmcphy_status); 184 caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK; 185 if (caldone != PHYCTRL_CALDONE_DONE) { 186 printf("%s: caldone timeout.\n", __func__); 187 return; 188 } 189 190 /* Set the frequency of the DLL operation */ 191 if (clock < 75 * MHz) 192 freqsel = PHYCTRL_FREQSEL_50M; 193 else if (clock < 125 * MHz) 194 freqsel = PHYCTRL_FREQSEL_100M; 195 else if (clock < 175 * MHz) 196 freqsel = PHYCTRL_FREQSEL_150M; 197 else 198 freqsel = PHYCTRL_FREQSEL_200M; 199 200 /* Set the frequency of the DLL operation */ 201 writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]); 202 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]); 203 204 /* REN Enable on STRB Line for HS400 */ 205 writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]); 206 207 read_poll_timeout(readl, dllrdy, PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 208 5000, &phy->emmcphy_status); 209} 210 211static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy) 212{ 213 writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]); 214 writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]); 215} 216 217static int rk3399_emmc_get_phy(struct udevice *dev) 218{ 219 struct rockchip_sdhc *priv = dev_get_priv(dev); 220 ofnode phy_node; 221 void *grf_base; 222 u32 grf_phy_offset, phandle; 223 224 phandle = dev_read_u32_default(dev, "phys", 0); 225 phy_node = ofnode_get_by_phandle(phandle); 226 if (!ofnode_valid(phy_node)) { 227 debug("Not found emmc phy device\n"); 228 return -ENODEV; 229 } 230 231 grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 232 if (IS_ERR_OR_NULL(grf_base)) { 233 printf("%s Get syscon grf failed", __func__); 234 return -ENODEV; 235 } 236 grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0); 237 238 priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset); 239 240 return 0; 241} 242 243static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host) 244{ 245 struct mmc *mmc = host->mmc; 246 u32 vendor; 247 248 vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER); 249 if (mmc->selected_mode == MMC_HS_400_ES) 250 vendor |= ARASAN_VENDOR_ENHANCED_STROBE; 251 else 252 vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE; 253 sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER); 254 255 return 0; 256} 257 258static void rk3399_sdhci_set_control_reg(struct sdhci_host *host) 259{ 260 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 261 struct mmc *mmc = host->mmc; 262 uint clock = mmc->tran_speed; 263 int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ; 264 265 if (cycle_phy) 266 rk3399_emmc_phy_power_off(priv->phy); 267 268 sdhci_set_control_reg(host); 269 270 /* 271 * Reinitializing the device tries to set it to lower-speed modes 272 * first, which fails if the Enhanced Strobe bit is set, making 273 * the device impossible to use. Set the correct value here to 274 * let reinitialization attempts succeed. 275 */ 276 if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)) 277 rk3399_sdhci_set_enhanced_strobe(host); 278}; 279 280static int rk3399_sdhci_set_ios_post(struct sdhci_host *host) 281{ 282 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 283 struct mmc *mmc = host->mmc; 284 uint clock = mmc->tran_speed; 285 int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ; 286 287 if (!clock) 288 clock = mmc->clock; 289 290 if (cycle_phy) 291 rk3399_emmc_phy_power_on(priv->phy, clock); 292 293 return 0; 294} 295 296static void rk3568_sdhci_set_clock(struct sdhci_host *host, u32 div) 297{ 298 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 299 struct mmc *mmc = host->mmc; 300 ulong rate; 301 302 rate = clk_set_rate(&priv->emmc_clk, mmc->clock); 303 if (IS_ERR_VALUE(rate)) 304 printf("%s: Set clock rate failed: %ld\n", __func__, (long)rate); 305} 306 307static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable) 308{ 309 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 310 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 311 struct mmc *mmc = host->mmc; 312 int val, ret; 313 u32 extra, txclk_tapnum; 314 315 if (!enable) { 316 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); 317 return 0; 318 } 319 320 if (clock >= 100 * MHz) { 321 /* reset DLL */ 322 sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL); 323 udelay(1); 324 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); 325 326 /* Init DLL settings */ 327 extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT | 328 DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC | 329 DWCMSHC_EMMC_DLL_START; 330 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 331 332 ret = read_poll_timeout(readl, val, DLL_LOCK_WO_TMOUT(val), 1, 333 500, 334 host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0); 335 if (ret) 336 return ret; 337 338 extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE; 339 if (data->flags & FLAG_INVERTER_FLAG_IN_RXCLK) 340 extra |= DLL_RXCLK_NO_INVERTER; 341 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 342 343 txclk_tapnum = data->hs200_txclk_tapnum; 344 if (mmc->selected_mode == MMC_HS_400 || 345 mmc->selected_mode == MMC_HS_400_ES) { 346 txclk_tapnum = data->hs400_txclk_tapnum; 347 348 extra = DLL_CMDOUT_SRC_CLK_NEG | 349 DLL_CMDOUT_BOTH_CLK_EDGE | 350 DWCMSHC_EMMC_DLL_DLYENA | 351 DLL_CMDOUT_TAPNUM_90_DEGREES | 352 DLL_CMDOUT_TAPNUM_FROM_SW; 353 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT); 354 } 355 356 extra = DWCMSHC_EMMC_DLL_DLYENA | 357 DLL_TXCLK_TAPNUM_FROM_SW | 358 DLL_TXCLK_NO_INVERTER | 359 txclk_tapnum; 360 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); 361 362 extra = DWCMSHC_EMMC_DLL_DLYENA | 363 DLL_STRBIN_TAPNUM_DEFAULT | 364 DLL_STRBIN_TAPNUM_FROM_SW; 365 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 366 } else { 367 /* 368 * Disable DLL and reset both of sample and drive clock. 369 * The bypass bit and start bit need to be set if DLL is not locked. 370 */ 371 extra = DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START; 372 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 373 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); 374 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 375 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CMDOUT); 376 /* 377 * Before switching to hs400es mode, the driver will enable 378 * enhanced strobe first. PHY needs to configure the parameters 379 * of enhanced strobe first. 380 */ 381 extra = DWCMSHC_EMMC_DLL_DLYENA | 382 DLL_STRBIN_DELAY_NUM_SEL | 383 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; 384 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 385 } 386 387 return 0; 388} 389 390static int rk3568_sdhci_set_ios_post(struct sdhci_host *host) 391{ 392 struct mmc *mmc = host->mmc; 393 struct rockchip_sdhc_plat *plat = dev_get_plat(mmc->dev); 394 struct mmc_config *cfg = &plat->cfg; 395 u32 reg; 396 397 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); 398 reg &= ~SDHCI_CTRL_UHS_MASK; 399 400 switch (mmc->selected_mode) { 401 case UHS_SDR25: 402 case MMC_HS: 403 case MMC_HS_52: 404 reg |= SDHCI_CTRL_UHS_SDR25; 405 break; 406 case UHS_SDR50: 407 reg |= SDHCI_CTRL_UHS_SDR50; 408 break; 409 case UHS_DDR50: 410 case MMC_DDR_52: 411 reg |= SDHCI_CTRL_UHS_DDR50; 412 break; 413 case UHS_SDR104: 414 case MMC_HS_200: 415 reg |= SDHCI_CTRL_UHS_SDR104; 416 break; 417 case MMC_HS_400: 418 case MMC_HS_400_ES: 419 reg |= DWCMSHC_CTRL_HS400; 420 break; 421 default: 422 reg |= SDHCI_CTRL_UHS_SDR12; 423 } 424 425 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); 426 427 reg = sdhci_readw(host, DWCMSHC_EMMC_EMMC_CTRL); 428 429 if (IS_MMC(mmc)) 430 reg |= DWCMSHC_CARD_IS_EMMC; 431 else 432 reg &= ~DWCMSHC_CARD_IS_EMMC; 433 434 if (mmc->selected_mode == MMC_HS_400_ES) 435 reg |= DWCMSHC_ENHANCED_STROBE; 436 else 437 reg &= ~DWCMSHC_ENHANCED_STROBE; 438 439 sdhci_writew(host, reg, DWCMSHC_EMMC_EMMC_CTRL); 440 441 /* 442 * Reading more than 4 blocks with a single CMD18 command in PIO mode 443 * triggers Data End Bit Error using a slower mode than HS200. Limit to 444 * reading max 4 blocks in one command when using PIO mode. 445 */ 446 if (!(host->flags & USE_DMA)) { 447 if (mmc->selected_mode == MMC_HS_200 || 448 mmc->selected_mode == MMC_HS_400 || 449 mmc->selected_mode == MMC_HS_400_ES) 450 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 451 else 452 cfg->b_max = 4; 453 } 454 455 return 0; 456} 457 458static void rockchip_sdhci_set_control_reg(struct sdhci_host *host) 459{ 460 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 461 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 462 463 if (data->set_control_reg) 464 data->set_control_reg(host); 465} 466 467static int rockchip_sdhci_set_ios_post(struct sdhci_host *host) 468{ 469 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 470 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 471 472 if (data->set_ios_post) 473 return data->set_ios_post(host); 474 475 return 0; 476} 477 478static void rockchip_sdhci_set_clock(struct sdhci_host *host, u32 div) 479{ 480 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 481 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 482 483 if (data->set_clock) 484 data->set_clock(host, div); 485} 486 487static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) 488{ 489 struct rockchip_sdhc *priv = dev_get_priv(mmc->dev); 490 struct sdhci_host *host = &priv->host; 491 char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; 492 struct mmc_cmd cmd; 493 u32 ctrl, blk_size; 494 int ret; 495 496 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 497 ctrl |= SDHCI_CTRL_EXEC_TUNING; 498 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 499 500 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 501 502 blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64); 503 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8) 504 blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128); 505 sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE); 506 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 507 508 cmd.cmdidx = opcode; 509 cmd.resp_type = MMC_RSP_R1; 510 cmd.cmdarg = 0; 511 512 do { 513 ret = mmc_send_cmd(mmc, &cmd, NULL); 514 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 515 if (ret || tuning_loop_counter-- == 0) 516 break; 517 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 518 519 if (ret || tuning_loop_counter < 0 || !(ctrl & SDHCI_CTRL_TUNED_CLK)) { 520 if (!ret) 521 ret = -EIO; 522 printf("%s: Tuning failed: %d\n", __func__, ret); 523 524 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 525 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 526 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 527 } 528 529 /* Enable only interrupts served by the SD controller */ 530 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE); 531 532 return ret; 533} 534 535static int rockchip_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable) 536{ 537 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 538 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 539 540 if (data->config_dll) 541 return data->config_dll(host, clock, enable); 542 543 return 0; 544} 545 546static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host) 547{ 548 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 549 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 550 551 if (data->set_enhanced_strobe) 552 return data->set_enhanced_strobe(host); 553 554 return 0; 555} 556 557static struct sdhci_ops rockchip_sdhci_ops = { 558 .set_control_reg = rockchip_sdhci_set_control_reg, 559 .set_ios_post = rockchip_sdhci_set_ios_post, 560 .set_clock = rockchip_sdhci_set_clock, 561 .platform_execute_tuning = rockchip_sdhci_execute_tuning, 562 .config_dll = rockchip_sdhci_config_dll, 563 .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe, 564}; 565 566static int rockchip_sdhci_probe(struct udevice *dev) 567{ 568 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev); 569 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 570 struct rockchip_sdhc_plat *plat = dev_get_plat(dev); 571 struct rockchip_sdhc *priv = dev_get_priv(dev); 572 struct mmc_config *cfg = &plat->cfg; 573 struct sdhci_host *host = &priv->host; 574 struct clk clk; 575 int ret; 576 577 host->max_clk = cfg->f_max; 578 ret = clk_get_by_index(dev, 0, &clk); 579 if (!ret) { 580 ret = clk_set_rate(&clk, host->max_clk); 581 if (IS_ERR_VALUE(ret)) 582 printf("%s clk set rate fail!\n", __func__); 583 } else { 584 printf("%s fail to get clk\n", __func__); 585 } 586 587 priv->emmc_clk = clk; 588 priv->dev = dev; 589 590 if (data->get_phy) { 591 ret = data->get_phy(dev); 592 if (ret) 593 return ret; 594 } 595 596 host->ops = &rockchip_sdhci_ops; 597 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; 598 599 host->mmc = &plat->mmc; 600 host->mmc->priv = &priv->host; 601 host->mmc->dev = dev; 602 upriv->mmc = host->mmc; 603 604 ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ); 605 if (ret) 606 return ret; 607 608 /* 609 * Disable use of DMA and force use of PIO mode in SPL to fix an issue 610 * where loading part of TF-A into SRAM using DMA silently fails. 611 */ 612 if (IS_ENABLED(CONFIG_SPL_BUILD) && 613 dev_read_bool(dev, "u-boot,spl-fifo-mode")) 614 host->flags &= ~USE_DMA; 615 616 return sdhci_probe(dev); 617} 618 619static int rockchip_sdhci_of_to_plat(struct udevice *dev) 620{ 621 struct rockchip_sdhc_plat *plat = dev_get_plat(dev); 622 struct rockchip_sdhc *priv = dev_get_priv(dev); 623 struct mmc_config *cfg = &plat->cfg; 624 struct sdhci_host *host = &priv->host; 625 int ret; 626 627 host->name = dev->name; 628 host->ioaddr = dev_read_addr_ptr(dev); 629 630 ret = mmc_of_parse(dev, cfg); 631 if (ret) 632 return ret; 633 634 return 0; 635} 636 637static int rockchip_sdhci_bind(struct udevice *dev) 638{ 639 struct rockchip_sdhc_plat *plat = dev_get_plat(dev); 640 641 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 642} 643 644static const struct sdhci_data rk3399_data = { 645 .get_phy = rk3399_emmc_get_phy, 646 .set_control_reg = rk3399_sdhci_set_control_reg, 647 .set_ios_post = rk3399_sdhci_set_ios_post, 648 .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe, 649}; 650 651static const struct sdhci_data rk3568_data = { 652 .set_ios_post = rk3568_sdhci_set_ios_post, 653 .set_clock = rk3568_sdhci_set_clock, 654 .config_dll = rk3568_sdhci_config_dll, 655 .flags = FLAG_INVERTER_FLAG_IN_RXCLK, 656 .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, 657 .hs400_txclk_tapnum = 0x8, 658}; 659 660static const struct sdhci_data rk3588_data = { 661 .set_ios_post = rk3568_sdhci_set_ios_post, 662 .set_clock = rk3568_sdhci_set_clock, 663 .config_dll = rk3568_sdhci_config_dll, 664 .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, 665 .hs400_txclk_tapnum = 0x9, 666}; 667 668static const struct udevice_id sdhci_ids[] = { 669 { 670 .compatible = "arasan,sdhci-5.1", 671 .data = (ulong)&rk3399_data, 672 }, 673 { 674 .compatible = "rockchip,rk3568-dwcmshc", 675 .data = (ulong)&rk3568_data, 676 }, 677 { 678 .compatible = "rockchip,rk3588-dwcmshc", 679 .data = (ulong)&rk3588_data, 680 }, 681 { } 682}; 683 684U_BOOT_DRIVER(arasan_sdhci_drv) = { 685 .name = "rockchip_sdhci_5_1", 686 .id = UCLASS_MMC, 687 .of_match = sdhci_ids, 688 .of_to_plat = rockchip_sdhci_of_to_plat, 689 .ops = &sdhci_ops, 690 .bind = rockchip_sdhci_bind, 691 .probe = rockchip_sdhci_probe, 692 .priv_auto = sizeof(struct rockchip_sdhc), 693 .plat_auto = sizeof(struct rockchip_sdhc_plat), 694}; 695