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d678a59d |
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18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
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a2955579 |
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01-May-2024 |
Tom Rini <trini@konsulko.com> |
video: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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322c0da8 |
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17-May-2023 |
Michal Simek <michal.simek@amd.com> |
video: zynqmp: Enable 1024x768 resolution Add support for 1024x768 60p resolution and set it up this resolution by default. This resolution is still able to use only one GT line. But for example 800x600 60p has some issues with settings. That's why extend this table by tested resolutions. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/957e1e85a05744326ec2606dadc1af6e69976f37.1684312924.git.michal.simek@amd.com |
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a29f44d6 |
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17-May-2023 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> |
video: zynqmp: Driver for Xilinx ZynqMP DisplayPort Subsystem The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort Subsystem. It includes a buffer manager, blender, an audio mixer and a DisplayPort source controller (transmitter). The DisplayPort controller can source data from memory (non-live input) or the stream (live input). The DisplayPort controller is responsible for managing the link and physical layer functionality. The controller packs audio/video data into transfer units and sends them over the main link. The link rate and lane counts can be selected based on the application bandwidth requirements. The DisplayPort pipeline consists of the DisplayPort direct memory access (DMA) for fetching data from memory. The DisplayPort DMA controller (DPDMA) supports up to six input channels as non-live input. This driver supports the DisplayPort Subsystem and implements 1)640x480 resolution 2)RGBA8888 32bpp format 3)DPDMA channel 3 for Graphics 4)Non-live input 5)Fixed 5.4G link rate 6)Tested on ZCU102 board There will be additional work to configure GT lines based on DT, higher resolutions, support for more compressed video formats, spliting code to more files, add support for EDID, audio support, using clock framework for all clocks and in general code clean up. Codevelop-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5c1567b63d0280dacc7efba2998857c399c25358.1684312924.git.michal.simek@amd.com |
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c4865e16 |
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17-May-2023 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> |
video: move zynqmp files to subdirectory Place zynqmp files and headers in custom driver subdirectory. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9aae6d217f0673c310818e3de38bb239c79c060c.1684312924.git.michal.simek@amd.com |
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a2955579 |
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01-May-2024 |
Tom Rini <trini@konsulko.com> |
video: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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322c0da8 |
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17-May-2023 |
Michal Simek <michal.simek@amd.com> |
video: zynqmp: Enable 1024x768 resolution Add support for 1024x768 60p resolution and set it up this resolution by default. This resolution is still able to use only one GT line. But for example 800x600 60p has some issues with settings. That's why extend this table by tested resolutions. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/957e1e85a05744326ec2606dadc1af6e69976f37.1684312924.git.michal.simek@amd.com |
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a29f44d6 |
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17-May-2023 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> |
video: zynqmp: Driver for Xilinx ZynqMP DisplayPort Subsystem The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort Subsystem. It includes a buffer manager, blender, an audio mixer and a DisplayPort source controller (transmitter). The DisplayPort controller can source data from memory (non-live input) or the stream (live input). The DisplayPort controller is responsible for managing the link and physical layer functionality. The controller packs audio/video data into transfer units and sends them over the main link. The link rate and lane counts can be selected based on the application bandwidth requirements. The DisplayPort pipeline consists of the DisplayPort direct memory access (DMA) for fetching data from memory. The DisplayPort DMA controller (DPDMA) supports up to six input channels as non-live input. This driver supports the DisplayPort Subsystem and implements 1)640x480 resolution 2)RGBA8888 32bpp format 3)DPDMA channel 3 for Graphics 4)Non-live input 5)Fixed 5.4G link rate 6)Tested on ZCU102 board There will be additional work to configure GT lines based on DT, higher resolutions, support for more compressed video formats, spliting code to more files, add support for EDID, audio support, using clock framework for all clocks and in general code clean up. Codevelop-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5c1567b63d0280dacc7efba2998857c399c25358.1684312924.git.michal.simek@amd.com |
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c4865e16 |
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17-May-2023 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> |
video: move zynqmp files to subdirectory Place zynqmp files and headers in custom driver subdirectory. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9aae6d217f0673c310818e3de38bb239c79c060c.1684312924.git.michal.simek@amd.com |
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322c0da8 |
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17-May-2023 |
Michal Simek <michal.simek@amd.com> |
video: zynqmp: Enable 1024x768 resolution Add support for 1024x768 60p resolution and set it up this resolution by default. This resolution is still able to use only one GT line. But for example 800x600 60p has some issues with settings. That's why extend this table by tested resolutions. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/957e1e85a05744326ec2606dadc1af6e69976f37.1684312924.git.michal.simek@amd.com |
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a29f44d6 |
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17-May-2023 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> |
video: zynqmp: Driver for Xilinx ZynqMP DisplayPort Subsystem The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort Subsystem. It includes a buffer manager, blender, an audio mixer and a DisplayPort source controller (transmitter). The DisplayPort controller can source data from memory (non-live input) or the stream (live input). The DisplayPort controller is responsible for managing the link and physical layer functionality. The controller packs audio/video data into transfer units and sends them over the main link. The link rate and lane counts can be selected based on the application bandwidth requirements. The DisplayPort pipeline consists of the DisplayPort direct memory access (DMA) for fetching data from memory. The DisplayPort DMA controller (DPDMA) supports up to six input channels as non-live input. This driver supports the DisplayPort Subsystem and implements 1)640x480 resolution 2)RGBA8888 32bpp format 3)DPDMA channel 3 for Graphics 4)Non-live input 5)Fixed 5.4G link rate 6)Tested on ZCU102 board There will be additional work to configure GT lines based on DT, higher resolutions, support for more compressed video formats, spliting code to more files, add support for EDID, audio support, using clock framework for all clocks and in general code clean up. Codevelop-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5c1567b63d0280dacc7efba2998857c399c25358.1684312924.git.michal.simek@amd.com |
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c4865e16 |
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17-May-2023 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> |
video: move zynqmp files to subdirectory Place zynqmp files and headers in custom driver subdirectory. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9aae6d217f0673c310818e3de38bb239c79c060c.1684312924.git.michal.simek@amd.com |