Searched refs:enable (Results 251 - 275 of 551) sorted by relevance

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/u-boot/arch/mips/mach-octeon/include/mach/
H A Dcvmx-helper-cfg.h59 * enable/disable DWB.
120 bool enable_fec : 1; /** True to enable FEC for 10/40G links */
554 * @param enable true to enable autonegotiation, false to force full
557 void cvmx_helper_set_port_autonegotiation(int xiface, int index, bool enable);
587 * @param enable true to enable fec, false to disable.
589 void cvmx_helper_set_port_fec(int xiface, int index, bool enable);
639 * @param tx_vboost vboost enable (1 = enable,
[all...]
/u-boot/drivers/clk/imx/
H A Dclk-imx8qm.c259 int __imx8_clk_enable(struct clk *clk, bool enable) argument
354 ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
H A Dclk-imx8qxp.c243 int __imx8_clk_enable(struct clk *clk, bool enable) argument
328 ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
/u-boot/drivers/dma/
H A Ddma-uclass.c144 if (!ops->enable)
147 return ops->enable(dma);
/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3328.c189 /* enable the write to the equivalent lower bits */
230 /* enable the write to the equivalent lower bits */
261 int pin_num, int enable)
269 /* enable the write to the equivalent lower bits */
270 data = BIT(bit + 16) | (enable << bit);
260 rk3328_set_schmitt(struct rockchip_pin_bank *bank, int pin_num, int enable) argument
H A Dpinctrl-rv1108.c152 /* enable the write to the equivalent lower bits */
204 /* enable the write to the equivalent lower bits */
243 int pin_num, int enable)
251 /* enable the write to the equivalent lower bits */
252 data = BIT(bit + 16) | (enable << bit);
242 rv1108_set_schmitt(struct rockchip_pin_bank *bank, int pin_num, int enable) argument
/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c69 void enable_ocotp_clk(unsigned char enable) argument
71 clock_enable(CCGR_OCOTP, enable);
80 void enable_usboh3_clk(unsigned char enable) argument
84 if (enable) {
95 /* enable the clock gate */
528 int enable_i2c_clk(unsigned char enable, unsigned i2c_num) argument
535 if (enable) {
580 /* enable the clock gate */
635 /* enable the clock gate */
658 /* enable th
1082 hab_caam_clock_enable(unsigned char enable) argument
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/u-boot/drivers/power/acpi_pmc/
H A Dacpi-pmc-uclass.c176 int pmc_global_reset_set_enable(struct udevice *dev, bool enable) argument
183 return ops->global_reset_set_enable(dev, enable);
/u-boot/drivers/pwm/
H A Dpwm-aspeed.c38 * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
101 static int aspeed_pwm_set_enable(struct udevice *dev, uint channel, bool enable) argument
110 enable ? PWM_ASPEED_CTRL_PIN_ENABLE : 0);
H A Drk_pwm.c104 static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable) argument
115 if (enable)
H A Dpwm-mtk.c129 static int mtk_pwm_set_enable(struct udevice *dev, uint channel, bool enable) argument
135 if (enable)
/u-boot/drivers/usb/host/
H A Dehci-mxs.c34 static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable) argument
40 if (enable) {
/u-boot/drivers/gpio/
H A Domap_gpio.c87 int enable)
92 if (enable)
86 _set_gpio_dataout(const struct gpio_bank *bank, int gpio, int enable) argument
/u-boot/drivers/clk/at91/
H A Dclk-peripheral.c82 .enable = clk_peripheral_enable,
209 .enable = clk_sam9x5_peripheral_enable,
/u-boot/drivers/mmc/
H A Dzynq_sdhci.c165 * @enable: Enable or disable Delay chain based Tx and Rx clock
171 static void arasan_phy_set_delaychain(struct sdhci_host *host, bool enable) argument
176 if (enable)
188 * @enable: Enable or disable DLL clock
191 * Enable or disable eMMC DLL clock in PHY_CTRL_REG2. When DLL enable is
194 static int arasan_phy_set_dll(struct sdhci_host *host, bool enable) argument
199 if (enable)
207 if (!enable)
249 static int arasan_sdhci_config_dll(struct sdhci_host *host, unsigned int clock, bool enable) argument
254 if (enable) {
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/u-boot/arch/x86/cpu/apollolake/
H A Dpmc.c93 static int apl_global_reset_set_enable(struct udevice *dev, bool enable) argument
97 if (enable)
170 * Set PMC base addresses and enable decoding. BARs 1 and 3 are 64-bit
/u-boot/arch/arm/mach-tegra/
H A Dxusb-padctl-common.c27 if (phy && phy->ops && phy->ops->enable)
28 return phy->ops->enable(phy);
/u-boot/drivers/video/nexell/soc/
H A Ds5pxx18_soc_disptop.h364 void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,
381 void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,
/u-boot/arch/arm/mach-uniphier/dram/
H A Dumc-pxs2.c76 static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable) argument
82 if (enable)
89 if (!enable) {
372 /* reflect ZQ settings and enable average algorithm*/
440 /* enable/disable auto refresh */
441 static void umc_refresh_ctrl(void __iomem *dc_base, int enable) argument
448 if (enable)
/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr4_mpr_pda_if.c100 /* dll enable */
187 * enable MPR page 2 mpr mode in DDR4 MR3
329 * enable MPR page 2 mpr mode in DDR4 MR3
434 int mv_ddr4_vref_training_mode_ctrl(u8 dev_num, u8 if_id, enum hws_access_type access_type, int enable) argument
447 val = (((enable == 1) ? 1 : 0) << 7);
481 /* disable and then enable the training with a new range */
499 /* 1 to enable */
504 /* 1 to enable */
513 /* 1 to enable */
537 * set vdq tr, 0x1918[6] to 0x0 to disable or 0x1 to enable
629 mv_ddr4_pda_ctrl(u8 dev_num, u8 if_id, u8 cs_num, int enable) argument
[all...]
/u-boot/lib/acpi/
H A Dacpi_device.c401 struct acpi_gpio reset, enable, stop; local
406 gpio_get_acpi(enable_gpio, &enable);
409 has_enable = enable.pins[0];
432 dw0_write, &enable, true);
476 dw0_write, &enable, false);
/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c314 void hab_caam_clock_enable(unsigned char enable) argument
321 void enable_ocotp_clk(unsigned char enable) argument
323 clock_enable(CCGR_OCOTP, !!enable);
327 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) argument
333 clock_enable(CCGR_I2C1 + i2c_num, !!enable);
557 /* enable clock */
762 * Here we only enable the outputs.
H A Dclock_imx8mm.c27 void hab_caam_clock_enable(unsigned char enable) argument
33 void enable_ocotp_clk(unsigned char enable) argument
35 clock_enable(CCGR_OCOTP, !!enable);
38 int enable_i2c_clk(unsigned char enable, unsigned i2c_num) argument
50 clock_enable(i2c_ccgr[i2c_num], !!enable);
433 * Here we only enable the outputs.
/u-boot/drivers/spi/
H A Dspi-qup.c185 static int qup_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable) argument
189 debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
198 enable = !enable;
200 return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
260 * Function to configure Input and Output enable/disable
373 /* Configure input and output enable */
460 /* Configure input and output enable */
H A Dstm32_spi.c271 static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable) argument
276 dev_dbg(dev, "cs=%d enable=%d\n", cs, enable);
285 enable = !enable;
287 return dm_gpio_set_value(&plat->cs_gpios[cs], enable ? 1 : 0);
550 /* enable clock */

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