1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. 4 * 5 * Author: Sam Shih <sam.shih@mediatek.com> 6 */ 7 8#include <common.h> 9#include <clk.h> 10#include <dm.h> 11#include <pwm.h> 12#include <div64.h> 13#include <linux/bitops.h> 14#include <linux/io.h> 15#include <linux/time.h> 16 17/* PWM registers and bits definitions */ 18#define PWMCON 0x00 19#define PWMHDUR 0x04 20#define PWMLDUR 0x08 21#define PWMGDUR 0x0c 22#define PWMWAVENUM 0x28 23#define PWMDWIDTH 0x2c 24#define PWM45DWIDTH_FIXUP 0x30 25#define PWMTHRES 0x30 26#define PWM45THRES_FIXUP 0x34 27 28#define PWM_CLK_DIV_MAX 7 29#define MAX_PWM_NUM 8 30 31enum mtk_pwm_reg_ver { 32 PWM_REG_V1, 33 PWM_REG_V2, 34}; 35 36static const unsigned int mtk_pwm_reg_offset_v1[] = { 37 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 38}; 39 40static const unsigned int mtk_pwm_reg_offset_v2[] = { 41 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 42}; 43 44struct mtk_pwm_soc { 45 unsigned int num_pwms; 46 bool pwm45_fixup; 47 enum mtk_pwm_reg_ver reg_ver; 48}; 49 50struct mtk_pwm_priv { 51 void __iomem *base; 52 struct clk top_clk; 53 struct clk main_clk; 54 struct clk pwm_clks[MAX_PWM_NUM]; 55 const struct mtk_pwm_soc *soc; 56}; 57 58static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val) 59{ 60 struct mtk_pwm_priv *priv = dev_get_priv(dev); 61 u32 offset; 62 63 switch (priv->soc->reg_ver) { 64 case PWM_REG_V2: 65 offset = mtk_pwm_reg_offset_v2[channel]; 66 break; 67 68 default: 69 offset = mtk_pwm_reg_offset_v1[channel]; 70 } 71 72 writel(val, priv->base + offset + reg); 73} 74 75static int mtk_pwm_set_config(struct udevice *dev, uint channel, 76 uint period_ns, uint duty_ns) 77{ 78 struct mtk_pwm_priv *priv = dev_get_priv(dev); 79 u32 clkdiv = 0, clksel = 0, cnt_period, cnt_duty, 80 reg_width = PWMDWIDTH, reg_thres = PWMTHRES; 81 u64 resolution; 82 int ret = 0; 83 84 clk_enable(&priv->top_clk); 85 clk_enable(&priv->main_clk); 86 /* Using resolution in picosecond gets accuracy higher */ 87 resolution = (u64)NSEC_PER_SEC * 1000; 88 do_div(resolution, clk_get_rate(&priv->pwm_clks[channel])); 89 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); 90 while (cnt_period > 8191) { 91 resolution *= 2; 92 clkdiv++; 93 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, 94 resolution); 95 if (clkdiv > PWM_CLK_DIV_MAX && clksel == 0) { 96 clksel = 1; 97 clkdiv = 0; 98 resolution = (u64)NSEC_PER_SEC * 1000 * 1625; 99 do_div(resolution, 100 clk_get_rate(&priv->pwm_clks[channel])); 101 cnt_period = DIV_ROUND_CLOSEST_ULL( 102 (u64)period_ns * 1000, resolution); 103 clk_enable(&priv->pwm_clks[channel]); 104 } 105 } 106 if (clkdiv > PWM_CLK_DIV_MAX && clksel == 1) { 107 printf("pwm period %u not supported\n", period_ns); 108 return -EINVAL; 109 } 110 if (priv->soc->pwm45_fixup && channel > 2) { 111 /* 112 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES 113 * from the other PWMs on MT7623. 114 */ 115 reg_width = PWM45DWIDTH_FIXUP; 116 reg_thres = PWM45THRES_FIXUP; 117 } 118 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); 119 if (clksel == 1) 120 mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | BIT(3) | clkdiv); 121 else 122 mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | clkdiv); 123 mtk_pwm_w32(dev, channel, reg_width, cnt_period); 124 mtk_pwm_w32(dev, channel, reg_thres, cnt_duty); 125 126 return ret; 127}; 128 129static int mtk_pwm_set_enable(struct udevice *dev, uint channel, bool enable) 130{ 131 struct mtk_pwm_priv *priv = dev_get_priv(dev); 132 u32 val = 0; 133 134 val = readl(priv->base); 135 if (enable) 136 val |= BIT(channel); 137 else 138 val &= ~BIT(channel); 139 writel(val, priv->base); 140 141 return 0; 142}; 143 144static int mtk_pwm_probe(struct udevice *dev) 145{ 146 struct mtk_pwm_priv *priv = dev_get_priv(dev); 147 int ret = 0; 148 int i; 149 150 priv->soc = (struct mtk_pwm_soc *)dev_get_driver_data(dev); 151 priv->base = dev_read_addr_ptr(dev); 152 if (!priv->base) 153 return -EINVAL; 154 ret = clk_get_by_name(dev, "top", &priv->top_clk); 155 if (ret < 0) 156 return ret; 157 ret = clk_get_by_name(dev, "main", &priv->main_clk); 158 if (ret < 0) 159 return ret; 160 for (i = 0; i < priv->soc->num_pwms; i++) { 161 char name[8]; 162 163 snprintf(name, sizeof(name), "pwm%d", i + 1); 164 ret = clk_get_by_name(dev, name, &priv->pwm_clks[i]); 165 if (ret < 0) 166 return ret; 167 } 168 169 return ret; 170} 171 172static const struct pwm_ops mtk_pwm_ops = { 173 .set_config = mtk_pwm_set_config, 174 .set_enable = mtk_pwm_set_enable, 175}; 176 177static const struct mtk_pwm_soc mt7622_data = { 178 .num_pwms = 6, 179 .pwm45_fixup = false, 180 .reg_ver = PWM_REG_V1, 181}; 182 183static const struct mtk_pwm_soc mt7623_data = { 184 .num_pwms = 5, 185 .pwm45_fixup = true, 186 .reg_ver = PWM_REG_V1, 187}; 188 189static const struct mtk_pwm_soc mt7629_data = { 190 .num_pwms = 1, 191 .pwm45_fixup = false, 192 .reg_ver = PWM_REG_V1, 193}; 194 195static const struct mtk_pwm_soc mt7981_data = { 196 .num_pwms = 2, 197 .pwm45_fixup = false, 198 .reg_ver = PWM_REG_V2, 199}; 200 201static const struct mtk_pwm_soc mt7986_data = { 202 .num_pwms = 2, 203 .pwm45_fixup = false, 204 .reg_ver = PWM_REG_V1, 205}; 206 207static const struct mtk_pwm_soc mt7988_data = { 208 .num_pwms = 8, 209 .pwm45_fixup = false, 210 .reg_ver = PWM_REG_V2, 211}; 212 213static const struct udevice_id mtk_pwm_ids[] = { 214 { .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data }, 215 { .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data }, 216 { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data }, 217 { .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data }, 218 { .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data }, 219 { .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data }, 220 { } 221}; 222 223U_BOOT_DRIVER(mtk_pwm) = { 224 .name = "mtk_pwm", 225 .id = UCLASS_PWM, 226 .of_match = mtk_pwm_ids, 227 .ops = &mtk_pwm_ops, 228 .probe = mtk_pwm_probe, 229 .priv_auto = sizeof(struct mtk_pwm_priv), 230}; 231