1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Freescale i.MX28 USB Host driver 4 * 5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * on behalf of DENX Software Engineering GmbH 7 */ 8 9#include <common.h> 10#include <asm/io.h> 11#include <asm/arch/imx-regs.h> 12#include <errno.h> 13#include <linux/delay.h> 14#include <dm.h> 15#include <power/regulator.h> 16 17#include "ehci.h" 18 19/* This DIGCTL register ungates clock to USB */ 20#define HW_DIGCTL_CTRL 0x8001c000 21#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2) 22#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16) 23 24struct ehci_mxs_port { 25 uint32_t usb_regs; 26 struct mxs_usbphy_regs *phy_regs; 27 28 struct mxs_register_32 *pll; 29 uint32_t pll_en_bits; 30 uint32_t pll_dis_bits; 31 uint32_t gate_bits; 32}; 33 34static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable) 35{ 36 struct mxs_register_32 *digctl_ctrl = 37 (struct mxs_register_32 *)HW_DIGCTL_CTRL; 38 int pll_offset, dig_offset; 39 40 if (enable) { 41 pll_offset = offsetof(struct mxs_register_32, reg_set); 42 dig_offset = offsetof(struct mxs_register_32, reg_clr); 43 writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset); 44 writel(port->pll_en_bits, (u32)port->pll + pll_offset); 45 } else { 46 pll_offset = offsetof(struct mxs_register_32, reg_clr); 47 dig_offset = offsetof(struct mxs_register_32, reg_set); 48 writel(port->pll_dis_bits, (u32)port->pll + pll_offset); 49 writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset); 50 } 51 52 return 0; 53} 54 55static int __ehci_hcd_init(struct ehci_mxs_port *port, enum usb_init_type init, 56 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 57{ 58 u32 usb_base, cap_base; 59 int ret; 60 61 /* Reset the PHY block */ 62 writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set); 63 udelay(10); 64 writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, 65 &port->phy_regs->hw_usbphy_ctrl_clr); 66 67 /* Enable USB clock */ 68 ret = ehci_mxs_toggle_clock(port, 1); 69 if (ret) 70 return ret; 71 72 /* Start USB PHY */ 73 writel(0, &port->phy_regs->hw_usbphy_pwd); 74 75 /* Enable UTMI+ Level 2 and Level 3 compatibility */ 76 writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1, 77 &port->phy_regs->hw_usbphy_ctrl_set); 78 79 usb_base = port->usb_regs + 0x100; 80 *hccr = (struct ehci_hccr *)usb_base; 81 82 cap_base = ehci_readl(&(*hccr)->cr_capbase); 83 *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base)); 84 85 return 0; 86} 87 88static int __ehci_hcd_stop(struct ehci_mxs_port *port) 89{ 90 u32 usb_base, cap_base, tmp; 91 struct ehci_hccr *hccr; 92 struct ehci_hcor *hcor; 93 94 /* Stop the USB port */ 95 usb_base = port->usb_regs + 0x100; 96 hccr = (struct ehci_hccr *)usb_base; 97 cap_base = ehci_readl(&hccr->cr_capbase); 98 hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base)); 99 100 tmp = ehci_readl(&hcor->or_usbcmd); 101 tmp &= ~CMD_RUN; 102 ehci_writel(&hcor->or_usbcmd, tmp); 103 104 /* Disable the PHY */ 105 tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF | 106 USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV | 107 USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS | 108 USBPHY_PWD_TXPWDFS; 109 writel(tmp, &port->phy_regs->hw_usbphy_pwd); 110 111 /* Disable USB clock */ 112 return ehci_mxs_toggle_clock(port, 0); 113} 114 115struct ehci_mxs_priv_data { 116 struct ehci_ctrl ctrl; 117 struct usb_ehci *ehci; 118 struct udevice *vbus_supply; 119 struct ehci_mxs_port port; 120 enum usb_init_type init_type; 121}; 122 123/* 124 * Below defines correspond to imx28 clk Linux (v5.15.y) 125 * clock driver to provide proper offset for PHY[01] 126 * devices. 127 */ 128#define CLK_USB_PHY0 62 129#define CLK_USB_PHY1 63 130#define PLL0CTRL0(base) ((base) + 0x0000) 131#define PLL1CTRL0(base) ((base) + 0x0020) 132 133static int ehci_usb_ofdata_to_platdata(struct udevice *dev) 134{ 135 struct ehci_mxs_priv_data *priv = dev_get_priv(dev); 136 struct usb_plat *plat = dev_get_plat(dev); 137 struct ehci_mxs_port *port = &priv->port; 138 u32 phandle, phy_reg, clk_reg, clk_id; 139 ofnode np = dev_ofnode(dev); 140 ofnode phy_node, clk_node; 141 const char *mode; 142 int ret; 143 144 mode = ofnode_read_string(np, "dr_mode"); 145 if (mode) { 146 if (strcmp(mode, "peripheral") == 0) 147 plat->init_type = USB_INIT_DEVICE; 148 else if (strcmp(mode, "host") == 0) 149 plat->init_type = USB_INIT_HOST; 150 else 151 return -EINVAL; 152 } 153 154 /* Read base address of the USB IP block */ 155 ret = ofnode_read_u32(np, "reg", &port->usb_regs); 156 if (ret) 157 return ret; 158 159 /* Read base address of the USB PHY IP block */ 160 ret = ofnode_read_u32(np, "fsl,usbphy", &phandle); 161 if (ret) 162 return ret; 163 164 phy_node = ofnode_get_by_phandle(phandle); 165 if (!ofnode_valid(phy_node)) 166 return -ENODEV; 167 168 ret = ofnode_read_u32(phy_node, "reg", &phy_reg); 169 if (ret) 170 return ret; 171 172 port->phy_regs = (struct mxs_usbphy_regs *)phy_reg; 173 174 /* Read base address of the CLK IP block and proper ID */ 175 ret = ofnode_read_u32_index(phy_node, "clocks", 0, &phandle); 176 if (ret) 177 return ret; 178 179 ret = ofnode_read_u32_index(phy_node, "clocks", 1, &clk_id); 180 if (ret) 181 return ret; 182 183 clk_node = ofnode_get_by_phandle(phandle); 184 if (!ofnode_valid(clk_node)) 185 return -ENODEV; 186 187 ret = ofnode_read_u32(clk_node, "reg", &clk_reg); 188 if (ret) 189 return ret; 190 191 port->pll = (struct mxs_register_32 *)clk_reg; 192 193 /* Provide proper offset for USB PHY clocks */ 194 if (clk_id == CLK_USB_PHY0) 195 port->pll = PLL0CTRL0(port->pll); 196 197 if (clk_id == CLK_USB_PHY1) 198 port->pll = PLL1CTRL0(port->pll); 199 200 debug("%s: pll_reg: 0x%p clk_id: %d\n", __func__, port->pll, clk_id); 201 /* 202 * On the imx28 the values provided by CLKCTRL_PLL0* defines to are the 203 * same as ones for CLKCTRL_PLL1*. As a result the former can be used 204 * for both ports - i.e. (usb[01]). 205 */ 206 port->pll_en_bits = CLKCTRL_PLL0CTRL0_EN_USB_CLKS | 207 CLKCTRL_PLL0CTRL0_POWER; 208 port->pll_dis_bits = CLKCTRL_PLL0CTRL0_EN_USB_CLKS; 209 port->gate_bits = HW_DIGCTL_CTRL_USB0_CLKGATE; 210 211 return 0; 212} 213 214static int ehci_usb_probe(struct udevice *dev) 215{ 216 struct usb_plat *plat = dev_get_plat(dev); 217 struct usb_ehci *ehci = dev_read_addr_ptr(dev); 218 struct ehci_mxs_priv_data *priv = dev_get_priv(dev); 219 struct ehci_mxs_port *port = &priv->port; 220 enum usb_init_type type = plat->init_type; 221 struct ehci_hccr *hccr; 222 struct ehci_hcor *hcor; 223 int ret; 224 225 priv->ehci = ehci; 226 priv->init_type = type; 227 228 debug("%s: USB type: %s reg: 0x%x phy_reg 0x%p\n", __func__, 229 type == USB_INIT_HOST ? "HOST" : "DEVICE", port->usb_regs, 230 (uint32_t *)port->phy_regs); 231 232#if CONFIG_IS_ENABLED(DM_REGULATOR) 233 ret = device_get_supply_regulator(dev, "vbus-supply", 234 &priv->vbus_supply); 235 if (ret) 236 debug("%s: No vbus supply\n", dev->name); 237 238 if (!ret && priv->vbus_supply) { 239 ret = regulator_set_enable_if_allowed(priv->vbus_supply, 240 (type == USB_INIT_DEVICE) ? 241 false : true); 242 if (ret) { 243 puts("Error enabling VBUS supply\n"); 244 return ret; 245 } 246 } 247#endif 248 ret = __ehci_hcd_init(port, type, &hccr, &hcor); 249 if (ret) 250 return ret; 251 252 mdelay(10); 253 return ehci_register(dev, hccr, hcor, NULL, 0, priv->init_type); 254} 255 256static int ehci_usb_remove(struct udevice *dev) 257{ 258 struct ehci_mxs_priv_data *priv = dev_get_priv(dev); 259 struct ehci_mxs_port *port = &priv->port; 260 int ret; 261 262 ret = ehci_deregister(dev); 263 if (ret) 264 return ret; 265 266#if CONFIG_IS_ENABLED(DM_REGULATOR) 267 if (priv->vbus_supply) { 268 ret = regulator_set_enable_if_allowed(priv->vbus_supply, false); 269 if (ret) { 270 puts("Error disabling VBUS supply\n"); 271 return ret; 272 } 273 } 274#endif 275 return __ehci_hcd_stop(port); 276} 277 278static const struct udevice_id mxs_usb_ids[] = { 279 { .compatible = "fsl,imx28-usb" }, 280 { } 281}; 282 283U_BOOT_DRIVER(usb_mxs) = { 284 .name = "ehci_mxs", 285 .id = UCLASS_USB, 286 .of_match = mxs_usb_ids, 287 .of_to_plat = ehci_usb_ofdata_to_platdata, 288 .probe = ehci_usb_probe, 289 .remove = ehci_usb_remove, 290 .ops = &ehci_usb_ops, 291 .plat_auto = sizeof(struct usb_plat), 292 .priv_auto = sizeof(struct ehci_mxs_priv_data), 293 .flags = DM_FLAG_ALLOC_PRIV_DMA, 294}; 295